From 22242681cff52bfb7cba5d2a37b91802be7a4e4c Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 2 Nov 2009 12:00:01 +0100 Subject: MIPS: Extend COMMAND_LINE_SIZE Some firmware may pass well over 256 bytes these days. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/setup.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e600cedda97..50511aac04e 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -1,7 +1,7 @@ #ifndef _MIPS_SETUP_H #define _MIPS_SETUP_H -#define COMMAND_LINE_SIZE 256 +#define COMMAND_LINE_SIZE 4096 #ifdef __KERNEL__ extern void setup_early_printk(void); -- cgit v1.2.3 From d30cecbcbe149a36a354757cea835c1bb28689cf Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 27 May 2009 17:29:37 +0100 Subject: MIPS: Don't write ones to reserved entryhi bits. We've silently been relying on the hardware chopping off excess, reserved ASID bits for no better reason that it saving an instruction. Because we already have: #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) in . We can use a cleanup to avoid writing non-zero bits into the reserved entryhi bits. This avoid triggering some debugging assertion in the Cavium simulator. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mmu_context.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d9743536a62..ed331c2e488 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -165,12 +165,12 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * having ASID_MASK smaller than the hardware maximum, * make sure no "soft" bits become "hard"... */ - write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) - | (cpu_context(cpu, next) & ASID_MASK)); + write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | + cpu_asid(cpu, next)); ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_asid(cpu, next)); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); @@ -226,11 +226,11 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) } /* See comments for similar code above */ write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) | - (cpu_context(cpu, next) & ASID_MASK)); + cpu_asid(cpu, next)); ehb(); /* Make sure it propagates to TCStatus */ evpe(mtflags); #else - write_c0_entryhi(cpu_context(cpu, next)); + write_c0_entryhi(cpu_asid(cpu, next)); #endif /* CONFIG_MIPS_MT_SMTC */ TLBMISS_HANDLER_SETUP_PGD(next->pgd); -- cgit v1.2.3 From 067f3290f7508f492e2f838222766fa1874606c5 Mon Sep 17 00:00:00 2001 From: David Daney Date: Thu, 1 Oct 2009 16:47:38 -0700 Subject: MIPS: Octeon: Fix compile error in arch/mips/cavium-octeon/smp.c Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/smp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index 32d51a31dc4..c198efdf583 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -65,11 +65,12 @@ void octeon_send_ipi_single(int cpu, unsigned int action) cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); } -static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) +static inline void octeon_send_ipi_mask(const struct cpumask *mask, + unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu_mask(i, *mask) octeon_send_ipi_single(i, action); } -- cgit v1.2.3 From 962a9dd47e7d92a9b29e7114c108bcff3ad0eb05 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 7 Oct 2009 01:59:20 +0200 Subject: MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/thread_info.h | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 01cc1630b66..845da2107ed 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -86,14 +86,7 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define __HAVE_ARCH_THREAD_INFO_ALLOCATOR #ifdef CONFIG_DEBUG_STACK_USAGE -#define alloc_thread_info(tsk) \ -({ \ - struct thread_info *ret; \ - \ - ret = kzalloc(THREAD_SIZE, GFP_KERNEL); \ - \ - ret; \ -}) +#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL) #else #define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL) #endif -- cgit v1.2.3 From 01a6fbf759a17940079fbdc0a4d43b596f323e7b Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 7 Oct 2009 22:11:08 +0200 Subject: MIPS: IP27: Fix build Broken by 182a85f8a119c789610a9d464f4129ded9f3c107. Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-ip27/topology.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index f6837422fe6..09a59bcc1b0 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -44,8 +44,8 @@ extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; .busy_factor = 32, \ .imbalance_pct = 125, \ .cache_nice_tries = 1, \ - .flags = SD_LOAD_BALANCE \ - | SD_BALANCE_EXEC \ + .flags = SD_LOAD_BALANCE | \ + SD_BALANCE_EXEC, \ .last_balance = jiffies, \ .balance_interval = 1, \ .nr_balance_failed = 0, \ -- cgit v1.2.3 From b40bb20e74a02dbe80fc7be6d0f9f05344051d20 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Thu, 8 Oct 2009 20:39:50 +0800 Subject: MIPS: Loongson: Remove redundant local_irq_disable() That code is executed with irq disabled already, so, remove the redundant local_irq_disable() here. Signed-off-by: Wu Zhangjin Signed-off-by: Ralf Baechle --- arch/mips/loongson/common/irq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c index f368c735cbd..b32b4a3e513 100644 --- a/arch/mips/loongson/common/irq.c +++ b/arch/mips/loongson/common/irq.c @@ -55,7 +55,6 @@ void __init arch_init_irq(void) * int-handler is not on bootstrap */ clear_c0_status(ST0_IM | ST0_BEV); - local_irq_disable(); /* setting irq trigger mode */ set_irq_trigger_mode(); -- cgit v1.2.3 From f45e5183618e41e3c8dbf87b74dc47d0c531462a Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Thu, 8 Oct 2009 21:17:54 +0800 Subject: MIPS: Add IRQF_TIMER flag for timer interrupts Along the lines of d6c585a4342a2ff627a29f9aea77c5ed4cd76023, add IRQF_TIMER flag for all timer interrupts This ensures that timer interrupts won't be disabled on suspend and not threaded for PREEMPT_RT. Signed-off-by: Wu Zhangjin Acked-by: Thomas Gleixner Signed-off-by: Ralf Baechle --- arch/mips/jazz/irq.c | 2 +- arch/mips/kernel/cevt-gt641xx.c | 2 +- arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/kernel/i8253.c | 2 +- arch/mips/nxp/pnx8550/common/time.c | 2 +- arch/mips/sgi-ip27/ip27-timer.c | 2 +- arch/mips/sni/time.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c index 7fd170d007e..7bd32d04c2c 100644 --- a/arch/mips/jazz/irq.c +++ b/arch/mips/jazz/irq.c @@ -134,7 +134,7 @@ static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id) static struct irqaction r4030_timer_irqaction = { .handler = r4030_timer_interrupt, - .flags = IRQF_DISABLED, + .flags = IRQF_DISABLED | IRQF_TIMER, .name = "R4030 timer", }; diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c index 92351e00ae0..f5d265eb6ea 100644 --- a/arch/mips/kernel/cevt-gt641xx.c +++ b/arch/mips/kernel/cevt-gt641xx.c @@ -113,7 +113,7 @@ static irqreturn_t gt641xx_timer0_interrupt(int irq, void *dev_id) static struct irqaction gt641xx_timer0_irqaction = { .handler = gt641xx_timer0_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "gt641xx_timer0", }; diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 2652362ce04..b469ad05d52 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -83,7 +83,7 @@ out: struct irqaction c0_compare_irqaction = { .handler = c0_compare_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "timer", }; diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c index f7d8d5d0ddb..ed5c441615e 100644 --- a/arch/mips/kernel/i8253.c +++ b/arch/mips/kernel/i8253.c @@ -98,7 +98,7 @@ static irqreturn_t timer_interrupt(int irq, void *dev_id) static struct irqaction irq0 = { .handler = timer_interrupt, - .flags = IRQF_DISABLED | IRQF_NOBALANCING, + .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER, .name = "timer" }; diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c index 18b19278487..d987a89c1e4 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/nxp/pnx8550/common/time.c @@ -59,7 +59,7 @@ static irqreturn_t pnx8xxx_timer_interrupt(int irq, void *dev_id) static struct irqaction pnx8xxx_timer_irq = { .handler = pnx8xxx_timer_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "pnx8xxx_timer", }; diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 6d0e59ffba2..d6802d6d1f8 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -105,7 +105,7 @@ static irqreturn_t hub_rt_counter_handler(int irq, void *dev_id) struct irqaction hub_rt_irqaction = { .handler = hub_rt_counter_handler, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "hub-rt", }; diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c index 62df6a598e0..f3b60e67120 100644 --- a/arch/mips/sni/time.c +++ b/arch/mips/sni/time.c @@ -67,7 +67,7 @@ static irqreturn_t a20r_interrupt(int irq, void *dev_id) static struct irqaction a20r_irqaction = { .handler = a20r_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "a20r-timer", }; -- cgit v1.2.3 From a22d621c80fb08f668ae3bfe62aeaae64b0b2b89 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Thu, 8 Oct 2009 22:16:47 +0200 Subject: MIPS: VPE: Remove stray unlock_kernel. Signed-off-by: Ralf Baechle Reported-by: Josip Rodin --- arch/mips/kernel/vpe.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 03092ab2a29..60477529362 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -1116,8 +1116,6 @@ static int vpe_open(struct inode *inode, struct file *filp) v->shared_ptr = NULL; v->__start = 0; - unlock_kernel(); - return 0; } -- cgit v1.2.3 From 80b8585b07feede94a742c4cdb80ab607a8813b3 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Sat, 10 Oct 2009 19:19:49 +0800 Subject: MIPS: 64-bit: Fix o32 lookup_dcookie syscall An o32 aplication passes a 64-bit value in a pair of registers; a 64-bit kernel expects a 64-bit argument in a single register. Signed-off-by: Chen Jie Signed-off-by: Hu Hongbing Signed-off-by: Wu Zhangjin Signed-off-by: Ralf Baechle --- arch/mips/kernel/linux32.c | 6 ++++++ arch/mips/kernel/scall64-o32.S | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 6242bc68add..b77fefaff9d 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -428,3 +428,9 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs) return do_fork(clone_flags, newsp, ®s, 0, parent_tidptr, child_tidptr); } + +asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf, + size_t len) +{ + return sys_lookup_dcookie(merge_64(a0, a1), buf, len); +} diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index 9bbf9775e0b..ba0dde6465a 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -450,7 +450,7 @@ sys_call_table: PTR sys_io_submit PTR sys_io_cancel /* 4245 */ PTR sys_exit_group - PTR sys_lookup_dcookie + PTR sys32_lookup_dcookie PTR sys_epoll_create PTR sys_epoll_ctl PTR sys_epoll_wait /* 4250 */ -- cgit v1.2.3 From c49e38c1a5e1c814f07365e7a5773801e20e26b5 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Sat, 10 Oct 2009 23:26:35 +0800 Subject: MIPS: Add IRQF_TIMER flag for timer interrupts As the commit 3ee4c147 shows, we need to "Add IRQF_TIMER flag for timer interrupts", Atsushi Nemoto have reported that some other timer interrupts should be considered, Here it is. Acked-by: Thomas Gleixner Acked-by: Rafael J. Wysocki Signed-off-by: Wu Zhangjin Signed-off-by: Ralf Baechle --- arch/mips/kernel/cevt-bcm1480.c | 2 +- arch/mips/kernel/cevt-ds1287.c | 2 +- arch/mips/kernel/cevt-sb1250.c | 2 +- arch/mips/kernel/cevt-txx9.c | 2 +- arch/mips/nxp/pnx8550/common/int.c | 2 +- arch/mips/nxp/pnx8550/common/time.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c index e02f79b1eb5..bfea327c636 100644 --- a/arch/mips/kernel/cevt-bcm1480.c +++ b/arch/mips/kernel/cevt-bcm1480.c @@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void) bcm1480_unmask_irq(cpu, irq); action->handler = sibyte_counter_handler; - action->flags = IRQF_DISABLED | IRQF_PERCPU; + action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c index 6996da4d74a..00a4da277cb 100644 --- a/arch/mips/kernel/cevt-ds1287.c +++ b/arch/mips/kernel/cevt-ds1287.c @@ -107,7 +107,7 @@ static irqreturn_t ds1287_interrupt(int irq, void *dev_id) static struct irqaction ds1287_irqaction = { .handler = ds1287_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "ds1287", }; diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c index ac5903d1b20..da78eeaea6e 100644 --- a/arch/mips/kernel/cevt-sb1250.c +++ b/arch/mips/kernel/cevt-sb1250.c @@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void) sb1250_unmask_irq(cpu, irq); action->handler = sibyte_counter_handler; - action->flags = IRQF_DISABLED | IRQF_PERCPU; + action->flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER; action->name = name; action->dev_id = cd; diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 0037f21baf0..218ee6bda93 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -146,7 +146,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id) static struct irqaction txx9tmr_irq = { .handler = txx9tmr_interrupt, - .flags = IRQF_DISABLED | IRQF_PERCPU, + .flags = IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER, .name = "txx9tmr", .dev_id = &txx9_clock_event_device, }; diff --git a/arch/mips/nxp/pnx8550/common/int.c b/arch/mips/nxp/pnx8550/common/int.c index f080f114a1b..7aca7d5375e 100644 --- a/arch/mips/nxp/pnx8550/common/int.c +++ b/arch/mips/nxp/pnx8550/common/int.c @@ -172,7 +172,7 @@ static struct irqaction gic_action = { static struct irqaction timer_action = { .handler = no_action, - .flags = IRQF_DISABLED, + .flags = IRQF_DISABLED | IRQF_TIMER, .name = "Timer", }; diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c index d987a89c1e4..8836c6203df 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/nxp/pnx8550/common/time.c @@ -72,7 +72,7 @@ static irqreturn_t monotonic_interrupt(int irq, void *dev_id) static struct irqaction monotonic_irqaction = { .handler = monotonic_interrupt, - .flags = IRQF_DISABLED, + .flags = IRQF_DISABLED | IRQF_TIMER, .name = "Monotonic timer", }; -- cgit v1.2.3 From a2e62f3a852e1e8187853291f5ee09ad4c881fcc Mon Sep 17 00:00:00 2001 From: Ralf Roesch Date: Wed, 16 Sep 2009 08:01:20 +0200 Subject: MIPS: TXx9: Fix error handling / Fix for noenexisting gpio_remove. Error was introduced by commit 0385d1f3d394c6814be0b165c153fc3fc254469a. Signed-off-by: Ralf Roesch Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index c860810722c..dfe4720ac82 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -817,7 +817,8 @@ void __init txx9_iocled_init(unsigned long baseaddr, out_pdev: platform_device_put(pdev); out_gpio: - gpio_remove(&iocled->chip); + if (gpiochip_remove(&iocled->chip)) + return; out_unmap: iounmap(iocled->mmioaddr); out_free: -- cgit v1.2.3 From e85d59df13cf5cce08becb3fd261048e6d870c0d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 31 Aug 2009 20:27:39 +0200 Subject: MIPS: BCM63xx: Fix soft-reset lockup on BCM6345 This patch fixes a lockup on BCM6345 where setting the PLL soft reset bit will also lock the other blocks including UART. Instead of setting only the PLL soft reset bit in the software reset register, set this bit but do not touch the others. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/setup.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/mips/bcm63xx/setup.c b/arch/mips/bcm63xx/setup.c index b18a0ca926f..d0056598fbf 100644 --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -75,7 +75,9 @@ void bcm63xx_machine_reboot(void) bcm6348_a1_reboot(); printk(KERN_INFO "triggering watchdog soft-reset...\n"); - bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG); + reg |= SYS_PLL_SOFT_RESET; + bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG); while (1) ; } -- cgit v1.2.3 From e85843a1e1974167878e6124a91a06036c3b849d Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 17 Aug 2009 00:28:24 +0200 Subject: MIPS: AU1000: Fix build failure for db1x00 configured for Au1100 SoC This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index feea00148b5..91595fa8903 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio) if ((gpio >= 8) && (gpio <= 15)) return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ + + return -ENXIO; } #ifdef CONFIG_SOC_AU1100 -- cgit v1.2.3 From 6c1e7a5ad9ac40c9bf45381409dc16207b6ffceb Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 10 Aug 2009 21:42:54 +0200 Subject: MIPS: BCM63xx: Make bcm63xx_uart_register an initfunc This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/boards/board_bcm963xx.c | 3 --- arch/mips/bcm63xx/dev-uart.c | 2 +- arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h | 6 ------ 3 files changed, 1 insertion(+), 10 deletions(-) delete mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 78e155d21be..05a35cf5963 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #define PFX "board_bcm963xx: " @@ -794,8 +793,6 @@ int __init board_register_devices(void) { u32 val; - bcm63xx_uart_register(); - if (board.has_pccard) bcm63xx_pcmcia_register(); diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c index 5f3d89c4a98..b0519461ad9 100644 --- a/arch/mips/bcm63xx/dev-uart.c +++ b/arch/mips/bcm63xx/dev-uart.c @@ -10,7 +10,6 @@ #include #include #include -#include static struct resource uart_resources[] = { { @@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void) uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); return platform_device_register(&bcm63xx_uart_device); } +arch_initcall(bcm63xx_uart_register); diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h deleted file mode 100644 index bf348f573bb..00000000000 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_UART_H_ -#define BCM63XX_DEV_UART_H_ - -int bcm63xx_uart_register(void); - -#endif /* BCM63XX_DEV_UART_H_ */ -- cgit v1.2.3 From 2cfac7f7f2e6d11bcba105b3d6ba4d96ba5ad349 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Mon, 10 Aug 2009 21:42:59 +0200 Subject: MIPS: BCM63xx: Prepare for watchdog support This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/Makefile | 2 +- arch/mips/bcm63xx/dev-wdt.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm63xx/dev-wdt.c diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index c146d1edede..00064b66080 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,5 +1,5 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o \ - dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o + dev-dsp.o dev-enet.o dev-pcmcia.o dev-uart.o dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c new file mode 100644 index 00000000000..3e6c716a4c1 --- /dev/null +++ b/arch/mips/bcm63xx/dev-wdt.c @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include + +static struct resource wdt_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bcm63xx_wdt_device = { + .name = "bcm63xx-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +int __init bcm63xx_wdt_register(void) +{ + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); + wdt_resources[0].end = wdt_resources[0].start; + wdt_resources[0].end += RSET_WDT_SIZE - 1; + + return platform_device_register(&bcm63xx_wdt_device); +} +arch_initcall(bcm63xx_wdt_register); -- cgit v1.2.3 From 72838a170372d6bb44bcb04a81aa2c83312cfbc0 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 4 Aug 2009 23:09:36 +0200 Subject: MIPS: AR7: register watchdog device only if enabled in hw configuration This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/ar7/platform.c | 9 ++++++++- arch/mips/include/asm/mach-ar7/ar7.h | 3 +++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index e2278c04459..835f3f0319c 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) { u16 chip_id; int res; + u32 *bootcr, val; #ifdef CONFIG_SERIAL_8250 static struct uart_port uart_port[2]; @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) ar7_wdt_res.end = ar7_wdt_res.start + 0x20; - res = platform_device_register(&ar7_wdt); + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); + val = *bootcr; + iounmap(bootcr); + + /* Register watchdog only if enabled in hardware */ + if (val & AR7_WDT_HW_ENA) + res = platform_device_register(&ar7_wdt); return res; } diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index de71694614d..21cbbc70644 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -78,6 +78,9 @@ #define AR7_REF_CLOCK 25000000 #define AR7_XTAL_CLOCK 24000000 +/* DCL */ +#define AR7_WDT_HW_ENA 0x10 + struct plat_cpmac_data { int reset_bit; int power_bit; -- cgit v1.2.3 From 39d2211d20518677511043d7ee16bbca6d0c5070 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 12 Oct 2009 02:23:48 +0200 Subject: MIPS: MTX-1: Fix build if CONFIG_PCI is disabled. Signed-off-by: Ralf Baechle --- arch/mips/alchemy/mtx-1/board_setup.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cc32c69a74a..45b61c9b82b 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -69,6 +69,7 @@ void __init board_setup(void) #else au_writel(0xf, Au1500_PCI_CFG); #endif + board_pci_idsel = mtx1_pci_idsel; #endif /* Initialize sys_pinfunc */ @@ -85,8 +86,6 @@ void __init board_setup(void) alchemy_gpio_direction_output(211, 1); /* green on */ alchemy_gpio_direction_output(212, 0); /* red off */ - board_pci_idsel = mtx1_pci_idsel; - printk(KERN_INFO "4G Systems MTX-1 Board\n"); } -- cgit v1.2.3 From 0f334a3e8c3586f81286345eb077ed32b375e8d6 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Mon, 7 Sep 2009 11:11:31 -0700 Subject: MIPS: Fix machine check exception in kmap_coherent() On an SMP system with cache aliases, the following sequence of events may happen: 1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a temporary mapping in the fixmap region 2) copy_page() starts on CPU0 3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page() 4) CPU0 takes the interrupt, interrupting copy_page() 5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again 6) The second invocation of kmap_coherent() on CPU0 tries to use the same fixmap virtual address that was being used by copy_user_highpage() 7) CPU0 throws a machine check exception for the TLB address conflict Fixed by creating an extra set of fixmap entries for use in interrupt handlers. This prevents fixmap VA conflicts between copy_user_highpage() running in user context, and local_r4k_flush_cache_page() invoked from an SMP IPI. Signed-off-by: Kevin Cernekee Signed-off-by: Ralf Baechle --- arch/mips/include/asm/fixmap.h | 4 ++-- arch/mips/mm/init.c | 6 +++++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h index efeddc8db8b..0b89b83e205 100644 --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -48,9 +48,9 @@ enum fixed_addresses { #define FIX_N_COLOURS 8 FIX_CMAP_BEGIN, #ifdef CONFIG_MIPS_MT_SMTC - FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS), + FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS * 2), #else - FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS, + FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * 2), #endif #ifdef CONFIG_HIGHMEM /* reserved pte's for temporary kernel mappings */ diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 15aa1902a78..8d1f4f36304 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -132,7 +133,10 @@ void *kmap_coherent(struct page *page, unsigned long addr) inc_preempt_count(); idx = (addr >> PAGE_SHIFT) & (FIX_N_COLOURS - 1); #ifdef CONFIG_MIPS_MT_SMTC - idx += FIX_N_COLOURS * smp_processor_id(); + idx += FIX_N_COLOURS * smp_processor_id() + + (in_interrupt() ? (FIX_N_COLOURS * NR_CPUS) : 0); +#else + idx += in_interrupt() ? FIX_N_COLOURS : 0; #endif vaddr = __fix_to_virt(FIX_CMAP_END - idx); pte = mk_pte(page, PAGE_KERNEL); -- cgit v1.2.3 From accfd35a4e82148ff3d6e1946c1786e73fb408fd Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 10 Jul 2009 01:53:54 -0700 Subject: MIPS: MTI: Fix accesses to device registers on MIPS boards This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/mti-malta/malta-int.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 3e0a9b35ba5..e568d0da060 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void) dummy = BONITO_PCIMAP_CFG; iob(); /* sync */ - irq = readl((u32 *)_pcictrl_bonito_pcicfg); + irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); iob(); /* sync */ irq &= 0xff; BONITO_PCIMAP_CFG = 0; -- cgit v1.2.3 From c70887555143fdede9595df4c7a598676922f107 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 12 Oct 2009 22:30:06 +0200 Subject: MIPS: Kconfig: Fix duplicate default value for MIPS_L1_CACHE_SHIFT. Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 705a7a9170f..7159495ee0b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1012,9 +1012,8 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int - default "4" if MACH_DECSTATION || MIKROTIK_RB532 + default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON - default "4" if PMC_MSP4200_EVAL default "5" config HAVE_STD_PC_SERIAL_PORT -- cgit v1.2.3 From a951f2829adba3f2945172b740528fce4366907d Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 12 Oct 2009 22:54:47 +0200 Subject: MIPS: Malta: Enable PCI 2.1 compatibility in PIIX4 Based on original patch by Chris Dearman . Signed-off-by: Ralf Baechle --- arch/mips/mti-malta/malta-pci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b9743190609..efdb4f66ffc 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -241,3 +241,16 @@ void __init mips_pcibios_init(void) register_pci_controller(controller); } + +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} + +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); -- cgit v1.2.3 From a4e7cac18f074fa55142bc86cc35a74f3c6ea615 Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Mon, 12 Oct 2009 23:20:20 +0200 Subject: MIPS: 1004K: Enable SPRAM support. Signed-off-by: Ralf Baechle --- arch/mips/kernel/spram.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6ddb507a87e..71b47376cf7 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -208,6 +208,7 @@ __cpuinit void spram_config(void) case CPU_24K: case CPU_34K: case CPU_74K: + case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & (1<<24)) { -- cgit v1.2.3 From a074f0e89faa8989bdbd6110785d2aafe7df5285 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 10 Jul 2009 01:51:27 -0700 Subject: MIPS: SPRAM: Clean up support code a little Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/include/asm/spram.h | 10 ++++++++++ arch/mips/kernel/cpu-probe.c | 8 +------- arch/mips/kernel/spram.c | 4 +--- 3 files changed, 12 insertions(+), 10 deletions(-) create mode 100644 arch/mips/include/asm/spram.h diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h new file mode 100644 index 00000000000..0b89006e490 --- /dev/null +++ b/arch/mips/include/asm/spram.h @@ -0,0 +1,10 @@ +#ifndef _MIPS_SPRAM_H +#define _MIPS_SPRAM_H + +#ifdef CONFIG_CPU_MIPSR2 +extern __init void spram_config(void); +#else +static inline void spram_config(void) { }; +#endif /* CONFIG_CPU_MIPSR2 */ + +#endif /* _MIPS_SPRAM_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f709657e4dc..7a51866068a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -23,7 +23,7 @@ #include #include #include - +#include /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, * the implementation of the "wait" feature differs between CPU families. This @@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); } -#ifdef CONFIG_CPU_MIPSR2 -extern void spram_config(void); -#else -static inline void spram_config(void) {} -#endif - static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 71b47376cf7..1821d12a641 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type, offset += 2 * SPRAM_TAG_STRIDE; } } - -__cpuinit void spram_config(void) +void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; -- cgit v1.2.3 From cea2be444380fc1bf665cd023ed84be7e0872d28 Mon Sep 17 00:00:00 2001 From: Nigel Stephens Date: Mon, 12 Oct 2009 14:57:18 -0700 Subject: MIPS: Fix abs.[sd] and neg.[sd] emulation for NaN operands This patch ensures that the sign bit is always updated for NaN operands. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/math-emu/dp_simple.c | 13 ++++--------- arch/mips/math-emu/sp_simple.c | 11 +++-------- 2 files changed, 7 insertions(+), 17 deletions(-) diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index 1c555e6c6a9..d9ae1dbabda 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -62,8 +62,6 @@ ieee754dp ieee754dp_neg(ieee754dp x) return ieee754dp_nanxcpt(y, "neg"); } - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "neg", x); return x; } @@ -76,15 +74,12 @@ ieee754dp ieee754dp_abs(ieee754dp x) CLEARCX; FLUSHXDP; + /* Clear sign ALWAYS, irrespective of NaN */ + DPSIGN(x) = 0; + if (xc == IEEE754_CLASS_SNAN) { - SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + return ieee754dp_nanxcpt(ieee754dp_indef(), "abs"); } - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "abs", x); - - /* quick fix up */ - DPSIGN(x) = 0; return x; } diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index 770f0f4677c..3175477d36f 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c @@ -62,8 +62,6 @@ ieee754sp ieee754sp_neg(ieee754sp x) return ieee754sp_nanxcpt(y, "neg"); } - if (ieee754sp_isnan(x)) /* but not infinity */ - return ieee754sp_nanxcpt(x, "neg", x); return x; } @@ -76,15 +74,12 @@ ieee754sp ieee754sp_abs(ieee754sp x) CLEARCX; FLUSHXSP; + /* Clear sign ALWAYS, irrespective of NaN */ + SPSIGN(x) = 0; + if (xc == IEEE754_CLASS_SNAN) { - SETCX(IEEE754_INVALID_OPERATION); return ieee754sp_nanxcpt(ieee754sp_indef(), "abs"); } - if (ieee754sp_isnan(x)) /* but not infinity */ - return ieee754sp_nanxcpt(x, "abs", x); - - /* quick fix up */ - SPSIGN(x) = 0; return x; } -- cgit v1.2.3 From 2ee0a42961c942c6a2fb70700ef4e25c0acf5fca Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 10 Jul 2009 02:06:38 -0700 Subject: MIPS: CMP: Fix memory barriers for correct operation of amon_cpu_start Signed-off-by: Chris Dearman (chris@mips.com) Signed-off-by: Ralf Baechle --- arch/mips/mti-malta/malta-amon.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index df9e526312a..469d9b0cee6 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -70,11 +70,12 @@ void amon_cpu_start(int cpu, launch->sp = sp; launch->a0 = a0; - /* Make sure target sees parameters before the go bit */ - smp_mb(); - + smp_wmb(); /* Target must see parameters before go */ launch->flags |= LAUNCH_FGO; + smp_wmb(); /* Target must see go before we poll */ + while ((launch->flags & LAUNCH_FGONE) == 0) ; + smp_rmb(); /* Target will be updating flags soon */ pr_debug("launch: cpu%d gone!\n", cpu); } -- cgit v1.2.3 From 7098f748283b4c056cca9c284c476b03f004ca12 Mon Sep 17 00:00:00 2001 From: Chris Dearman Date: Fri, 10 Jul 2009 01:54:09 -0700 Subject: MIPS: GIC: Random fixes and enhancements. Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/include/asm/gcmpregs.h | 18 ++-- arch/mips/include/asm/gic.h | 188 ++++----------------------------------- arch/mips/kernel/irq-gic.c | 114 +++++++++--------------- arch/mips/mti-malta/malta-int.c | 101 ++++++++++++--------- arch/mips/mti-malta/malta-pci.c | 14 ++- 5 files changed, 142 insertions(+), 293 deletions(-) diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h index 36fd969d64d..c0cf76a2ca8 100644 --- a/arch/mips/include/asm/gcmpregs.h +++ b/arch/mips/include/asm/gcmpregs.h @@ -19,15 +19,20 @@ #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ /* Offsets to individual GCMP registers from GCMP base */ -#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) +#define GCMPOFS(block, tag, reg) \ + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) +#define GCMPOFSn(block, tag, reg, n) \ + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) +#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) /* GCMP register access */ #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) +#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) @@ -49,10 +54,10 @@ #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 +#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 +#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 @@ -115,5 +120,6 @@ #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ extern int __init gcmp_probe(unsigned long, unsigned long); - +extern int __init gcmp_niocu(void); +extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); #endif /* _ASM_GCMPREGS_H */ diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index a8f57341f12..9b9436a4d81 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -12,7 +12,6 @@ #define _ASM_GICREGS_H #undef GICISBYTELITTLEENDIAN -#define GICISWORDLITTLEENDIAN /* Constants */ #define GIC_POL_POS 1 @@ -20,11 +19,7 @@ #define GIC_TRIG_EDGE 1 #define GIC_TRIG_LEVEL 0 -#ifdef CONFIG_SMP #define GIC_NUM_INTRS (24 + NR_CPUS * 2) -#else -#define GIC_NUM_INTRS 32 -#endif #define MSK(n) ((1 << (n)) - 1) #define REG32(addr) (*(volatile unsigned int *) (addr)) @@ -70,13 +65,13 @@ #define USM_VISIBLE_SECTION_SIZE 0x10000 /* Register Map for Shared Section */ -#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) #define GIC_SH_CONFIG_OFS 0x0000 /* Shared Global Counter */ #define GIC_SH_COUNTER_31_00_OFS 0x0010 #define GIC_SH_COUNTER_63_32_OFS 0x0014 +#define GIC_SH_REVISIONID_OFS 0x0020 /* Interrupt Polarity */ #define GIC_SH_POL_31_0_OFS 0x0100 @@ -164,24 +159,31 @@ (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) +/* Convert an interrupt number to a byte offset/bit for multi-word registers */ +#define GIC_INTR_OFS(intr) (((intr) / 32)*4) +#define GIC_INTR_BIT(intr) ((intr) % 32) + /* Polarity : Reset Value is always 0 */ #define GIC_SH_SET_POLARITY_OFS 0x0100 #define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \ + GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr)) /* Triggering : Reset Value is always 0 */ #define GIC_SH_SET_TRIGGER_OFS 0x0180 #define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \ + GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr)) /* Mask manipulation */ #define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) - +#define GIC_SET_INTR_MASK(intr) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \ + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) #define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) +#define GIC_CLR_INTR_MASK(intr) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \ + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) /* Register Map for Local Section */ #define GIC_VPE_CTL_OFS 0x0000 @@ -219,161 +221,6 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -#else /* CONFIG_CPU_BIG_ENDIAN */ - -#define GIC_SH_CONFIG_OFS 0x0000 - -/* Shared Global Counter */ -#define GIC_SH_COUNTER_31_00_OFS 0x0014 -#define GIC_SH_COUNTER_63_32_OFS 0x0010 - -/* Interrupt Polarity */ -#define GIC_SH_POL_31_0_OFS 0x0104 -#define GIC_SH_POL_63_32_OFS 0x0100 -#define GIC_SH_POL_95_64_OFS 0x010c -#define GIC_SH_POL_127_96_OFS 0x0108 -#define GIC_SH_POL_159_128_OFS 0x0114 -#define GIC_SH_POL_191_160_OFS 0x0110 -#define GIC_SH_POL_223_192_OFS 0x011c -#define GIC_SH_POL_255_224_OFS 0x0118 - -/* Edge/Level Triggering */ -#define GIC_SH_TRIG_31_0_OFS 0x0184 -#define GIC_SH_TRIG_63_32_OFS 0x0180 -#define GIC_SH_TRIG_95_64_OFS 0x018c -#define GIC_SH_TRIG_127_96_OFS 0x0188 -#define GIC_SH_TRIG_159_128_OFS 0x0194 -#define GIC_SH_TRIG_191_160_OFS 0x0190 -#define GIC_SH_TRIG_223_192_OFS 0x019c -#define GIC_SH_TRIG_255_224_OFS 0x0198 - -/* Dual Edge Triggering */ -#define GIC_SH_DUAL_31_0_OFS 0x0204 -#define GIC_SH_DUAL_63_32_OFS 0x0200 -#define GIC_SH_DUAL_95_64_OFS 0x020c -#define GIC_SH_DUAL_127_96_OFS 0x0208 -#define GIC_SH_DUAL_159_128_OFS 0x0214 -#define GIC_SH_DUAL_191_160_OFS 0x0210 -#define GIC_SH_DUAL_223_192_OFS 0x021c -#define GIC_SH_DUAL_255_224_OFS 0x0218 - -/* Set/Clear corresponding bit in Edge Detect Register */ -#define GIC_SH_WEDGE_OFS 0x0280 - -/* Reset Mask - Disables Interrupt */ -#define GIC_SH_RMASK_31_0_OFS 0x0304 -#define GIC_SH_RMASK_63_32_OFS 0x0300 -#define GIC_SH_RMASK_95_64_OFS 0x030c -#define GIC_SH_RMASK_127_96_OFS 0x0308 -#define GIC_SH_RMASK_159_128_OFS 0x0314 -#define GIC_SH_RMASK_191_160_OFS 0x0310 -#define GIC_SH_RMASK_223_192_OFS 0x031c -#define GIC_SH_RMASK_255_224_OFS 0x0318 - -/* Set Mask (WO) - Enables Interrupt */ -#define GIC_SH_SMASK_31_0_OFS 0x0384 -#define GIC_SH_SMASK_63_32_OFS 0x0380 -#define GIC_SH_SMASK_95_64_OFS 0x038c -#define GIC_SH_SMASK_127_96_OFS 0x0388 -#define GIC_SH_SMASK_159_128_OFS 0x0394 -#define GIC_SH_SMASK_191_160_OFS 0x0390 -#define GIC_SH_SMASK_223_192_OFS 0x039c -#define GIC_SH_SMASK_255_224_OFS 0x0398 - -/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ -#define GIC_SH_MASK_31_0_OFS 0x0404 -#define GIC_SH_MASK_63_32_OFS 0x0400 -#define GIC_SH_MASK_95_64_OFS 0x040c -#define GIC_SH_MASK_127_96_OFS 0x0408 -#define GIC_SH_MASK_159_128_OFS 0x0414 -#define GIC_SH_MASK_191_160_OFS 0x0410 -#define GIC_SH_MASK_223_192_OFS 0x041c -#define GIC_SH_MASK_255_224_OFS 0x0418 - -/* Pending Global Interrupts (RO) */ -#define GIC_SH_PEND_31_0_OFS 0x0484 -#define GIC_SH_PEND_63_32_OFS 0x0480 -#define GIC_SH_PEND_95_64_OFS 0x048c -#define GIC_SH_PEND_127_96_OFS 0x0488 -#define GIC_SH_PEND_159_128_OFS 0x0494 -#define GIC_SH_PEND_191_160_OFS 0x0490 -#define GIC_SH_PEND_223_192_OFS 0x049c -#define GIC_SH_PEND_255_224_OFS 0x0498 - -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 - -/* Maps Interrupt X to a Pin */ -#define GIC_SH_MAP_TO_PIN(intr) \ - (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) - -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 - -/* - * Maps Interrupt X to a VPE. This is more complex than the LE case, as - * odd and even registers need to be transposed. It does work - trust me! - */ -#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ - (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ - (((((vpe) / 32) ^ 1) - 1) * 4)) -#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) - -/* Polarity */ -#define GIC_SH_SET_POLARITY_OFS 0x0100 -#define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) - -/* Triggering */ -#define GIC_SH_SET_TRIGGER_OFS 0x0180 -#define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) - -/* Mask manipulation */ -#define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -#define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -/* Register Map for Local Section */ -#define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_PEND_OFS 0x0004 -#define GIC_VPE_MASK_OFS 0x0008 -#define GIC_VPE_RMASK_OFS 0x000c -#define GIC_VPE_SMASK_OFS 0x0010 -#define GIC_VPE_WD_MAP_OFS 0x0040 -#define GIC_VPE_COMPARE_MAP_OFS 0x0044 -#define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 -#define GIC_VPE_SWINT0_MAP_OFS 0x0054 -#define GIC_VPE_SWINT1_MAP_OFS 0x0058 -#define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VPE_WD_CONFIG0_OFS 0x0090 -#define GIC_VPE_WD_COUNT0_OFS 0x0094 -#define GIC_VPE_WD_INITIAL0_OFS 0x0098 -#define GIC_VPE_COMPARE_LO_OFS 0x00a4 -#define GIC_VPE_COMPARE_HI_OFS 0x00a0 - -#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 -#define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) - -#define GIC_VPE_EIC_VEC_BASE 0x0800 -#define GIC_VPE_EIC_VEC(intr) \ - (GIC_VPE_EIC_VEC_BASE + (4 * intr)) - -#define GIC_VPE_TENABLE_NMI_OFS 0x1000 -#define GIC_VPE_TENABLE_YQ_OFS 0x1004 -#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 -#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 - -/* User Mode Visible Section Register Map */ -#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 -#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 - -#endif /* !LE */ - /* Masks */ #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) @@ -473,12 +320,13 @@ struct gic_intrmask_regs { * in building ipi_map. */ struct gic_intr_map { - unsigned int intrnum; /* Ext Intr Num */ unsigned int cpunum; /* Directed to this CPU */ unsigned int pin; /* Directed to this Pin */ unsigned int polarity; /* Polarity : +/- */ unsigned int trigtype; /* Trigger : Edge/Levl */ - unsigned int ipiflag; /* Is used for IPI ? */ + unsigned int flags; /* Misc flags */ +#define GIC_FLAG_IPI 0x01 +#define GIC_FLAG_TRANSPARENT 0x02 }; extern void gic_init(unsigned long gic_base_addr, diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index d2072cd3859..b181f2f0ea8 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -14,38 +14,23 @@ static unsigned long _gic_base; -static unsigned int _irqbase, _mapsize, numvpes, numintrs; -static struct gic_intr_map *_intrmap; +static unsigned int _irqbase; +static unsigned int gic_irq_flags[GIC_NUM_INTRS]; +#define GIC_IRQ_FLAG_EDGE 0x0001 -static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; +struct gic_pcpu_mask pcpu_masks[NR_CPUS]; static struct gic_pending_regs pending_regs[NR_CPUS]; static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; -#define gic_wedgeb2bok 0 /* - * Can GIC handle b2b writes to wedge register? - */ -#if gic_wedgeb2bok == 0 -static DEFINE_SPINLOCK(gic_wedgeb2b_lock); -#endif - void gic_send_ipi(unsigned int intr) { -#if gic_wedgeb2bok == 0 - unsigned long flags; -#endif pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, read_c0_status()); - if (!gic_wedgeb2bok) - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); - if (!gic_wedgeb2bok) { - (void) GIC_REG(SHARED, GIC_SH_CONFIG); - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); - } } /* This is Malta specific and needs to be exported */ -static void vpe_local_setup(unsigned int numvpes) +static void __init vpe_local_setup(unsigned int numvpes) { int i; unsigned long timer_interrupt = 5, perf_interrupt = 5; @@ -105,44 +90,34 @@ unsigned int gic_get_int(void) static unsigned int gic_irq_startup(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_SET_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_SET_INTR_MASK(irq); return 0; } static void gic_irq_ack(unsigned int irq) { -#if gic_wedgeb2bok == 0 - unsigned long flags; -#endif - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_CLR_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_CLR_INTR_MASK(irq); - if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { - if (!gic_wedgeb2bok) - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); + if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); - if (!gic_wedgeb2bok) { - (void) GIC_REG(SHARED, GIC_SH_CONFIG); - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); - } - } } static void gic_mask_irq(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_CLR_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_CLR_INTR_MASK(irq); } static void gic_unmask_irq(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_SET_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_SET_INTR_MASK(irq); } #ifdef CONFIG_SMP @@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) unsigned long flags; int i; - pr_debug(KERN_DEBUG "%s called\n", __func__); irq -= _irqbase; - + pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; @@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) /* Re-route this IRQ */ GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); - /* - * FIXME: assumption that _intrmap is ordered and has no holes - */ - - /* Update the intr_map */ - _intrmap[irq].cpunum = first_cpu(tmp); - /* Update the pcpu_masks */ for (i = 0; i < NR_CPUS; i++) clear_bit(irq, pcpu_masks[i].pcpu_mask); @@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = { #endif }; -static void __init setup_intr(unsigned int intr, unsigned int cpu, - unsigned int pin, unsigned int polarity, unsigned int trigtype) +static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, + unsigned int pin, unsigned int polarity, unsigned int trigtype, + unsigned int flags) { /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { @@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu, GIC_SET_TRIGGER(intr, trigtype); /* Init Intr Masks */ - GIC_SET_INTR_MASK(intr, 0); + GIC_CLR_INTR_MASK(intr); + /* Initialise per-cpu Interrupt software masks */ + if (flags & GIC_FLAG_IPI) + set_bit(intr, pcpu_masks[cpu].pcpu_mask); + if (flags & GIC_FLAG_TRANSPARENT) + GIC_SET_INTR_MASK(intr); + if (trigtype == GIC_TRIG_EDGE) + gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; } -static void __init gic_basic_init(void) +static void __init gic_basic_init(int numintrs, int numvpes, + struct gic_intr_map *intrmap, int mapsize) { unsigned int i, cpu; /* Setup defaults */ - for (i = 0; i < GIC_NUM_INTRS; i++) { + for (i = 0; i < numintrs; i++) { GIC_SET_POLARITY(i, GIC_POL_POS); GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); - GIC_SET_INTR_MASK(i, 0); + GIC_CLR_INTR_MASK(i); + if (i < GIC_NUM_INTRS) + gic_irq_flags[i] = 0; } /* Setup specifics */ - for (i = 0; i < _mapsize; i++) { - cpu = _intrmap[i].cpunum; + for (i = 0; i < mapsize; i++) { + cpu = intrmap[i].cpunum; if (cpu == X) continue; - - if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 && - _intrmap[i].ipiflag == 0) + if (cpu == 0 && i != 0 && intrmap[i].flags == 0) continue; - - setup_intr(_intrmap[i].intrnum, - _intrmap[i].cpunum, - _intrmap[i].pin, - _intrmap[i].polarity, - _intrmap[i].trigtype); - /* Initialise per-cpu Interrupt software masks */ - if (_intrmap[i].ipiflag) - set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask); + gic_setup_intr(i, + intrmap[i].cpunum, + intrmap[i].pin, + intrmap[i].polarity, + intrmap[i].trigtype, + intrmap[i].flags); } vpe_local_setup(numvpes); @@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr, unsigned int irqbase) { unsigned int gicconfig; + int numvpes, numintrs; _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, gic_addrspace_size); _irqbase = irqbase; - _intrmap = intr_map; - _mapsize = intr_map_size; GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> @@ -290,5 +262,5 @@ void __init gic_init(unsigned long gic_base_addr, pr_debug("%s called\n", __func__); - gic_basic_init(); + gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); } diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index e568d0da060..377a925e8cc 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -379,32 +379,32 @@ static msc_irqmap_t __initdata msc_eicirqmap[] = { static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); -#if defined(CONFIG_MIPS_MT_SMP) /* * This GIC specific tabular array defines the association between External * Interrupts and CPUs/Core Interrupts. The nature of the External * Interrupts is also defined here - polarity/trigger. */ + +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { - { GIC_EXT_INTR(0), X, X, X, X, 0 }, - { GIC_EXT_INTR(1), X, X, X, X, 0 }, - { GIC_EXT_INTR(2), X, X, X, X, 0 }, - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(10), X, X, X, X, 0 }, - { GIC_EXT_INTR(11), X, X, X, X, 0 }, - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(15), X, X, X, X, 0 }, -/* This is the end of the general interrupts now we do IPI ones */ + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + /* The remainder of this table is initialised by fill_ipi_map */ }; -#endif /* * GCMP needs to be detected before any SMP initialisation @@ -419,20 +419,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size) gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; if (gcmp_present) - printk(KERN_DEBUG "GCMP present\n"); + pr_debug("GCMP present\n"); return gcmp_present; } +/* Return the number of IOCU's present */ +int __init gcmp_niocu(void) +{ + return gcmp_present ? + (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : + 0; +} + +/* Set GCMP region attributes */ +void __init gcmp_setregion(int region, unsigned long base, + unsigned long mask, int type) +{ + GCMPGCBn(CMxBASE, region) = base; + GCMPGCBn(CMxMASK, region) = mask | type; +} + #if defined(CONFIG_MIPS_MT_SMP) static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) { int intr = baseintr + cpu; - gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); gic_intr_map[intr].cpunum = cpu; gic_intr_map[intr].pin = cpupin; gic_intr_map[intr].polarity = GIC_POL_POS; gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; - gic_intr_map[intr].ipiflag = 1; + gic_intr_map[intr].flags = GIC_FLAG_IPI; ipi_map[cpu] |= (1 << (cpupin + 2)); } @@ -447,6 +462,12 @@ static void __init fill_ipi_map(void) } #endif +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + set_irq_handler(irq, handle_percpu_irq); +} + void __init arch_init_irq(void) { init_i8259_irqs(); @@ -463,7 +484,7 @@ void __init arch_init_irq(void) MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } if (gic_present) - printk(KERN_DEBUG "GIC present\n"); + pr_debug("GIC present\n"); switch (mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: @@ -526,16 +547,16 @@ void __init arch_init_irq(void) &corehi_irqaction); } -#if defined(CONFIG_MIPS_MT_SMP) if (gic_present) { /* FIXME */ int i; - +#if defined(CONFIG_MIPS_MT_SMP) gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; gic_resched_int_base = gic_call_int_base - NR_CPUS; - fill_ipi_map(); - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +#endif + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); if (!gcmp_present) { /* Enable the GIC */ i = REG(_msc01_biu_base, MSC01_SC_CFG); @@ -543,7 +564,7 @@ void __init arch_init_irq(void) (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); pr_debug("GIC Enabled\n"); } - +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); @@ -556,16 +577,14 @@ void __init arch_init_irq(void) write_c0_status(0x1100dc00); printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); for (i = 0; i < NR_CPUS; i++) { - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), &irq_resched); - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), &irq_call); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), handle_percpu_irq); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), handle_percpu_irq); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_RESCHED_INT(i), &irq_resched); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_CALL_INT(i), &irq_call); } +#endif } else { +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_veic) { set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); @@ -580,14 +599,10 @@ void __init arch_init_irq(void) cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; } - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); - - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); - } + arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); + arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); #endif + } } void malta_be_init(void) diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index efdb4f66ffc..2fbfa1a8c3a 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -27,7 +27,7 @@ #include #include - +#include #include #include #include @@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(0, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); @@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(1, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; -- cgit v1.2.3 From 05cf20790b3b3ed81cb001e8f41e473247f28302 Mon Sep 17 00:00:00 2001 From: Jaidev Patwardhan Date: Fri, 10 Jul 2009 01:54:25 -0700 Subject: MIPS: GCMP: Avoid accessing registers when they are not present Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/mti-malta/malta-int.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 377a925e8cc..4c3fca18a17 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -411,6 +411,11 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { */ int __init gcmp_probe(unsigned long addr, unsigned long size) { + if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { + gcmp_present = 0; + return gcmp_present; + } + if (gcmp_present >= 0) return gcmp_present; @@ -479,9 +484,14 @@ void __init arch_init_irq(void) GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; gic_present = 1; } else { - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; + if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { + _msc01_biu_base = (unsigned long) + ioremap_nocache(MSC01_BIU_REG_BASE, + MSC01_BIU_ADDRSPACE_SZ); + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & + MSC01_SC_CFG_GICPRES_MSK) >> + MSC01_SC_CFG_GICPRES_SHF; + } } if (gic_present) pr_debug("GIC present\n"); -- cgit v1.2.3 From 2e41f91d9e90e34254746fefcb7bb678a3c9d541 Mon Sep 17 00:00:00 2001 From: Jaidev Patwardhan Date: Fri, 10 Jul 2009 02:06:00 -0700 Subject: MIPS: SMTC: Avoid queing multiple reschedule IPIs Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/include/asm/smtc_ipi.h | 1 + arch/mips/kernel/smtc.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h index 8ce51757434..15278dbd7e7 100644 --- a/arch/mips/include/asm/smtc_ipi.h +++ b/arch/mips/include/asm/smtc_ipi.h @@ -45,6 +45,7 @@ struct smtc_ipi_q { spinlock_t lock; struct smtc_ipi *tail; int depth; + int resched_flag; /* reschedule already queued */ }; static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 4d181df44a4..24630fd8ef6 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -75,7 +75,6 @@ unsigned long irq_hwmask[NR_IRQS]; asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; - /* * Number of InterProcessor Interrupt (IPI) message buffers to allocate */ @@ -388,6 +387,7 @@ void smtc_prepare_cpus(int cpus) IPIQ[i].head = IPIQ[i].tail = NULL; spin_lock_init(&IPIQ[i].lock); IPIQ[i].depth = 0; + IPIQ[i].resched_flag = 0; /* No reschedules queued initially */ } /* cpu_data index starts at zero */ @@ -741,11 +741,24 @@ void smtc_forward_irq(unsigned int irq) static void smtc_ipi_qdump(void) { int i; + struct smtc_ipi *temp; for (i = 0; i < NR_CPUS ;i++) { - printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", + pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, IPIQ[i].depth); + temp = IPIQ[i].head; + + while (temp != IPIQ[i].tail) { + pr_debug("%d %d %d: ", temp->type, temp->dest, + (int)temp->arg); +#ifdef SMTC_IPI_DEBUG + pr_debug("%u %lu\n", temp->sender, temp->stamp); +#else + pr_debug("\n"); +#endif + temp = temp->flink; + } } } @@ -784,11 +797,16 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) int mtflags; unsigned long tcrestart; extern void r4k_wait_irqoff(void), __pastwait(void); + int set_resched_flag = (type == LINUX_SMP_IPI && + action == SMP_RESCHEDULE_YOURSELF); if (cpu == smp_processor_id()) { printk("Cannot Send IPI to self!\n"); return; } + if (set_resched_flag && IPIQ[cpu].resched_flag != 0) + return; /* There is a reschedule queued already */ + /* Set up a descriptor, to be delivered either promptly or queued */ pipi = smtc_ipi_dq(&freeIPIq); if (pipi == NULL) { @@ -801,6 +819,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) pipi->dest = cpu; if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { /* If not on same VPE, enqueue and send cross-VPE interrupt */ + IPIQ[cpu].resched_flag |= set_resched_flag; smtc_ipi_nq(&IPIQ[cpu], pipi); LOCK_CORE_PRA(); settc(cpu_data[cpu].tc_id); @@ -847,6 +866,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) */ write_tc_c0_tchalt(0); UNLOCK_CORE_PRA(); + IPIQ[cpu].resched_flag |= set_resched_flag; smtc_ipi_nq(&IPIQ[cpu], pipi); } else { postdirect: @@ -996,12 +1016,15 @@ void deferred_smtc_ipi(void) * already enabled. */ local_irq_save(flags); - spin_lock(&q->lock); pipi = __smtc_ipi_dq(q); spin_unlock(&q->lock); - if (pipi != NULL) + if (pipi != NULL) { + if (pipi->type == LINUX_SMP_IPI && + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) + IPIQ[cpu].resched_flag = 0; ipi_decode(pipi); + } /* * The use of the __raw_local restore isn't * as obviously necessary here as in smtc_ipi_replay(), @@ -1082,6 +1105,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm) * with interrupts off */ local_irq_save(flags); + if (pipi->type == LINUX_SMP_IPI && + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) + IPIQ[cpu].resched_flag = 0; ipi_decode(pipi); local_irq_restore(flags); } -- cgit v1.2.3 From 0db2b74e9150651a25ffd2e2285575ce193f763c Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 13 Oct 2009 16:54:01 +0200 Subject: MIPS: Set S-cache linesize to 64-bytes for MTI's S-cache Signed-off-by: Ralf Baechle --- arch/mips/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7159495ee0b..03bd56a2fb6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1013,6 +1013,7 @@ config BOOT_ELF32 config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL + default "6" if MIPS_CPU_SCACHE default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON default "5" -- cgit v1.2.3 From b6b74d5490c3ad88de503e0c5d44e4820b79b678 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 13 Oct 2009 08:52:28 -0700 Subject: MIPS: Octeon: Use write_{un,}lock_irq{restore,save} to set irq affinity Since the locks are used from interrupt context we need the irqsave/irqrestore versions of the locking functions. Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/octeon-irq.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 384f1842bfb..0bda5c5db15 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -182,9 +182,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq) static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) { int cpu; + unsigned long flags; int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - write_lock(&octeon_irq_ciu0_rwlock); + write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); for_each_online_cpu(cpu) { int coreid = cpu_logical_map(cpu); uint64_t en0 = @@ -200,7 +201,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - write_unlock(&octeon_irq_ciu0_rwlock); + write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); return 0; } @@ -299,9 +300,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq) static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) { int cpu; + unsigned long flags; int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - write_lock(&octeon_irq_ciu1_rwlock); + write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); for_each_online_cpu(cpu) { int coreid = cpu_logical_map(cpu); uint64_t en1 = @@ -318,7 +320,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask * * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - write_unlock(&octeon_irq_ciu1_rwlock); + write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); return 0; } -- cgit v1.2.3 From cd847b7857b835f9730d6fc93c3f423fcacc50f7 Mon Sep 17 00:00:00 2001 From: David Daney Date: Tue, 13 Oct 2009 11:26:03 -0700 Subject: MIPS: Octeon: Use lockless interrupt controller operations when possible. Some newer Octeon chips have registers that allow lockless operation of the interrupt controller. Take advantage of them. Signed-off-by: David Daney Signed-off-by: Ralf Baechle --- arch/mips/cavium-octeon/octeon-irq.c | 214 +++++++++++++++++++++++++++++------ 1 file changed, 178 insertions(+), 36 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 0bda5c5db15..6f2acf09328 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -17,6 +17,15 @@ DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); DEFINE_SPINLOCK(octeon_irq_msi_lock); +static int octeon_coreid_for_cpu(int cpu) +{ +#ifdef CONFIG_SMP + return cpu_logical_map(cpu); +#else + return cvmx_get_core_num(); +#endif +} + static void octeon_irq_core_ack(unsigned int irq) { unsigned int bit = irq - OCTEON_IRQ_SW0; @@ -152,11 +161,10 @@ static void octeon_irq_ciu0_disable(unsigned int irq) int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ unsigned long flags; uint64_t en0; -#ifdef CONFIG_SMP int cpu; write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); + int coreid = octeon_coreid_for_cpu(cpu); en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); en0 &= ~(1ull << bit); cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); @@ -167,15 +175,45 @@ static void octeon_irq_ciu0_disable(unsigned int irq) */ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); -#else - int coreid = cvmx_get_core_num(); - local_irq_save(flags); - en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - en0 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); - cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - local_irq_restore(flags); -#endif +} + +/* + * Enable the irq on the current core for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu0_enable_v2(unsigned int irq) +{ + int index = cvmx_get_core_num() * 2; + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); +} + +/* + * Disable the irq on the current core for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu0_disable_v2(unsigned int irq) +{ + int index = cvmx_get_core_num() * 2; + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); +} + +/* + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu0_disable_all_v2(unsigned int irq) +{ + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + int index; + int cpu; + for_each_online_cpu(cpu) { + index = octeon_coreid_for_cpu(cpu) * 2; + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } } #ifdef CONFIG_SMP @@ -187,7 +225,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); + int coreid = octeon_coreid_for_cpu(cpu); uint64_t en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); if (cpumask_test_cpu(cpu, dest)) @@ -205,8 +243,42 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * return 0; } + +/* + * Set affinity for the irq for chips that have the EN*_W1{S,C} + * registers. + */ +static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq, + const struct cpumask *dest) +{ + int cpu; + int index; + u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + for_each_online_cpu(cpu) { + index = octeon_coreid_for_cpu(cpu) * 2; + if (cpumask_test_cpu(cpu, dest)) + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask); + else + cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask); + } + return 0; +} #endif +/* + * Newer octeon chips have support for lockless CIU operation. + */ +static struct irq_chip octeon_irq_chip_ciu0_v2 = { + .name = "CIU0", + .enable = octeon_irq_ciu0_enable_v2, + .disable = octeon_irq_ciu0_disable_all_v2, + .ack = octeon_irq_ciu0_disable_v2, + .eoi = octeon_irq_ciu0_enable_v2, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu0_set_affinity_v2, +#endif +}; + static struct irq_chip octeon_irq_chip_ciu0 = { .name = "CIU0", .enable = octeon_irq_ciu0_enable, @@ -270,11 +342,10 @@ static void octeon_irq_ciu1_disable(unsigned int irq) int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ unsigned long flags; uint64_t en1; -#ifdef CONFIG_SMP int cpu; write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); + int coreid = octeon_coreid_for_cpu(cpu); en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); en1 &= ~(1ull << bit); cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); @@ -285,19 +356,50 @@ static void octeon_irq_ciu1_disable(unsigned int irq) */ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); -#else - int coreid = cvmx_get_core_num(); - local_irq_save(flags); - en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - en1 &= ~(1ull << bit); - cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); - cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - local_irq_restore(flags); -#endif +} + +/* + * Enable the irq on the current core for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu1_enable_v2(unsigned int irq) +{ + int index = cvmx_get_core_num() * 2 + 1; + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); + + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); +} + +/* + * Disable the irq on the current core for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu1_disable_v2(unsigned int irq) +{ + int index = cvmx_get_core_num() * 2 + 1; + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); + + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); +} + +/* + * Disable the irq on the all cores for chips that have the EN*_W1{S,C} + * registers. + */ +static void octeon_irq_ciu1_disable_all_v2(unsigned int irq) +{ + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); + int index; + int cpu; + for_each_online_cpu(cpu) { + index = octeon_coreid_for_cpu(cpu) * 2 + 1; + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } } #ifdef CONFIG_SMP -static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) +static int octeon_irq_ciu1_set_affinity(unsigned int irq, + const struct cpumask *dest) { int cpu; unsigned long flags; @@ -305,7 +407,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask * write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); for_each_online_cpu(cpu) { - int coreid = cpu_logical_map(cpu); + int coreid = octeon_coreid_for_cpu(cpu); uint64_t en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1 (coreid * 2 + 1)); @@ -324,8 +426,42 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask * return 0; } + +/* + * Set affinity for the irq for chips that have the EN*_W1{S,C} + * registers. + */ +static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq, + const struct cpumask *dest) +{ + int cpu; + int index; + u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0); + for_each_online_cpu(cpu) { + index = octeon_coreid_for_cpu(cpu) * 2 + 1; + if (cpumask_test_cpu(cpu, dest)) + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask); + else + cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask); + } + return 0; +} #endif +/* + * Newer octeon chips have support for lockless CIU operation. + */ +static struct irq_chip octeon_irq_chip_ciu1_v2 = { + .name = "CIU0", + .enable = octeon_irq_ciu1_enable_v2, + .disable = octeon_irq_ciu1_disable_all_v2, + .ack = octeon_irq_ciu1_disable_v2, + .eoi = octeon_irq_ciu1_enable_v2, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu1_set_affinity_v2, +#endif +}; + static struct irq_chip octeon_irq_chip_ciu1 = { .name = "CIU1", .enable = octeon_irq_ciu1_enable, @@ -422,6 +558,8 @@ static struct irq_chip octeon_irq_chip_msi = { void __init arch_init_irq(void) { int irq; + struct irq_chip *chip0; + struct irq_chip *chip1; #ifdef CONFIG_SMP /* Set the default affinity to the boot cpu. */ @@ -432,6 +570,16 @@ void __init arch_init_irq(void) if (NR_IRQS < OCTEON_IRQ_LAST) pr_err("octeon_irq_init: NR_IRQS is set too low\n"); + if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || + OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { + chip0 = &octeon_irq_chip_ciu0_v2; + chip1 = &octeon_irq_chip_ciu1_v2; + } else { + chip0 = &octeon_irq_chip_ciu0; + chip1 = &octeon_irq_chip_ciu1; + } + /* 0 - 15 reserved for i8259 master and slave controller. */ /* 17 - 23 Mips internal */ @@ -442,14 +590,12 @@ void __init arch_init_irq(void) /* 24 - 87 CIU_INT_SUM0 */ for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, - handle_percpu_irq); + set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); } /* 88 - 151 CIU_INT_SUM1 */ for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { - set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, - handle_percpu_irq); + set_irq_chip_and_handler(irq, chip1, handle_percpu_irq); } #ifdef CONFIG_PCI_MSI @@ -507,14 +653,10 @@ asmlinkage void plat_irq_dispatch(void) #ifdef CONFIG_HOTPLUG_CPU static int is_irq_enabled_on_cpu(unsigned int irq, unsigned int cpu) { - unsigned int isset; -#ifdef CONFIG_SMP - int coreid = cpu_logical_map(cpu); -#else - int coreid = cvmx_get_core_num(); -#endif + unsigned int isset; + int coreid = octeon_coreid_for_cpu(cpu); int bit = (irq < OCTEON_IRQ_WDOG0) ? - irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; + irq - OCTEON_IRQ_WORKQ0 : irq - OCTEON_IRQ_WDOG0; if (irq < 64) { isset = (cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)) & (1ull << bit)) >> bit; -- cgit v1.2.3 From c2ea1d56eaf084c66177eb5658ff4065e79b36ea Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Tue, 13 Oct 2009 23:23:28 +0200 Subject: MIPS: Avoid potential hazard on Context register set_saved_sp reads Context register. Avoid reading stale value from earlier incomplete write. Issue found and fixed for head.S by Chris Dearman . Signed-off-by: Chris Dearman Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mmu_context.h | 3 +++ arch/mips/kernel/head.S | 1 + 2 files changed, 4 insertions(+) diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index ed331c2e488..6083db58650 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #ifdef CONFIG_MIPS_MT_SMTC #include @@ -36,11 +37,13 @@ extern unsigned long pgd_current[]; #ifdef CONFIG_32BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 25); \ + back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif #ifdef CONFIG_64BIT #define TLBMISS_HANDLER_SETUP() \ write_c0_context((unsigned long) smp_processor_id() << 26); \ + back_to_back_c0_hazard(); \ TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir) #endif diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index 531ce7b1612..ea695d9605e 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -191,6 +191,7 @@ NESTED(kernel_entry, 16, sp) # kernel entry point /* Set the SP after an empty pt_regs. */ PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE PTR_ADDU sp, $28 + back_to_back_c0_hazard set_saved_sp sp, t0, t1 PTR_SUBU sp, 4 * SZREG # init stack pointer -- cgit v1.2.3 From e8d4c342e5cfecb8080c181e881deb35ef99806d Mon Sep 17 00:00:00 2001 From: Zhang Le Date: Fri, 19 Jun 2009 18:01:39 +0800 Subject: MIPS: Loongson 2: Set cpu_has_dc_aliases and cpu_icache_snoops_remote_store Loongson 2 does not have dcache aliases when is using 16k pages. and the And because Loongson 2 doesn't do SMP , cpu_icache_snoops_remote_store does not matter here. Signed-off-by: Zhang Le Signed-off-by: Ralf Baechle --- arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h index ce5b6e270e3..9947e57c91d 100644 --- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -29,7 +29,7 @@ #define cpu_has_cache_cdex_p 0 #define cpu_has_cache_cdex_s 0 #define cpu_has_counter 1 -#define cpu_has_dc_aliases 1 +#define cpu_has_dc_aliases (PAGE_SIZE < 0x4000) #define cpu_has_divec 0 #define cpu_has_dsp 0 #define cpu_has_ejtag 0 @@ -54,6 +54,5 @@ #define cpu_has_vce 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -#define cpu_icache_snoops_remote_store 1 #endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ -- cgit v1.2.3 From 2b5b9b786c177fa4bca1646325a1dd98c4399523 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Wed, 14 Oct 2009 09:56:00 +0200 Subject: MIPS: bcm63xx: Set the correct BCM3302 CPU name For consistency with other BCM63xx SoC set the CPU name to "Broadcom BCM6338" when actually running on that system. Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle --- arch/mips/bcm63xx/cpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 6dc43f0483e..70378bb5e3f 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -284,6 +285,7 @@ void __init bcm63xx_cpu_init(void) { unsigned int tmp, expected_cpu_id; struct cpuinfo_mips *c = ¤t_cpu_data; + unsigned int cpu = smp_processor_id(); /* soc registers location depends on cpu type */ expected_cpu_id = 0; @@ -293,6 +295,7 @@ void __init bcm63xx_cpu_init(void) * BCM6338 as the same PrId as BCM3302 see arch/mips/kernel/cpu-probe.c */ case CPU_BCM3302: + __cpu_name[cpu] = "Broadcom BCM6338"; expected_cpu_id = BCM6338_CPU_ID; bcm63xx_regs_base = bcm96338_regs_base; bcm63xx_irqs = bcm96338_irqs; -- cgit v1.2.3 From fcc152f3bf55cec61167b173774cbf717b0ff5e4 Mon Sep 17 00:00:00 2001 From: Atsushi Nemoto Date: Thu, 3 Sep 2009 22:59:00 +0900 Subject: MIPS: TXx9: Fix spi-baseclk value TXx9 SPI bit rate is calculated by: fBR = fSPI / 2 / (n + 1) (fSPI is SPI master clock freq, i.e. imbusclk freq.) So use imbus_clk / 2 as a spi-baseclk. Signed-off-by: Atsushi Nemoto Signed-off-by: Ralf Baechle --- arch/mips/txx9/generic/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index dfe4720ac82..e10184c1b3e 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -85,7 +85,7 @@ int txx9_ccfg_toeon __initdata = 1; struct clk *clk_get(struct device *dev, const char *id) { if (!strcmp(id, "spi-baseclk")) - return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 4); + return (struct clk *)((unsigned long)txx9_gbus_clock / 2 / 2); if (!strcmp(id, "imbus_clk")) return (struct clk *)((unsigned long)txx9_gbus_clock / 2); return ERR_PTR(-ENOENT); -- cgit v1.2.3 From 44f2c586a3553154bc6549eb696c7716c85f910b Mon Sep 17 00:00:00 2001 From: Manuel Lauss Date: Wed, 14 Oct 2009 12:22:20 +0200 Subject: MIPS: Alchemy: Fix hang with high-frequency edge interrupts The handle_edge_irq() flowhandler disables edge int sources which occur too fast (i.e. another edge comes in before the irq handler function had a chance to finish). Currently, the mask_ack() callback does not ack the edges in hardware, leading to an endless loop in the flowhandler where it tries to shut up the irq source. When I rewrote the alchemy IRQ code I wrongly assumed the mask_ack() callback was only used by the level flowhandler, hence it omitted the (at the time pointless) edge acks. Turned out I was wrong; so here is a complete mask_ack implementation for Alchemy IC, which fixes the above mentioned problem. Signed-off-by: Manuel Lauss Signed-off-by: Ralf Baechle --- arch/mips/alchemy/common/irq.c | 34 ++++++++++++++++++++++++++-------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index c88c821b4c3..d670928afcf 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -354,6 +354,28 @@ static void au1x_ic1_ack(unsigned int irq_nr) au_sync(); } +static void au1x_ic0_maskack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + + au_writel(1 << bit, IC0_WAKECLR); + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_RISINGCLR); + au_writel(1 << bit, IC0_FALLINGCLR); + au_sync(); +} + +static void au1x_ic1_maskack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + + au_writel(1 << bit, IC1_WAKECLR); + au_writel(1 << bit, IC1_MASKCLR); + au_writel(1 << bit, IC1_RISINGCLR); + au_writel(1 << bit, IC1_FALLINGCLR); + au_sync(); +} + static int au1x_ic1_setwake(unsigned int irq, unsigned int on) { unsigned int bit = irq - AU1000_INTC1_INT_BASE; @@ -379,25 +401,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) /* * irq_chips for both ICs; this way the mask handlers can be * as short as possible. - * - * NOTE: the ->ack() callback is used by the handle_edge_irq - * flowhandler only, the ->mask_ack() one by handle_level_irq, - * so no need for an irq_chip for each type of irq (level/edge). */ static struct irq_chip au1x_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, /* edge */ + .ack = au1x_ic0_ack, .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_mask, /* level */ + .mask_ack = au1x_ic0_maskack, .unmask = au1x_ic0_unmask, .set_type = au1x_ic_settype, }; static struct irq_chip au1x_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, /* edge */ + .ack = au1x_ic1_ack, .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_mask, /* level */ + .mask_ack = au1x_ic1_maskack, .unmask = au1x_ic1_unmask, .set_type = au1x_ic_settype, .set_wake = au1x_ic1_setwake, -- cgit v1.2.3 From 55f4e1d4fe88f16f773ba5bb31ce8c1ae63724af Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Wed, 21 Oct 2009 22:51:46 +0800 Subject: MIPS: Oprofile: Rename cpu_type from godson2 to loongson2 Unify the naming method between kernel and the user-space oprofile tool. Because loongson is used instead of godson in most of the places, we agreed to use loongson instead, which will simplify future maintenance. Signed-off-by: Wu Zhangjin Acked-by: Robert Richter Signed-off-by: Ralf Baechle --- arch/mips/oprofile/op_model_loongson2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index deed1d5d498..575cd147347 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -22,7 +22,7 @@ * otherwise, the oprofile tool will not recognize this and complain about * "cpu_type 'unset' is not valid". */ -#define LOONGSON2_CPU_TYPE "mips/godson2" +#define LOONGSON2_CPU_TYPE "mips/loongson2" #define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) #define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) -- cgit v1.2.3 From 049a31afe16e733a54f7da7fdf845034758c6ee1 Mon Sep 17 00:00:00 2001 From: Arnaud Patard Date: Tue, 20 Oct 2009 10:27:47 +0200 Subject: MIPS: O32: Fix ppoll sys_ppoll syscall needs to use a compat handler on 64bit kernels with o32 user-space. Signed-off-by: Arnaud Patard Signed-off-by: Ralf Baechle --- arch/mips/kernel/scall64-o32.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S index ba0dde6465a..14dde4ca932 100644 --- a/arch/mips/kernel/scall64-o32.S +++ b/arch/mips/kernel/scall64-o32.S @@ -505,7 +505,7 @@ sys_call_table: PTR sys_fchmodat PTR sys_faccessat /* 4300 */ PTR compat_sys_pselect6 - PTR sys_ppoll + PTR compat_sys_ppoll PTR sys_unshare PTR sys_splice PTR sys32_sync_file_range /* 4305 */ -- cgit v1.2.3