From 280f681db9da837d527b430813b2045e1dda332c Mon Sep 17 00:00:00 2001 From: Philippe Langlais Date: Wed, 19 Oct 2011 10:22:22 +0200 Subject: arch: arm: ST-E HSI controller Change-Id: Ibe70431ede8a9707b37e3394c22beb9acc42d8cb Signed-off-by: Pawel Szyszuk --- arch/arm/mach-ux500/include/mach/hsi.h | 122 +++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm/mach-ux500/include/mach/hsi.h (limited to 'arch/arm/mach-ux500/include/mach/hsi.h') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h new file mode 100644 index 00000000000..030e35e729b --- /dev/null +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * License Terms: GNU General Public License v2 + */ + +#ifndef __MACH_HSI_H +#define __MACH_HSI_H + +#include + +/* HSIT register offsets */ +#define STE_HSI_TX_ID 0x000 +#define STE_HSI_TX_MODE 0x004 +#define STE_HSI_TX_STATE 0x008 +#define STE_HSI_TX_IOSTATE 0x00C +#define STE_HSI_TX_BUFSTATE 0x010 +#define STE_HSI_TX_DIVISOR 0x014 +#define STE_HSI_TX_PARITY 0x018 +#define STE_HSI_TX_BREAK 0x01C +#define STE_HSI_TX_CHANNELS 0x020 +#define STE_HSI_TX_FLUSHBITS 0x024 +#define STE_HSI_TX_PRIORITY 0x028 +#define STE_HSI_TX_BURSTLEN 0x02C +#define STE_HSI_TX_PREAMBLE 0x030 +#define STE_HSI_TX_DATASWAP 0x034 +#define STE_HSI_TX_FRAMELENX 0x080 +#define STE_HSI_TX_BUFFERX 0x0C0 +#define STE_HSI_TX_BASEX 0x100 +#define STE_HSI_TX_SPANX 0x140 +#define STE_HSI_TX_GAUGEX 0x180 +#define STE_HSI_TX_WATERMARKX 0x1C0 +#define STE_HSI_TX_DMAEN 0x200 +#define STE_HSI_TX_WATERMARKIS 0x204 +#define STE_HSI_TX_WATERMARKIM 0x208 +#define STE_HSI_TX_WATERMARKIC 0x20C +#define STE_HSI_TX_WATERMARKID 0x210 +#define STE_HSI_TX_PERIPHID0 0xFE0 +#define STE_HSI_TX_PERIPHID1 0xFE4 +#define STE_HSI_TX_PERIPHID2 0xFE8 +#define STE_HSI_TX_PERIPHID3 0xFEC + +/* HSIR register offsets */ +#define STE_HSI_RX_ID 0x000 +#define STE_HSI_RX_MODE 0x004 +#define STE_HSI_RX_STATE 0x008 +#define STE_HSI_RX_BUFSTATE 0x00C +#define STE_HSI_RX_THRESHOLD 0x010 +#define STE_HSI_RX_PARITY 0x014 +#define STE_HSI_RX_DETECTOR 0x018 +#define STE_HSI_RX_EXCEP 0x01C +#define STE_HSI_RX_ACK 0x020 +#define STE_HSI_RX_CHANNELS 0x024 +#define STE_HSI_RX_REALTIME 0x028 +#define STE_HSI_RX_OVERRUN 0x02C +#define STE_HSI_RX_OVERRUNACK 0x030 +#define STE_HSI_RX_PREAMBLE 0x034 +#define STE_HSI_RX_PIPEGAUGE 0x038 +#define STE_HSI_RX_STATICCONFID 0x03C +#define STE_HSI_RX_BUFFERX 0x080 +#define STE_HSI_RX_FRAMELENX 0x0C0 +#define STE_HSI_RX_BASEX 0x100 +#define STE_HSI_RX_SPANX 0x140 +#define STE_HSI_RX_GAUGEX 0x180 +#define STE_HSI_RX_WATERMARKX 0x1C0 +#define STE_HSI_RX_DMAEN 0x200 +#define STE_HSI_RX_WATERMARKIS 0x204 +#define STE_HSI_RX_WATERMARKIM 0x208 +#define STE_HSI_RX_WATERMARKIC 0x20C +#define STE_HSI_RX_WATERMARKID 0x210 +#define STE_HSI_RX_OVERRUNMIS 0x214 +#define STE_HSI_RX_OVERRUNIM 0x218 +#define STE_HSI_RX_EXCEPMIS 0x21C +#define STE_HSI_RX_EXCEPIM 0x220 +#define STE_HSI_RX_PERIPHID0 0xFE0 +#define STE_HSI_RX_PERIPHID1 0xFE4 +#define STE_HSI_RX_PERIPHID2 0xFE8 +#define STE_HSI_RX_PERIPHID3 0xFEC + +/* HSI states */ +#define STE_HSI_STATE_IDLE 0x00 +#define STE_HSI_STATE_START 0x01 +#define STE_HSI_STATE_TRANSMIT 0x02 +#define STE_HSI_STATE_BREAK 0x03 +#define STE_HSI_STATE_FLUSH 0x04 +#define STE_HSI_STATE_HALT 0x05 + +/* HSI exceptions */ +#define STE_HSI_EXCEP_TIMEOUT 0x01 +#define STE_HSI_EXCEP_OVERRUN 0x02 +#define STE_HSI_EXCEP_BREAK 0x04 +#define STE_HSI_EXCEP_PARITY 0x08 + +/* HSI modes */ +#define STE_HSI_MODE_SLEEP 0x00 +#define STE_HSI_MODE_STREAM 0x01 +#define STE_HSI_MODE_FRAME 0x02 +#define STE_HSI_MODE_PIPELINED 0x03 +#define STE_HSI_MODE_FAILSAFE 0x04 + +#define STE_HSI_MAX_BUFFERS 32 + +/* Max channels of STE HSI controller */ +#define STE_HSI_MAX_CHANNELS 4 + +struct stedma40_chan_cfg; + +struct ste_hsi_port_cfg { +#ifdef CONFIG_STE_DMA40 + bool (*dma_filter)(struct dma_chan *chan, void *filter_param); + struct stedma40_chan_cfg *dma_tx_cfg; + struct stedma40_chan_cfg *dma_rx_cfg; +#endif +}; + +struct ste_hsi_platform_data { + int num_ports; + int use_dma; + struct ste_hsi_port_cfg *port_cfg; +}; + +#endif -- cgit v1.2.3 From 93a1c0f145a36dac2731771406f7a54b2301652b Mon Sep 17 00:00:00 2001 From: Pawel Szyszuk Date: Thu, 7 Jul 2011 15:16:33 +0100 Subject: ARM: U8500: ST-E HSI: DMA burst and PIPE support Added support for HSIR PIPELINED mode (also in drivers/hsi) Added DMA max burst (in DMA words) as a parameter in hsi.h DMA channel high priority set to TRUE for HSI ST-Ericsson ID: 356625 ST-Ericsson Linux next: NA ST-Ericsson FOSS-OUT ID: Trivial Change-Id: Id842e61343ce5013992337db085fcbe91dd5b9f7 Signed-off-by: Pawel Szyszuk Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/32180 Reviewed-by: Yann GAUTIER Reviewed-by: Andrew LYNN --- arch/arm/mach-ux500/include/mach/hsi.h | 5 +++- drivers/hsi/controllers/ste_hsi.c | 51 ++++++++++++++++++++++++++++------ 2 files changed, 47 insertions(+), 9 deletions(-) (limited to 'arch/arm/mach-ux500/include/mach/hsi.h') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h index 030e35e729b..1d2ab206e27 100644 --- a/arch/arm/mach-ux500/include/mach/hsi.h +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -63,6 +63,7 @@ #define STE_HSI_RX_SPANX 0x140 #define STE_HSI_RX_GAUGEX 0x180 #define STE_HSI_RX_WATERMARKX 0x1C0 +#define STE_HSI_RX_FRAMEBURSTCNT 0x1E0 #define STE_HSI_RX_DMAEN 0x200 #define STE_HSI_RX_WATERMARKIS 0x204 #define STE_HSI_RX_WATERMARKIM 0x208 @@ -101,7 +102,9 @@ #define STE_HSI_MAX_BUFFERS 32 /* Max channels of STE HSI controller */ -#define STE_HSI_MAX_CHANNELS 4 +#define STE_HSI_MAX_CHANNELS 2 + +#define STE_HSI_DMA_MAX_BURST 1 struct stedma40_chan_cfg; diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c index 8ac1363c14c..a9cd343fd53 100644 --- a/drivers/hsi/controllers/ste_hsi.c +++ b/drivers/hsi/controllers/ste_hsi.c @@ -198,9 +198,19 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) ste_hsi->tx_base + STE_HSI_TX_BASEX + 4 * i); writel(buffers - 1, ste_hsi->tx_base + STE_HSI_TX_SPANX + 4 * i); - writel(buffers - 1, - ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); + + /* + * The DMA burst request and the buffer occupation interrupt are + * asserted when the free space in the corresponding channel buffer + * is greater than the value programmed in TX_WATERMARKX field. + * The field value must be less than the corresponding SPAN value. + */ +#ifdef CONFIG_STE_DMA40 + writel(STE_HSI_DMA_MAX_BURST-1, + ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); +#else /* IRQ mode */ writel(0, ste_hsi->tx_base + STE_HSI_TX_WATERMARKX + 4 * i); +#endif } /* @@ -215,7 +225,16 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) * Configure RX */ writel(pcontext->rx_mode, ste_hsi->rx_base + STE_HSI_RX_MODE); - writel(0, ste_hsi->rx_base + STE_HSI_RX_PARITY); + + if (STE_HSI_MODE_PIPELINED == pcontext->rx_mode) + /* + * 0x0F: The READY line is negated after the start of the + * 16th frame reception in PIPELINED mode. + */ + writel(0x0F, ste_hsi->rx_base + STE_HSI_RX_FRAMEBURSTCNT); + else + writel(0, ste_hsi->rx_base + STE_HSI_RX_FRAMEBURSTCNT); + writel(pcontext->rx_channels, ste_hsi->rx_base + STE_HSI_RX_CHANNELS); /* Calculate buffers number per channel */ buffers = STE_HSI_MAX_BUFFERS / pcontext->rx_channels; @@ -226,9 +245,19 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) ste_hsi->rx_base + STE_HSI_RX_BASEX + 4 * i); writel(buffers - 1, ste_hsi->rx_base + STE_HSI_RX_SPANX + 4 * i); - writel(buffers - 1, - ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); + + /* + * The DMA burst request and the buffer occupation interrupt are + * asserted when the busy space in the corresponding channel buffer + * is greater than the value programmed in RX_WATERMARKX field. + * The field value must be less than the corresponding SPAN value. + */ +#ifdef CONFIG_STE_DMA40 + writel(STE_HSI_DMA_MAX_BURST-1, + ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); +#else /* IRQ mode */ writel(0, ste_hsi->rx_base + STE_HSI_RX_WATERMARKX + 4 * i); +#endif } /* @@ -642,13 +671,13 @@ static int ste_hsi_setup_dma(struct hsi_client *cl) .src_addr = 0, /* dynamic data */ .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, .direction = DMA_FROM_DEVICE, - .src_maxburst = 1, + .src_maxburst = STE_HSI_DMA_MAX_BURST, }; struct dma_slave_config tx_conf = { .dst_addr = 0, /* dynamic data */ .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, .direction = DMA_TO_DEVICE, - .dst_maxburst = 1, + .dst_maxburst = STE_HSI_DMA_MAX_BURST, }; if (!ste_hsi->use_dma) @@ -1279,7 +1308,13 @@ static int ste_hsi_setup(struct hsi_client *cl) ste_hsi->context->tx_mode = cl->tx_cfg.mode; ste_hsi->context->tx_divisor = div; ste_hsi->context->tx_channels = cl->tx_cfg.channels; - ste_hsi->context->rx_mode = cl->rx_cfg.mode; + + if ((HSI_FLOW_PIPE == cl->rx_cfg.flow) && + (HSI_MODE_FRAME == cl->rx_cfg.mode)) + ste_hsi->context->rx_mode = STE_HSI_MODE_PIPELINED; + else + ste_hsi->context->rx_mode = cl->rx_cfg.mode; + ste_hsi->context->rx_channels = cl->rx_cfg.channels; } -- cgit v1.2.3 From d9256f71b58049048681e0b1360b71cfa1940ffb Mon Sep 17 00:00:00 2001 From: Pawel Szyszuk Date: Thu, 6 Oct 2011 12:35:01 +0100 Subject: ARM: U9500: HSI registers update to DB8500 V2 spec ST-Ericsson Linux next: NA ST-Ericsson ID: 365681 ST-Ericsson FOSS-OUT ID: NA Change-Id: I396c2a4d44ded438308e358aa0ad976a397d4dd6 Signed-off-by: Pawel Szyszuk Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/33224 Reviewed-by: Christopher BLAIR Reviewed-by: Derek MORTON Reviewed-by: Andrew LYNN --- arch/arm/mach-ux500/include/mach/hsi.h | 11 +++++------ drivers/hsi/controllers/ste_hsi.c | 7 ++----- 2 files changed, 7 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-ux500/include/mach/hsi.h') diff --git a/arch/arm/mach-ux500/include/mach/hsi.h b/arch/arm/mach-ux500/include/mach/hsi.h index 1d2ab206e27..58d33249cae 100644 --- a/arch/arm/mach-ux500/include/mach/hsi.h +++ b/arch/arm/mach-ux500/include/mach/hsi.h @@ -16,13 +16,11 @@ #define STE_HSI_TX_IOSTATE 0x00C #define STE_HSI_TX_BUFSTATE 0x010 #define STE_HSI_TX_DIVISOR 0x014 -#define STE_HSI_TX_PARITY 0x018 #define STE_HSI_TX_BREAK 0x01C #define STE_HSI_TX_CHANNELS 0x020 #define STE_HSI_TX_FLUSHBITS 0x024 #define STE_HSI_TX_PRIORITY 0x028 -#define STE_HSI_TX_BURSTLEN 0x02C -#define STE_HSI_TX_PREAMBLE 0x030 +#define STE_HSI_TX_STATICCONFID 0x02C #define STE_HSI_TX_DATASWAP 0x034 #define STE_HSI_TX_FRAMELENX 0x080 #define STE_HSI_TX_BUFFERX 0x0C0 @@ -31,10 +29,11 @@ #define STE_HSI_TX_GAUGEX 0x180 #define STE_HSI_TX_WATERMARKX 0x1C0 #define STE_HSI_TX_DMAEN 0x200 -#define STE_HSI_TX_WATERMARKIS 0x204 +#define STE_HSI_TX_WATERMARKMIS 0x204 #define STE_HSI_TX_WATERMARKIM 0x208 #define STE_HSI_TX_WATERMARKIC 0x20C #define STE_HSI_TX_WATERMARKID 0x210 +#define STE_HSI_TX_WATERMARKIS 0x214 #define STE_HSI_TX_PERIPHID0 0xFE0 #define STE_HSI_TX_PERIPHID1 0xFE4 #define STE_HSI_TX_PERIPHID2 0xFE8 @@ -46,7 +45,6 @@ #define STE_HSI_RX_STATE 0x008 #define STE_HSI_RX_BUFSTATE 0x00C #define STE_HSI_RX_THRESHOLD 0x010 -#define STE_HSI_RX_PARITY 0x014 #define STE_HSI_RX_DETECTOR 0x018 #define STE_HSI_RX_EXCEP 0x01C #define STE_HSI_RX_ACK 0x020 @@ -65,7 +63,7 @@ #define STE_HSI_RX_WATERMARKX 0x1C0 #define STE_HSI_RX_FRAMEBURSTCNT 0x1E0 #define STE_HSI_RX_DMAEN 0x200 -#define STE_HSI_RX_WATERMARKIS 0x204 +#define STE_HSI_RX_WATERMARKMIS 0x204 #define STE_HSI_RX_WATERMARKIM 0x208 #define STE_HSI_RX_WATERMARKIC 0x20C #define STE_HSI_RX_WATERMARKID 0x210 @@ -73,6 +71,7 @@ #define STE_HSI_RX_OVERRUNIM 0x218 #define STE_HSI_RX_EXCEPMIS 0x21C #define STE_HSI_RX_EXCEPIM 0x220 +#define STE_HSI_RX_WATERMARKIS 0x224 #define STE_HSI_RX_PERIPHID0 0xFE0 #define STE_HSI_RX_PERIPHID1 0xFE4 #define STE_HSI_RX_PERIPHID2 0xFE8 diff --git a/drivers/hsi/controllers/ste_hsi.c b/drivers/hsi/controllers/ste_hsi.c index fe43d7b2133..8348a66697d 100644 --- a/drivers/hsi/controllers/ste_hsi.c +++ b/drivers/hsi/controllers/ste_hsi.c @@ -141,8 +141,6 @@ static void ste_hsi_init_registers(struct ste_hsi_controller *ste_hsi) writel(0, ste_hsi->tx_base + STE_HSI_TX_FLUSHBITS); /* TO DO: TX channel priorities will be implemented later */ writel(0, ste_hsi->tx_base + STE_HSI_TX_PRIORITY); - writel(0, ste_hsi->tx_base + STE_HSI_TX_BURSTLEN); - writel(0, ste_hsi->tx_base + STE_HSI_TX_PREAMBLE); writel(0, ste_hsi->tx_base + STE_HSI_TX_DATASWAP); writel(0, ste_hsi->tx_base + STE_HSI_TX_DMAEN); writel(0, ste_hsi->tx_base + STE_HSI_TX_WATERMARKID); @@ -187,7 +185,6 @@ static void ste_hsi_setup_registers(struct ste_hsi_controller *ste_hsi) */ writel(pcontext->tx_mode, ste_hsi->tx_base + STE_HSI_TX_MODE); writel(pcontext->tx_divisor, ste_hsi->tx_base + STE_HSI_TX_DIVISOR); - writel(0, ste_hsi->tx_base + STE_HSI_TX_PARITY); writel(pcontext->tx_channels, ste_hsi->tx_base + STE_HSI_TX_CHANNELS); /* Calculate buffers number per channel */ buffers = STE_HSI_MAX_BUFFERS / pcontext->tx_channels; @@ -879,7 +876,7 @@ static void ste_hsi_rx_tasklet(unsigned long data) u32 irq_status, irq_mask; unsigned int i; - irq_status = readl(ste_hsi->rx_base + STE_HSI_RX_WATERMARKIS); + irq_status = readl(ste_hsi->rx_base + STE_HSI_RX_WATERMARKMIS); if (!irq_status) goto out; @@ -927,7 +924,7 @@ static void ste_hsi_tx_tasklet(unsigned long data) u32 irq_status, irq_mask; unsigned int i; - irq_status = readl(ste_hsi->tx_base + STE_HSI_TX_WATERMARKIS); + irq_status = readl(ste_hsi->tx_base + STE_HSI_TX_WATERMARKMIS); if (!irq_status) goto out; -- cgit v1.2.3