From 2104da90a9aeef31ff6441d171a7d0492088f1d0 Mon Sep 17 00:00:00 2001 From: Lee Nicks Date: Mon, 7 Nov 2005 00:58:10 -0800 Subject: [PATCH] ppc32: add watchdog & RTC support for Marvell EV64360BP board This patch adds watchdog, RTC support for Marvell EV64360BP board. Signed-off-by: Lee Nicks Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/configs/ev64360_defconfig | 73 +++++++++++++++++++++++++++----------- arch/ppc/platforms/ev64360.c | 12 +++++++ arch/ppc/syslib/Makefile | 1 + 3 files changed, 66 insertions(+), 20 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/configs/ev64360_defconfig b/arch/ppc/configs/ev64360_defconfig index de9bbb791db..d471e578dcb 100644 --- a/arch/ppc/configs/ev64360_defconfig +++ b/arch/ppc/configs/ev64360_defconfig @@ -1,17 +1,17 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.13-rc5 -# Fri Aug 5 15:18:23 2005 +# Linux kernel version: 2.6.14 +# Fri Oct 28 19:15:34 2005 # CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_HAVE_DEC_LOCK=y CONFIG_PPC=y CONFIG_PPC32=y CONFIG_GENERIC_NVRAM=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y # # Code maturity level options @@ -26,6 +26,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32 # General setup # CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y @@ -35,6 +36,7 @@ CONFIG_SYSCTL=y CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set +CONFIG_INITRAMFS_SOURCE="" # CONFIG_EMBEDDED is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -74,7 +76,7 @@ CONFIG_TAU=y # CONFIG_TAU_AVERAGE is not set # CONFIG_KEXEC is not set # CONFIG_CPU_FREQ is not set -# CONFIG_PM is not set +# CONFIG_WANT_EARLY_SERIAL is not set CONFIG_PPC_STD_MMU=y CONFIG_NOT_COHERENT_CACHE=y @@ -86,22 +88,18 @@ CONFIG_NOT_COHERENT_CACHE=y # CONFIG_KATANA is not set # CONFIG_WILLOW is not set # CONFIG_CPCI690 is not set -# CONFIG_PCORE is not set # CONFIG_POWERPMC250 is not set # CONFIG_CHESTNUT is not set # CONFIG_SPRUCE is not set # CONFIG_HDPU is not set # CONFIG_EV64260 is not set # CONFIG_LOPEC is not set -# CONFIG_MCPN765 is not set # CONFIG_MVME5100 is not set # CONFIG_PPLUS is not set # CONFIG_PRPMC750 is not set # CONFIG_PRPMC800 is not set # CONFIG_SANDPOINT is not set # CONFIG_RADSTONE_PPC7D is not set -# CONFIG_ADIR is not set -# CONFIG_K2 is not set # CONFIG_PAL4 is not set # CONFIG_GEMINI is not set # CONFIG_EST8260 is not set @@ -138,10 +136,13 @@ CONFIG_FLATMEM_MANUAL=y # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set CONFIG_BINFMT_ELF=y CONFIG_BINFMT_MISC=y CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE="console=ttyMM0,115200 root=/dev/mtdblock1 rw rootfstype=jffs2" +# CONFIG_PM is not set +# CONFIG_SOFTWARE_SUSPEND is not set CONFIG_SECCOMP=y CONFIG_ISA_DMA_API=y @@ -152,7 +153,6 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCI_LEGACY_PROC is not set -# CONFIG_PCI_NAMES is not set # # PCCARD (PCMCIA/CardBus) support @@ -206,13 +206,18 @@ CONFIG_SYN_COOKIES=y # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_TUNNEL is not set -CONFIG_IP_TCPDIAG=y -# CONFIG_IP_TCPDIAG_IPV6 is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_BIC=y # CONFIG_IPV6 is not set # CONFIG_NETFILTER is not set +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + # # SCTP Configuration (EXPERIMENTAL) # @@ -239,6 +244,7 @@ CONFIG_TCP_CONG_BIC=y # CONFIG_HAMRADIO is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_IEEE80211 is not set # # Device Drivers @@ -251,6 +257,11 @@ CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_FW_LOADER is not set +# +# Connector - unified userspace <-> kernelspace linker +# +# CONFIG_CONNECTOR is not set + # # Memory Technology Devices (MTD) # @@ -358,7 +369,6 @@ CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=32768 CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" # CONFIG_LBD is not set # CONFIG_CDROM_PKTCDVD is not set @@ -379,6 +389,7 @@ CONFIG_IOSCHED_CFQ=y # # SCSI device support # +# CONFIG_RAID_ATTRS is not set # CONFIG_SCSI is not set # @@ -419,6 +430,10 @@ CONFIG_NETDEVICES=y # # CONFIG_ARCNET is not set +# +# PHY device support +# + # # Ethernet (10 or 100Mbit) # @@ -434,6 +449,7 @@ CONFIG_NETDEVICES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set +# CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SK98LIN is not set # CONFIG_TIGON3 is not set @@ -446,6 +462,7 @@ CONFIG_MV643XX_ETH_0=y # # Ethernet (10000 Mbit) # +# CONFIG_CHELSIO_T1 is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set @@ -547,7 +564,20 @@ CONFIG_LEGACY_PTY_COUNT=256 # # Watchdog Cards # -# CONFIG_WATCHDOG is not set +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_MV64X60_WDT=y + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set # CONFIG_NVRAM is not set CONFIG_GEN_RTC=y # CONFIG_GEN_RTC_X is not set @@ -571,7 +601,6 @@ CONFIG_GEN_RTC=y # I2C support # # CONFIG_I2C is not set -# CONFIG_I2C_SENSOR is not set # # Dallas's 1-wire bus @@ -582,12 +611,17 @@ CONFIG_GEN_RTC=y # Hardware Monitoring support # CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set # CONFIG_HWMON_DEBUG_CHIP is not set # # Misc devices # +# +# Multimedia Capabilities Port drivers +# + # # Multimedia devices # @@ -651,10 +685,6 @@ CONFIG_EXT2_FS=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set - -# -# XFS support -# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -663,6 +693,7 @@ CONFIG_INOTIFY=y CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set # # CD-ROM/DVD Filesystems @@ -683,11 +714,10 @@ CONFIG_DNOTIFY=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_SYSFS=y -# CONFIG_DEVPTS_FS_XATTR is not set CONFIG_TMPFS=y -# CONFIG_TMPFS_XATTR is not set # CONFIG_HUGETLB_PAGE is not set CONFIG_RAMFS=y +# CONFIG_RELAYFS_FS is not set # # Miscellaneous filesystems @@ -735,6 +765,7 @@ CONFIG_SUNRPC=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set # # Partition Types @@ -751,6 +782,7 @@ CONFIG_MSDOS_PARTITION=y # Library routines # # CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y @@ -767,6 +799,7 @@ CONFIG_ZLIB_DEFLATE=y # CONFIG_PRINTK_TIME is not set # CONFIG_DEBUG_KERNEL is not set CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_SERIAL_TEXT_DEBUG is not set # # Security options diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c index b1324564456..b9d844f88c2 100644 --- a/arch/ppc/platforms/ev64360.c +++ b/arch/ppc/platforms/ev64360.c @@ -52,6 +52,8 @@ static u32 ev64360_bus_frequency; unsigned char __res[sizeof(bd_t)]; +TODC_ALLOC(); + static int __init ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) { @@ -182,6 +184,9 @@ ev64360_setup_peripherals(void) EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN); + TODC_INIT(TODC_TYPE_DS1501, 0, 0, + ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8); + mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN, EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0); bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN); @@ -496,6 +501,13 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5, ppc_md.power_off = ev64360_power_off; ppc_md.halt = ev64360_halt; ppc_md.find_end_of_memory = ev64360_find_end_of_memory; + ppc_md.init = NULL; + + ppc_md.time_init = todc_time_init; + ppc_md.set_rtc_time = todc_set_rtc_time; + ppc_md.get_rtc_time = todc_get_rtc_time; + ppc_md.nvram_read_val = todc_direct_read_val; + ppc_md.nvram_write_val = todc_direct_write_val; ppc_md.calibrate_decr = ev64360_calibrate_decr; #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE) diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index b4ef15b45c4..2e58c210522 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -46,6 +46,7 @@ obj-$(CONFIG_BAMBOO) += pci_auto.o todc_time.o obj-$(CONFIG_CPCI690) += todc_time.o pci_auto.o obj-$(CONFIG_EBONY) += pci_auto.o todc_time.o obj-$(CONFIG_EV64260) += todc_time.o pci_auto.o +obj-$(CONFIG_EV64360) += todc_time.o obj-$(CONFIG_CHESTNUT) += mv64360_pic.o pci_auto.o obj-$(CONFIG_GEMINI) += open_pic.o obj-$(CONFIG_GT64260) += gt64260_pic.o -- cgit v1.2.3 From fcc188e7fdddd8b23f900e485e6b3db05e7375f4 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Mon, 7 Nov 2005 00:58:11 -0800 Subject: [PATCH] ppc32: Allow ERPN for early serial to depend on CPU type The PowerPC 440SPe supports up to 16 GB of RAM, and therefore its IO registers are at 0x4_xxxx_xxxx instead of being at 0x1_xxxx_xxxx like most other PPC 440 chips. To allow for this, this patch moves the definition of the ERPN used for mapping UART0 from being hard-coded in the head_44x.S assembly code to being defined in ibm44x.h. Signed-off-by: Roland Dreier Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/kernel/head_44x.S | 4 ++-- include/asm-ppc/ibm44x.h | 7 ++++++- 2 files changed, 8 insertions(+), 3 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/head_44x.S b/arch/ppc/kernel/head_44x.S index 8b49679fad5..677c571aa27 100644 --- a/arch/ppc/kernel/head_44x.S +++ b/arch/ppc/kernel/head_44x.S @@ -190,8 +190,8 @@ skpinv: addi r4,r4,1 /* Increment */ /* xlat fields */ lis r4,UART0_PHYS_IO_BASE@h /* RPN depends on SoC */ -#ifndef CONFIG_440EP - ori r4,r4,0x0001 /* ERPN is 1 for second 4GB page */ +#ifdef UART0_PHYS_ERPN + ori r4,r4,UART0_PHYS_ERPN /* Add ERPN if above 4GB */ #endif /* attrib fields */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index e5374be86ae..197a9ff23dd 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -34,12 +34,17 @@ /* Lowest TLB slot consumed by the default pinned TLBs */ #define PPC44x_LOW_SLOT 63 -/* LS 32-bits of UART0 physical address location for early serial text debug */ +/* + * Least significant 32-bits and extended real page number (ERPN) of + * UART0 physical address location for early serial text debug + */ #if defined(CONFIG_440SP) +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0xf0000200 #elif defined(CONFIG_440EP) #define UART0_PHYS_IO_BASE 0xe0000000 #else +#define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0x40000200 #endif -- cgit v1.2.3 From 41aace4fe81e3da52fa80b8380e5d2d084f77691 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Mon, 7 Nov 2005 00:58:12 -0800 Subject: [PATCH] ppc32: Dump error status for both PLB segments on 440SP The PowerPC 440SP SoC has two Processor Local Bus (PLB) segments (a high-throughput segment and a low-latency segment). Fix our PLB register definitions to cope with this, and add code to dump the status of both segments when a machine check occurs. Signed-off-by: Roland Dreier Cc: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/syslib/ibm44x_common.c | 11 +++++++++++ include/asm-ppc/ibm44x.h | 18 ++++++++++++++++++ 2 files changed, 29 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c index 5152c8e4134..ebae2e2fcea 100644 --- a/arch/ppc/syslib/ibm44x_common.c +++ b/arch/ppc/syslib/ibm44x_common.c @@ -214,9 +214,20 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo /* Called from machine_check_exception */ void platform_machine_check(struct pt_regs *regs) { +#ifdef CONFIG_440SP + printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", + mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), + mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH), + mfdcr(DCRN_PLB0_BESRL)); + printk("PLB1: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", + mfdcr(DCRN_PLB1_BEARH), mfdcr(DCRN_PLB1_BEARL), + mfdcr(DCRN_PLB1_ACR), mfdcr(DCRN_PLB1_BESRH), + mfdcr(DCRN_PLB1_BESRL)); +#else printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x\n", mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESR)); +#endif printk("POB0: BEAR=0x%08x%08x BESR0=0x%08x BESR1=0x%08x\n", mfdcr(DCRN_POB0_BEARH), mfdcr(DCRN_POB0_BEARL), mfdcr(DCRN_POB0_BESR0), mfdcr(DCRN_POB0_BESR1)); diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index 197a9ff23dd..0c2ba03a1d4 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -302,6 +302,23 @@ #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ +#if defined(CONFIG_440SP) +/* 440SP PLB Arbiter DCRs */ +#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ +#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ + +#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */ +#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */ +#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */ +#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */ +#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */ + +#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */ +#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */ +#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */ +#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */ +#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */ +#else /* 440GP/GX PLB Arbiter DCRs */ #define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ #define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ @@ -309,6 +326,7 @@ #define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ #define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ #define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ +#endif /* 440GP/GX PLB to OPB bridge DCRs */ #define DCRN_POB0_BESR0 0x090 -- cgit v1.2.3 From b0f7b8bc57ee90138a7c429951457027a90c326f Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Mon, 7 Nov 2005 00:58:13 -0800 Subject: [PATCH] ppc32: Add 440SPe support Add support for the AMCC PowerPC 440SPe SoC, including PCI Express in root port mode. Signed-off-by: Roland Dreier Cc: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/powerpc/kernel/cputable.c | 10 + arch/ppc/platforms/4xx/Kconfig | 8 +- arch/ppc/platforms/4xx/Makefile | 1 + arch/ppc/platforms/4xx/ppc440spe.c | 148 +++++++++++++ arch/ppc/platforms/4xx/ppc440spe.h | 66 ++++++ arch/ppc/syslib/Makefile | 1 + arch/ppc/syslib/ibm440sp_common.c | 4 +- arch/ppc/syslib/ibm44x_common.c | 2 +- arch/ppc/syslib/ppc440spe_pcie.c | 442 +++++++++++++++++++++++++++++++++++++ arch/ppc/syslib/ppc440spe_pcie.h | 149 +++++++++++++ arch/ppc/syslib/ppc4xx_pic.c | 37 +++- include/asm-ppc/ibm44x.h | 55 +++-- 12 files changed, 904 insertions(+), 19 deletions(-) create mode 100644 arch/ppc/platforms/4xx/ppc440spe.c create mode 100644 arch/ppc/platforms/4xx/ppc440spe.h create mode 100644 arch/ppc/syslib/ppc440spe_pcie.c create mode 100644 arch/ppc/syslib/ppc440spe_pcie.h (limited to 'arch/ppc') diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 33c63bcf69f..cc4e9eb1c13 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c @@ -929,6 +929,16 @@ struct cpu_spec cpu_specs[] = { .icache_bsize = 32, .dcache_bsize = 32, }, + { /* 440SPe Rev. A */ + .pvr_mask = 0xff000fff, + .pvr_value = 0x53000890, + .cpu_name = "440SPe Rev. A", + .cpu_features = CPU_FTR_SPLIT_ID_CACHE | + CPU_FTR_USE_TB, + .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, + .icache_bsize = 32, + .dcache_bsize = 32, + }, #endif /* CONFIG_44x */ #ifdef CONFIG_FSL_BOOKE { /* e200z5 */ diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index 76f4476cab4..108d5a730f8 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -124,9 +124,13 @@ config 440SP depends on LUAN default y +config 440SPE + bool + default n + config 440 bool - depends on 440GP || 440SP || 440EP + depends on 440GP || 440SP || 440SPE || 440EP default y config 440A @@ -168,7 +172,7 @@ config XILINX_OCP config IBM_EMAC4 bool - depends on 440GX || 440SP + depends on 440GX || 440SP || 440SPE default y config BIOS_FIXUP diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index 1dd6d7fd6a9..694accdb59f 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_440EP) += ibm440ep.o obj-$(CONFIG_440GP) += ibm440gp.o obj-$(CONFIG_440GX) += ibm440gx.o obj-$(CONFIG_440SP) += ibm440sp.o +obj-$(CONFIG_440SPE) += ppc440spe.o obj-$(CONFIG_405EP) += ibm405ep.o obj-$(CONFIG_405GPR) += ibm405gpr.o obj-$(CONFIG_VIRTEX_II_PRO) += virtex-ii_pro.o diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c new file mode 100644 index 00000000000..6139a0b3393 --- /dev/null +++ b/arch/ppc/platforms/4xx/ppc440spe.c @@ -0,0 +1,148 @@ +/* + * arch/ppc/platforms/4xx/ppc440spe.c + * + * PPC440SPe I/O descriptions + * + * Roland Dreier + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * Matt Porter + * Copyright 2002-2005 MontaVista Software Inc. + * + * Eugene Surovegin or + * Copyright (c) 2003, 2004 Zultys Technologies + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ +#include +#include +#include +#include +#include + +static struct ocp_func_emac_data ppc440spe_emac0_def = { + .rgmii_idx = -1, /* No RGMII */ + .rgmii_mux = -1, /* No RGMII */ + .zmii_idx = -1, /* No ZMII */ + .zmii_mux = -1, /* No ZMII */ + .mal_idx = 0, /* MAL device index */ + .mal_rx_chan = 0, /* MAL rx channel number */ + .mal_tx_chan = 0, /* MAL tx channel number */ + .wol_irq = 61, /* WOL interrupt number */ + .mdio_idx = -1, /* No shared MDIO */ + .tah_idx = -1, /* No TAH */ +}; +OCP_SYSFS_EMAC_DATA() + +static struct ocp_func_mal_data ppc440spe_mal0_def = { + .num_tx_chans = 1, /* Number of TX channels */ + .num_rx_chans = 1, /* Number of RX channels */ + .txeob_irq = 38, /* TX End Of Buffer IRQ */ + .rxeob_irq = 39, /* RX End Of Buffer IRQ */ + .txde_irq = 34, /* TX Descriptor Error IRQ */ + .rxde_irq = 35, /* RX Descriptor Error IRQ */ + .serr_irq = 33, /* MAL System Error IRQ */ + .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */ +}; +OCP_SYSFS_MAL_DATA() + +static struct ocp_func_iic_data ppc440spe_iic0_def = { + .fast_mode = 0, /* Use standad mode (100Khz) */ +}; + +static struct ocp_func_iic_data ppc440spe_iic1_def = { + .fast_mode = 0, /* Use standad mode (100Khz) */ +}; +OCP_SYSFS_IIC_DATA() + +struct ocp_def core_ocp[] = { + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 0, + .paddr = PPC440SPE_UART0_ADDR, + .irq = UART0_INT, + .pm = IBM_CPM_UART0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 1, + .paddr = PPC440SPE_UART1_ADDR, + .irq = UART1_INT, + .pm = IBM_CPM_UART1, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_16550, + .index = 2, + .paddr = PPC440SPE_UART2_ADDR, + .irq = UART2_INT, + .pm = IBM_CPM_UART2, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 0, + .paddr = 0x00000004f0000400ULL, + .irq = 2, + .pm = IBM_CPM_IIC0, + .additions = &ppc440spe_iic0_def, + .show = &ocp_show_iic_data + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_IIC, + .index = 1, + .paddr = 0x00000004f0000500ULL, + .irq = 3, + .pm = IBM_CPM_IIC1, + .additions = &ppc440spe_iic1_def, + .show = &ocp_show_iic_data + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_GPIO, + .index = 0, + .paddr = 0x00000004f0000700ULL, + .irq = OCP_IRQ_NA, + .pm = IBM_CPM_GPIO0, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_MAL, + .paddr = OCP_PADDR_NA, + .irq = OCP_IRQ_NA, + .pm = OCP_CPM_NA, + .additions = &ppc440spe_mal0_def, + .show = &ocp_show_mal_data, + }, + { .vendor = OCP_VENDOR_IBM, + .function = OCP_FUNC_EMAC, + .index = 0, + .paddr = 0x00000004f0000800ULL, + .irq = 60, + .pm = OCP_CPM_NA, + .additions = &ppc440spe_emac0_def, + .show = &ocp_show_emac_data, + }, + { .vendor = OCP_VENDOR_INVALID + } +}; + +/* Polarity and triggering settings for internal interrupt sources */ +struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = { + { .polarity = 0xffffffff, + .triggering = 0x010f0004, + .ext_irq_mask = 0x00000000, + }, + { .polarity = 0xffffffff, + .triggering = 0x001f8040, + .ext_irq_mask = 0x00007c30, /* IRQ6 - IRQ7, IRQ8 - IRQ12 */ + }, + { .polarity = 0xffffffff, + .triggering = 0x00000000, + .ext_irq_mask = 0x000000fc, /* IRQ0 - IRQ5 */ + }, + { .polarity = 0xffffffff, + .triggering = 0x00000000, + .ext_irq_mask = 0x00000000, + }, +}; diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h new file mode 100644 index 00000000000..2216846973b --- /dev/null +++ b/arch/ppc/platforms/4xx/ppc440spe.h @@ -0,0 +1,66 @@ +/* + * arch/ppc/platforms/4xx/ibm440spe.h + * + * PPC440SPe definitions + * + * Roland Dreier + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * Matt Porter + * Copyright 2004-2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifdef __KERNEL__ +#ifndef __PPC_PLATFORMS_PPC440SPE_H +#define __PPC_PLATFORMS_PPC440SPE_H + +#include + +#include + +/* UART */ +#define PPC440SPE_UART0_ADDR 0x00000004f0000200ULL +#define PPC440SPE_UART1_ADDR 0x00000004f0000300ULL +#define PPC440SPE_UART2_ADDR 0x00000004f0000600ULL +#define UART0_INT 0 +#define UART1_INT 1 +#define UART2_INT 37 + +/* Clock and Power Management */ +#define IBM_CPM_IIC0 0x80000000 /* IIC interface */ +#define IBM_CPM_IIC1 0x40000000 /* IIC interface */ +#define IBM_CPM_PCI 0x20000000 /* PCI bridge */ +#define IBM_CPM_CPU 0x02000000 /* processor core */ +#define IBM_CPM_DMA 0x01000000 /* DMA controller */ +#define IBM_CPM_BGO 0x00800000 /* PLB to OPB bus arbiter */ +#define IBM_CPM_BGI 0x00400000 /* OPB to PLB bridge */ +#define IBM_CPM_EBC 0x00200000 /* External Bux Controller */ +#define IBM_CPM_EBM 0x00100000 /* Ext Bus Master Interface */ +#define IBM_CPM_DMC 0x00080000 /* SDRAM peripheral controller */ +#define IBM_CPM_PLB 0x00040000 /* PLB bus arbiter */ +#define IBM_CPM_SRAM 0x00020000 /* SRAM memory controller */ +#define IBM_CPM_PPM 0x00002000 /* PLB Performance Monitor */ +#define IBM_CPM_UIC1 0x00001000 /* Universal Interrupt Controller */ +#define IBM_CPM_GPIO0 0x00000800 /* General Purpose IO (??) */ +#define IBM_CPM_GPT 0x00000400 /* General Purpose Timers */ +#define IBM_CPM_UART0 0x00000200 /* serial port 0 */ +#define IBM_CPM_UART1 0x00000100 /* serial port 1 */ +#define IBM_CPM_UART2 0x00000100 /* serial port 1 */ +#define IBM_CPM_UIC0 0x00000080 /* Universal Interrupt Controller */ +#define IBM_CPM_TMRCLK 0x00000040 /* CPU timers */ +#define IBM_CPM_EMAC0 0x00000020 /* EMAC 0 */ + +#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \ + | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \ + | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \ + | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \ + | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \ + | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \ + | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 ) +#endif /* __PPC_PLATFORMS_PPC440SP_H */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 2e58c210522..13dff1e51f1 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_440EP) += ibm440gx_common.o obj-$(CONFIG_440GP) += ibm440gp_common.o obj-$(CONFIG_440GX) += ibm440gx_common.o obj-$(CONFIG_440SP) += ibm440gx_common.o ibm440sp_common.o +obj-$(CONFIG_440SPE) += ibm440gx_common.o ibm440sp_common.o ppc440spe_pcie.o ifeq ($(CONFIG_4xx),y) ifeq ($(CONFIG_VIRTEX_II_PRO),y) obj-$(CONFIG_40x) += xilinx_pic.o diff --git a/arch/ppc/syslib/ibm440sp_common.c b/arch/ppc/syslib/ibm440sp_common.c index 417d4cff77a..cdafda127d8 100644 --- a/arch/ppc/syslib/ibm440sp_common.c +++ b/arch/ppc/syslib/ibm440sp_common.c @@ -1,7 +1,7 @@ /* * arch/ppc/syslib/ibm440sp_common.c * - * PPC440SP system library + * PPC440SP/PPC440SPe system library * * Matt Porter * Copyright 2002-2005 MontaVista Software Inc. @@ -35,7 +35,7 @@ unsigned long __init ibm440sp_find_end_of_memory(void) u32 mem_size = 0; /* Read two bank sizes and sum */ - for (i=0; i<2; i++) + for (i=0; i< MQ0_NUM_BANKS; i++) switch (mfdcr(DCRN_MQ0_BS0BAS + i) & MQ0_CONFIG_SIZE_MASK) { case MQ0_CONFIG_SIZE_8M: mem_size += PPC44x_MEM_SIZE_8M; diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c index ebae2e2fcea..a5bef9d163a 100644 --- a/arch/ppc/syslib/ibm44x_common.c +++ b/arch/ppc/syslib/ibm44x_common.c @@ -214,7 +214,7 @@ void __init ibm44x_platform_init(unsigned long r3, unsigned long r4, unsigned lo /* Called from machine_check_exception */ void platform_machine_check(struct pt_regs *regs) { -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) printk("PLB0: BEAR=0x%08x%08x ACR= 0x%08x BESR= 0x%08x%08x\n", mfdcr(DCRN_PLB0_BEARH), mfdcr(DCRN_PLB0_BEARL), mfdcr(DCRN_PLB0_ACR), mfdcr(DCRN_PLB0_BESRH), diff --git a/arch/ppc/syslib/ppc440spe_pcie.c b/arch/ppc/syslib/ppc440spe_pcie.c new file mode 100644 index 00000000000..1509fc1ddfb --- /dev/null +++ b/arch/ppc/syslib/ppc440spe_pcie.c @@ -0,0 +1,442 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "ppc440spe_pcie.h" + +static int +pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 *val) +{ + struct pci_controller *hose = bus->sysdata; + + if (PCI_SLOT(devfn) != 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + offset += devfn << 12; + + /* + * Note: the caller has already checked that offset is + * suitably aligned and that len is 1, 2 or 4. + */ + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16(hose->cfg_data + offset); + break; + default: + *val = in_le32(hose->cfg_data + offset); + break; + } + + if (0) printk("%s: read %x(%d) @ %x\n", __func__, *val, len, offset); + + return PCIBIOS_SUCCESSFUL; +} + +static int +pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, + int len, u32 val) +{ + struct pci_controller *hose = bus->sysdata; + + if (PCI_SLOT(devfn) != 1) + return PCIBIOS_DEVICE_NOT_FOUND; + + offset += devfn << 12; + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16(hose->cfg_data + offset, val); + break; + default: + out_le32(hose->cfg_data + offset, val); + break; + } + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops pcie_pci_ops = +{ + .read = pcie_read_config, + .write = pcie_write_config +}; + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static void check_error(void) +{ + u32 valPE0, valPE1, valPE2; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) { + printk(KERN_INFO "PCIE: SDR0_PEGPLLLCT1 reset error 0x%8x\n", valPE0); + } + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if ( !(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n"); + } + + /* SDR0_PExRCSSET rstdl */ + if ( !(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n"); + } + + /* SDR0_PExRCSSET rstpyn */ + if ( (valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n"); + } + + /* SDR0_PExRCSSET hldplb */ + if ( (valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n"); + } + + /* SDR0_PExRCSSET rdy */ + if ( (valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n"); + } + + /* SDR0_PExRCSSET shutdown */ + if ( (valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n"); + } +} + +/* + * Initialize PCI Express core as described in User Manual section 27.12.1 + */ +int ppc440spe_init_pcie(void) +{ + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + check_error(); + + printk(KERN_INFO "PCIE initialization OK\n"); + + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) + printk(KERN_INFO "PESDR_PLLCT2 resistance calibration failed (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT2)); + + /* De-assert reset of PCIe PLL, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(3); + + return 0; +} + +int ppc440spe_init_pcie_rootport(int port) +{ + static int core_init; + void __iomem *utl_base; + u32 val = 0; + int i; + + if (!core_init) { + ++core_init; + i = ppc440spe_init_pcie(); + if (i) + return i; + } + + /* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + */ + switch (port) { + case 0: + SDR_WRITE(PESDR0_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X8 << 12); + + SDR_WRITE(PESDR0_UTLSET1, 0x21222222); + SDR_WRITE(PESDR0_UTLSET2, 0x11000000); + + SDR_WRITE(PESDR0_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL3SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + + SDR_WRITE(PESDR0_RCSSET, + (SDR_READ(PESDR0_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 1: + SDR_WRITE(PESDR1_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + + SDR_WRITE(PESDR1_UTLSET1, 0x21222222); + SDR_WRITE(PESDR1_UTLSET2, 0x11000000); + + SDR_WRITE(PESDR1_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR1_HSSL3SET1, 0x35000000); + + SDR_WRITE(PESDR1_RCSSET, + (SDR_READ(PESDR1_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + + case 2: + SDR_WRITE(PESDR2_DLPSET, PTYPE_ROOT_PORT << 20 | LNKW_X4 << 12); + + SDR_WRITE(PESDR2_UTLSET1, 0x21222222); + SDR_WRITE(PESDR2_UTLSET2, 0x11000000); + + SDR_WRITE(PESDR2_HSSL0SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL1SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL2SET1, 0x35000000); + SDR_WRITE(PESDR2_HSSL3SET1, 0x35000000); + + SDR_WRITE(PESDR2_RCSSET, + (SDR_READ(PESDR2_RCSSET) & ~(1 << 24 | 1 << 16)) | 1 << 12); + break; + } + + mdelay(1000); + + switch (port) { + case 0: val = SDR_READ(PESDR0_RCSSTS); break; + case 1: val = SDR_READ(PESDR1_RCSSTS); break; + case 2: val = SDR_READ(PESDR2_RCSSTS); break; + } + + if (!(val & (1 << 20))) + printk(KERN_INFO "PCIE%d: PGRST inactive\n", port); + else + printk(KERN_WARNING "PGRST for PCIE%d failed %08x\n", port, val); + + switch (port) { + case 0: printk(KERN_INFO "PCIE0: LOOP %08x\n", SDR_READ(PESDR0_LOOP)); break; + case 1: printk(KERN_INFO "PCIE1: LOOP %08x\n", SDR_READ(PESDR1_LOOP)); break; + case 2: printk(KERN_INFO "PCIE2: LOOP %08x\n", SDR_READ(PESDR2_LOOP)); break; + } + + /* + * Map UTL registers at 0xc_1000_0n00 + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x10000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x10001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x10002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + } + + utl_base = ioremap64(0xc10000000ull + 0x1000 * port, 0x100); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); + + iounmap(utl_base); + + /* + * We map PCI Express configuration access into the 512MB regions + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), 0x40000000); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + + case 1: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), 0x80000000); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; + + case 2: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), 0xc0000000); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; + } + + /* + * Check for VC0 active and assert RDY. + */ + switch (port) { + case 0: + if (!(SDR_READ(PESDR0_RCSSTS) & (1 << 16))) + printk(KERN_WARNING "PCIE0: VC0 not active\n"); + SDR_WRITE(PESDR0_RCSSET, SDR_READ(PESDR0_RCSSET) | 1 << 20); + break; + case 1: + if (!(SDR_READ(PESDR1_RCSSTS) & (1 << 16))) + printk(KERN_WARNING "PCIE0: VC0 not active\n"); + SDR_WRITE(PESDR1_RCSSET, SDR_READ(PESDR1_RCSSET) | 1 << 20); + break; + case 2: + if (!(SDR_READ(PESDR2_RCSSTS) & (1 << 16))) + printk(KERN_WARNING "PCIE0: VC0 not active\n"); + SDR_WRITE(PESDR2_RCSSET, SDR_READ(PESDR2_RCSSET) | 1 << 20); + break; + } + +#if 0 + /* Dump all config regs */ + for (i = 0x300; i <= 0x320; ++i) + printk("[%04x] 0x%08x\n", i, SDR_READ(i)); + for (i = 0x340; i <= 0x353; ++i) + printk("[%04x] 0x%08x\n", i, SDR_READ(i)); + for (i = 0x370; i <= 0x383; ++i) + printk("[%04x] 0x%08x\n", i, SDR_READ(i)); + for (i = 0x3a0; i <= 0x3a2; ++i) + printk("[%04x] 0x%08x\n", i, SDR_READ(i)); + for (i = 0x3c0; i <= 0x3c3; ++i) + printk("[%04x] 0x%08x\n", i, SDR_READ(i)); +#endif + + mdelay(100); + + return 0; +} + +void ppc440spe_setup_pcie(struct pci_controller *hose, int port) +{ + void __iomem *mbase; + + /* + * Map 16MB, which is enough for 4 bits of bus # + */ + hose->cfg_data = ioremap64(0xc40000000ull + port * 0x40000000, + 1 << 24); + hose->ops = &pcie_pci_ops; + + /* + * Set bus numbers on our root port + */ + mbase = ioremap64(0xc50000000ull + port * 0x40000000, 4096); + out_8(mbase + PCI_PRIMARY_BUS, 0); + out_8(mbase + PCI_SECONDARY_BUS, 0); + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0); + out_le32(mbase + PECFG_POM0LAL, hose->mem_space.start); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), hose->mem_space.start); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(hose->mem_space.end - hose->mem_space.start) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), hose->mem_space.start); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(hose->mem_space.end - hose->mem_space.start) | 3); + + break; + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), 0x0000000d); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), hose->mem_space.start); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(hose->mem_space.end - hose->mem_space.start) | 3); + break; + } + + /* Set up 16GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffc); + out_le32(mbase + PECFG_BAR0LMPA, 0); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16(mbase + PCI_COMMAND, + in_le16(mbase + PCI_COMMAND) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + iounmap(mbase); +} diff --git a/arch/ppc/syslib/ppc440spe_pcie.h b/arch/ppc/syslib/ppc440spe_pcie.h new file mode 100644 index 00000000000..55b765ad327 --- /dev/null +++ b/arch/ppc/syslib/ppc440spe_pcie.h @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PPC_SYSLIB_PPC440SPE_PCIE_H +#define __PPC_SYSLIB_PPC440SPE_PCIE_H + +#define DCRN_SDR0_CFGADDR 0x00e +#define DCRN_SDR0_CFGDATA 0x00f + +#define DCRN_PCIE0_BASE 0x100 +#define DCRN_PCIE1_BASE 0x120 +#define DCRN_PCIE2_BASE 0x140 +#define PCIE0 DCRN_PCIE0_BASE +#define PCIE1 DCRN_PCIE1_BASE +#define PCIE2 DCRN_PCIE2_BASE + +#define DCRN_PEGPL_CFGBAH(base) (base + 0x00) +#define DCRN_PEGPL_CFGBAL(base) (base + 0x01) +#define DCRN_PEGPL_CFGMSK(base) (base + 0x02) +#define DCRN_PEGPL_MSGBAH(base) (base + 0x03) +#define DCRN_PEGPL_MSGBAL(base) (base + 0x04) +#define DCRN_PEGPL_MSGMSK(base) (base + 0x05) +#define DCRN_PEGPL_OMR1BAH(base) (base + 0x06) +#define DCRN_PEGPL_OMR1BAL(base) (base + 0x07) +#define DCRN_PEGPL_OMR1MSKH(base) (base + 0x08) +#define DCRN_PEGPL_OMR1MSKL(base) (base + 0x09) +#define DCRN_PEGPL_REGBAH(base) (base + 0x12) +#define DCRN_PEGPL_REGBAL(base) (base + 0x13) +#define DCRN_PEGPL_REGMSK(base) (base + 0x14) +#define DCRN_PEGPL_SPECIAL(base) (base + 0x15) + +/* + * System DCRs (SDRs) + */ +#define PESDR0_PLLLCT1 0x03a0 +#define PESDR0_PLLLCT2 0x03a1 +#define PESDR0_PLLLCT3 0x03a2 + +#define PESDR0_UTLSET1 0x0300 +#define PESDR0_UTLSET2 0x0301 +#define PESDR0_DLPSET 0x0302 +#define PESDR0_LOOP 0x0303 +#define PESDR0_RCSSET 0x0304 +#define PESDR0_RCSSTS 0x0305 +#define PESDR0_HSSL0SET1 0x0306 +#define PESDR0_HSSL0SET2 0x0307 +#define PESDR0_HSSL0STS 0x0308 +#define PESDR0_HSSL1SET1 0x0309 +#define PESDR0_HSSL1SET2 0x030a +#define PESDR0_HSSL1STS 0x030b +#define PESDR0_HSSL2SET1 0x030c +#define PESDR0_HSSL2SET2 0x030d +#define PESDR0_HSSL2STS 0x030e +#define PESDR0_HSSL3SET1 0x030f +#define PESDR0_HSSL3SET2 0x0310 +#define PESDR0_HSSL3STS 0x0311 +#define PESDR0_HSSL4SET1 0x0312 +#define PESDR0_HSSL4SET2 0x0313 +#define PESDR0_HSSL4STS 0x0314 +#define PESDR0_HSSL5SET1 0x0315 +#define PESDR0_HSSL5SET2 0x0316 +#define PESDR0_HSSL5STS 0x0317 +#define PESDR0_HSSL6SET1 0x0318 +#define PESDR0_HSSL6SET2 0x0319 +#define PESDR0_HSSL6STS 0x031a +#define PESDR0_HSSL7SET1 0x031b +#define PESDR0_HSSL7SET2 0x031c +#define PESDR0_HSSL7STS 0x031d +#define PESDR0_HSSCTLSET 0x031e +#define PESDR0_LANE_ABCD 0x031f +#define PESDR0_LANE_EFGH 0x0320 + +#define PESDR1_UTLSET1 0x0340 +#define PESDR1_UTLSET2 0x0341 +#define PESDR1_DLPSET 0x0342 +#define PESDR1_LOOP 0x0343 +#define PESDR1_RCSSET 0x0344 +#define PESDR1_RCSSTS 0x0345 +#define PESDR1_HSSL0SET1 0x0346 +#define PESDR1_HSSL0SET2 0x0347 +#define PESDR1_HSSL0STS 0x0348 +#define PESDR1_HSSL1SET1 0x0349 +#define PESDR1_HSSL1SET2 0x034a +#define PESDR1_HSSL1STS 0x034b +#define PESDR1_HSSL2SET1 0x034c +#define PESDR1_HSSL2SET2 0x034d +#define PESDR1_HSSL2STS 0x034e +#define PESDR1_HSSL3SET1 0x034f +#define PESDR1_HSSL3SET2 0x0350 +#define PESDR1_HSSL3STS 0x0351 +#define PESDR1_HSSCTLSET 0x0352 +#define PESDR1_LANE_ABCD 0x0353 + +#define PESDR2_UTLSET1 0x0370 +#define PESDR2_UTLSET2 0x0371 +#define PESDR2_DLPSET 0x0372 +#define PESDR2_LOOP 0x0373 +#define PESDR2_RCSSET 0x0374 +#define PESDR2_RCSSTS 0x0375 +#define PESDR2_HSSL0SET1 0x0376 +#define PESDR2_HSSL0SET2 0x0377 +#define PESDR2_HSSL0STS 0x0378 +#define PESDR2_HSSL1SET1 0x0379 +#define PESDR2_HSSL1SET2 0x037a +#define PESDR2_HSSL1STS 0x037b +#define PESDR2_HSSL2SET1 0x037c +#define PESDR2_HSSL2SET2 0x037d +#define PESDR2_HSSL2STS 0x037e +#define PESDR2_HSSL3SET1 0x037f +#define PESDR2_HSSL3SET2 0x0380 +#define PESDR2_HSSL3STS 0x0381 +#define PESDR2_HSSCTLSET 0x0382 +#define PESDR2_LANE_ABCD 0x0383 + +/* + * UTL register offsets + */ +#define PEUTL_PBBSZ 0x20 +#define PEUTL_OPDBSZ 0x68 +#define PEUTL_IPHBSZ 0x70 +#define PEUTL_IPDBSZ 0x78 +#define PEUTL_OUTTR 0x90 +#define PEUTL_INTR 0x98 +#define PEUTL_PCTL 0xa0 +#define PEUTL_RCIRQEN 0xb8 + +/* + * Config space register offsets + */ +#define PECFG_BAR0LMPA 0x210 +#define PECFG_BAR0HMPA 0x214 +#define PECFG_PIMEN 0x33c +#define PECFG_PIM0LAL 0x340 +#define PECFG_PIM0LAH 0x344 +#define PECFG_POM0LAL 0x380 +#define PECFG_POM0LAH 0x384 + +int ppc440spe_init_pcie(void); +int ppc440spe_init_pcie_rootport(int port); +void ppc440spe_setup_pcie(struct pci_controller *hose, int port); + +#endif /* __PPC_SYSLIB_PPC440SPE_PCIE_H */ diff --git a/arch/ppc/syslib/ppc4xx_pic.c b/arch/ppc/syslib/ppc4xx_pic.c index 0b435633a0d..aa4165144ec 100644 --- a/arch/ppc/syslib/ppc4xx_pic.c +++ b/arch/ppc/syslib/ppc4xx_pic.c @@ -38,6 +38,7 @@ extern unsigned char ppc4xx_uic_ext_irq_cfg[] __attribute__ ((weak)); #define IRQ_MASK_UICx(irq) (1 << (31 - ((irq) & 0x1f))) #define IRQ_MASK_UIC1(irq) IRQ_MASK_UICx(irq) #define IRQ_MASK_UIC2(irq) IRQ_MASK_UICx(irq) +#define IRQ_MASK_UIC3(irq) IRQ_MASK_UICx(irq) #define UIC_HANDLERS(n) \ static void ppc4xx_uic##n##_enable(unsigned int irq) \ @@ -88,7 +89,38 @@ static void ppc4xx_uic##n##_end(unsigned int irq) \ .end = ppc4xx_uic##n##_end, \ } \ -#if NR_UICS == 3 +#if NR_UICS == 4 +#define ACK_UIC0_PARENT +#define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC); +#define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC2NC); +#define ACK_UIC3_PARENT mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC3NC); +UIC_HANDLERS(0); +UIC_HANDLERS(1); +UIC_HANDLERS(2); +UIC_HANDLERS(3); + +static int ppc4xx_pic_get_irq(struct pt_regs *regs) +{ + u32 uic0 = mfdcr(DCRN_UIC_MSR(UIC0)); + if (uic0 & UIC0_UIC1NC) + return 64 - ffs(mfdcr(DCRN_UIC_MSR(UIC1))); + else if (uic0 & UIC0_UIC2NC) + return 96 - ffs(mfdcr(DCRN_UIC_MSR(UIC2))); + else if (uic0 & UIC0_UIC3NC) + return 128 - ffs(mfdcr(DCRN_UIC_MSR(UIC3))); + else + return uic0 ? 32 - ffs(uic0) : -1; +} + +static void __init ppc4xx_pic_impl_init(void) +{ + /* Enable cascade interrupts in UIC0 */ + ppc_cached_irq_mask[0] |= UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC; + mtdcr(DCRN_UIC_SR(UIC0), UIC0_UIC1NC | UIC0_UIC2NC | UIC0_UIC3NC); + mtdcr(DCRN_UIC_ER(UIC0), ppc_cached_irq_mask[0]); +} + +#elif NR_UICS == 3 #define ACK_UIC0_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC0NC); #define ACK_UIC1_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC); #define ACK_UIC2_PARENT mtdcr(DCRN_UIC_SR(UICB), UICB_UIC2NC); @@ -170,6 +202,9 @@ static struct ppc4xx_uic_impl { { .decl = DECLARE_UIC(1), .base = UIC1 }, #if NR_UICS > 2 { .decl = DECLARE_UIC(2), .base = UIC2 }, +#if NR_UICS > 3 + { .decl = DECLARE_UIC(3), .base = UIC3 }, +#endif #endif #endif }; diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index 0c2ba03a1d4..f835066fb3c 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -41,6 +41,9 @@ #if defined(CONFIG_440SP) #define UART0_PHYS_ERPN 1 #define UART0_PHYS_IO_BASE 0xf0000200 +#elif defined(CONFIG_440SPE) +#define UART0_PHYS_ERPN 4 +#define UART0_PHYS_IO_BASE 0xf0000200 #elif defined(CONFIG_440EP) #define UART0_PHYS_IO_BASE 0xe0000000 #else @@ -61,6 +64,11 @@ #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL +#elif defined(CONFIG_440SPE) +#define PPC44x_IO_PAGE 0x0000000400000000ULL +#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL +#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE +#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL #elif defined(CONFIG_440EP) #define PPC44x_IO_PAGE 0x0000000000000000ULL #define PPC44x_PCICFG_PAGE 0x0000000000000000ULL @@ -76,7 +84,7 @@ /* * 36-bit trap ranges */ -#if defined(CONFIG_440SP) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) #define PPC44x_IO_LO 0xf0000000UL #define PPC44x_IO_HI 0xf0000fffUL #define PPC44x_PCI0CFG_LO 0x0ec00000UL @@ -114,7 +122,7 @@ */ -/* CPRs (440GX and 440SP) */ +/* CPRs (440GX and 440SP/440SPe) */ #define DCRN_CPR_CONFIG_ADDR 0xc #define DCRN_CPR_CONFIG_DATA 0xd @@ -135,7 +143,7 @@ mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ mtdcr(DCRN_CPR_CONFIG_DATA, data);}) -/* SDRs (440GX and 440SP) */ +/* SDRs (440GX and 440SP/440SPe) */ #define DCRN_SDR_CONFIG_ADDR 0xe #define DCRN_SDR_CONFIG_DATA 0xf #define DCRN_SDR_PFC0 0x4100 @@ -185,7 +193,7 @@ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ mtdcr(DCRN_SDR_CONFIG_DATA,data);}) -/* DMA (excluding 440SP) */ +/* DMA (excluding 440SP/440SPe) */ #define DCRN_DMA0_BASE 0x100 #define DCRN_DMA1_BASE 0x108 #define DCRN_DMA2_BASE 0x110 @@ -205,12 +213,20 @@ /* UIC */ #define DCRN_UIC0_BASE 0xc0 #define DCRN_UIC1_BASE 0xd0 -#define DCRN_UIC2_BASE 0x210 -#define DCRN_UICB_BASE 0x200 #define UIC0 DCRN_UIC0_BASE #define UIC1 DCRN_UIC1_BASE + +#ifdef CONFIG_440SPE +#define DCRN_UIC2_BASE 0xe0 +#define DCRN_UIC3_BASE 0xf0 +#define UIC2 DCRN_UIC2_BASE +#define UIC3 DCRN_UIC3_BASE +#else +#define DCRN_UIC2_BASE 0x210 +#define DCRN_UICB_BASE 0x200 #define UIC2 DCRN_UIC2_BASE #define UICB DCRN_UICB_BASE +#endif #define DCRN_UIC_SR(base) (base + 0x0) #define DCRN_UIC_ER(base) (base + 0x2) @@ -223,6 +239,12 @@ #define UIC0_UIC1NC 0x00000002 +#ifdef CONFIG_440SPE +#define UIC0_UIC1NC 0x00000002 +#define UIC0_UIC2NC 0x00200000 +#define UIC0_UIC3NC 0x00008000 +#endif + #define UICB_UIC0NC 0x40000000 #define UICB_UIC1NC 0x10000000 #define UICB_UIC2NC 0x04000000 @@ -302,8 +324,8 @@ #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ -#if defined(CONFIG_440SP) -/* 440SP PLB Arbiter DCRs */ +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) +/* 440SP/440SPe PLB Arbiter DCRs */ #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ @@ -430,9 +452,13 @@ #define PPC44x_MEM_SIZE_1G 0x40000000 #define PPC44x_MEM_SIZE_2G 0x80000000 -/* 440SP memory controller DCRs */ +/* 440SP/440SPe memory controller DCRs */ #define DCRN_MQ0_BS0BAS 0x40 -#define DCRN_MQ0_BS1BAS 0x41 +#if defined(CONFIG_440SP) +#define MQ0_NUM_BANKS 2 +#elif defined(CONFIG_440SPE) +#define MQ0_NUM_BANKS 4 +#endif #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 @@ -444,8 +470,9 @@ #define MQ0_CONFIG_SIZE_512M 0x0000f000 #define MQ0_CONFIG_SIZE_1G 0x0000e000 #define MQ0_CONFIG_SIZE_2G 0x0000c000 +#define MQ0_CONFIG_SIZE_4G 0x00008000 -/* Internal SRAM Controller 440GX/440SP */ +/* Internal SRAM Controller 440GX/440SP/440SPe */ #define DCRN_SRAM0_BASE 0x000 #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) @@ -469,7 +496,7 @@ #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) #define SRAM_DPC_ENABLE 0x80000000 -/* L2 Cache Controller 440GX/440SP */ +/* L2 Cache Controller 440GX/440SP/440SPe */ #define DCRN_L2C0_CFG 0x030 #define L2C_CFG_L2M 0x80000000 #define L2C_CFG_ICU 0x40000000 @@ -633,8 +660,10 @@ #define IIC_CLOCK 50 #undef NR_UICS -#ifdef CONFIG_440GX +#if defined(CONFIG_440GX) #define NR_UICS 3 +#elif defined(CONFIG_440SPE) +#define NR_UICS 4 #else #define NR_UICS 2 #endif -- cgit v1.2.3 From 90eb2665841d7b444602736e2141a01c948f75b1 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Mon, 7 Nov 2005 00:58:14 -0800 Subject: [PATCH] ppc32: Add Yucca (440SPe eval board) platform Add support for AMCC PowerPC 440SPe "Yucca" eval board platform. Signed-off-by: Roland Dreier Cc: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/boot/simple/Makefile | 6 + arch/ppc/platforms/4xx/Kconfig | 11 +- arch/ppc/platforms/4xx/Makefile | 1 + arch/ppc/platforms/4xx/yucca.c | 395 ++++++++++++++++++++++++++++++++++++++++ arch/ppc/platforms/4xx/yucca.h | 111 +++++++++++ arch/ppc/syslib/Makefile | 1 + include/asm-ppc/ibm4xx.h | 4 + 7 files changed, 527 insertions(+), 2 deletions(-) create mode 100644 arch/ppc/platforms/4xx/yucca.c create mode 100644 arch/ppc/platforms/4xx/yucca.h (limited to 'arch/ppc') diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile index b7bd8f61a4a..ff0904ee889 100644 --- a/arch/ppc/boot/simple/Makefile +++ b/arch/ppc/boot/simple/Makefile @@ -79,6 +79,12 @@ zimageinitrd-$(CONFIG_LUAN) := zImage.initrd-TREE entrypoint-$(CONFIG_LUAN) := 0x01000000 extra.o-$(CONFIG_LUAN) := pibs.o + zimage-$(CONFIG_YUCCA) := zImage-TREE +zimageinitrd-$(CONFIG_YUCCA) := zImage.initrd-TREE + end-$(CONFIG_YUCCA) := yucca + entrypoint-$(CONFIG_YUCCA) := 0x01000000 + extra.o-$(CONFIG_YUCCA) := pibs.o + zimage-$(CONFIG_OCOTEA) := zImage-TREE zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE end-$(CONFIG_OCOTEA) := ocotea diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index 108d5a730f8..e70e4c6ec78 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -82,6 +82,12 @@ config LUAN help This option enables support for the IBM PPC440SP evaluation board. +config YUCCA + bool "Yucca" + select WANT_EARLY_SERIAL + help + This option enables support for the AMCC PPC440SPe evaluation board. + config OCOTEA bool "Ocotea" select WANT_EARLY_SERIAL @@ -126,7 +132,8 @@ config 440SP config 440SPE bool - default n + depends on YUCCA + default y config 440 bool @@ -162,7 +169,7 @@ config BOOKE config IBM_OCP bool - depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT + depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT default y config XILINX_OCP diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile index 694accdb59f..c9bb6117095 100644 --- a/arch/ppc/platforms/4xx/Makefile +++ b/arch/ppc/platforms/4xx/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_EBONY) += ebony.o obj-$(CONFIG_EP405) += ep405.o obj-$(CONFIG_BUBINGA) += bubinga.o obj-$(CONFIG_LUAN) += luan.o +obj-$(CONFIG_YUCCA) += yucca.o obj-$(CONFIG_OCOTEA) += ocotea.o obj-$(CONFIG_REDWOOD_5) += redwood5.o obj-$(CONFIG_REDWOOD_6) += redwood6.o diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c new file mode 100644 index 00000000000..e60f4bd437e --- /dev/null +++ b/arch/ppc/platforms/4xx/yucca.c @@ -0,0 +1,395 @@ +/* + * arch/ppc/platforms/4xx/yucca.c + * + * Yucca board specific routines + * + * Roland Dreier (based on luan.c by Matt Porter) + * + * Copyright 2004-2005 MontaVista Software Inc. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +extern bd_t __res; + +static struct ibm44x_clocks clocks __initdata; + +static void __init +yucca_calibrate_decr(void) +{ + unsigned int freq; + + if (mfspr(SPRN_CCR1) & CCR1_TCS) + freq = YUCCA_TMR_CLK; + else + freq = clocks.cpu; + + ibm44x_calibrate_decr(freq); +} + +static int +yucca_show_cpuinfo(struct seq_file *m) +{ + seq_printf(m, "vendor\t\t: AMCC\n"); + seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n"); + + return 0; +} + +static enum { + HOSE_UNKNOWN, + HOSE_PCIX, + HOSE_PCIE0, + HOSE_PCIE1, + HOSE_PCIE2 +} hose_type[4]; + +static inline int +yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) +{ + struct pci_controller *hose = pci_bus_to_hose(dev->bus->number); + + if (hose_type[hose->index] == HOSE_PCIX) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 81, -1, -1, -1 }, /* IDSEL 1 - PCIX0 Slot 0 */ + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + } else if (hose_type[hose->index] == HOSE_PCIE0) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 96, 97, 98, 99 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + } else if (hose_type[hose->index] == HOSE_PCIE1) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 100, 101, 102, 103 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + } else if (hose_type[hose->index] == HOSE_PCIE2) { + static char pci_irq_table[][4] = + /* + * PCI IDSEL/INTPIN->INTLINE + * A B C D + */ + { + { 104, 105, 106, 107 }, + }; + const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4; + return PCI_IRQ_TABLE_LOOKUP; + } + return -1; +} + +static void __init yucca_set_emacdata(void) +{ + struct ocp_def *def; + struct ocp_func_emac_data *emacdata; + + /* Set phy_map, phy_mode, and mac_addr for the EMAC */ + def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0); + emacdata = def->additions; + emacdata->phy_map = 0x00000001; /* Skip 0x00 */ + emacdata->phy_mode = PHY_MODE_GMII; + memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6); +} + +static int __init yucca_pcie_card_present(int port) +{ + void __iomem *pcie_fpga_base; + u16 reg; + + pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); + reg = in_be16(pcie_fpga_base + FPGA_REG1C); + iounmap(pcie_fpga_base); + + switch(port) { + case 0: return !(reg & FPGA_REG1C_PE0_PRSNT); + case 1: return !(reg & FPGA_REG1C_PE1_PRSNT); + case 2: return !(reg & FPGA_REG1C_PE2_PRSNT); + default: return 0; + } +} + +/* + * For the given slot, set rootpoint mode, send power to the slot, + * turn on the green LED and turn off the yellow LED, enable the clock + * and turn off reset. + */ +static void __init yucca_setup_pcie_fpga_rootpoint(int port) +{ + void __iomem *pcie_reg_fpga_base; + u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint; + + pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE); + + switch(port) { + case 0: + rootpoint = FPGA_REG1C_PE0_ROOTPOINT; + endpoint = 0; + power = FPGA_REG1A_PE0_PWRON; + green_led = FPGA_REG1A_PE0_GLED; + clock = FPGA_REG1A_PE0_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE0_YLED; + reset_off = FPGA_REG1C_PE0_PERST; + break; + case 1: + rootpoint = 0; + endpoint = FPGA_REG1C_PE1_ENDPOINT; + power = FPGA_REG1A_PE1_PWRON; + green_led = FPGA_REG1A_PE1_GLED; + clock = FPGA_REG1A_PE1_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE1_YLED; + reset_off = FPGA_REG1C_PE1_PERST; + break; + case 2: + rootpoint = 0; + endpoint = FPGA_REG1C_PE2_ENDPOINT; + power = FPGA_REG1A_PE2_PWRON; + green_led = FPGA_REG1A_PE2_GLED; + clock = FPGA_REG1A_PE2_REFCLK_ENABLE; + yellow_led = FPGA_REG1A_PE2_YLED; + reset_off = FPGA_REG1C_PE2_PERST; + break; + + default: + return; + } + + out_be16(pcie_reg_fpga_base + FPGA_REG1A, + ~(power | clock | green_led) & + (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A))); + out_be16(pcie_reg_fpga_base + FPGA_REG1C, + ~(endpoint | reset_off) & + (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C))); + + /* + * Leave device in reset for a while after powering on the + * slot to give it a chance to initialize. + */ + mdelay(250); + + out_be16(pcie_reg_fpga_base + FPGA_REG1C, + reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C)); + + iounmap(pcie_reg_fpga_base); +} + +static void __init +yucca_setup_hoses(void) +{ + struct pci_controller *hose; + char name[20]; + int i; + + if (0 && ppc440spe_init_pcie()) { + printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n"); + return; + } + + for (i = 0; i <= 2; ++i) { + if (!yucca_pcie_card_present(i)) + continue; + + printk(KERN_INFO "PCIE%d: card present\n", i); + yucca_setup_pcie_fpga_rootpoint(i); + if (ppc440spe_init_pcie_rootport(i)) { + printk(KERN_WARNING "PCIE%d: initialization failed\n", i); + continue; + } + + hose = pcibios_alloc_controller(); + if (!hose) + return; + + sprintf(name, "PCIE%d host bridge", i); + pci_init_resource(&hose->io_resource, + YUCCA_PCIX_LOWER_IO, + YUCCA_PCIX_UPPER_IO, + IORESOURCE_IO, + name); + + hose->mem_space.start = YUCCA_PCIE_LOWER_MEM + + i * YUCCA_PCIE_MEM_SIZE; + hose->mem_space.end = hose->mem_space.start + + YUCCA_PCIE_MEM_SIZE - 1; + + pci_init_resource(&hose->mem_resources[0], + hose->mem_space.start, + hose->mem_space.end, + IORESOURCE_MEM, + name); + + hose->first_busno = 0; + hose->last_busno = 15; + hose_type[hose->index] = HOSE_PCIE0 + i; + + ppc440spe_setup_pcie(hose, i); + hose->last_busno = pciauto_bus_scan(hose, hose->first_busno); + } + + ppc_md.pci_swizzle = common_swizzle; + ppc_md.pci_map_irq = yucca_map_irq; +} + +TODC_ALLOC(); + +static void __init +yucca_early_serial_map(void) +{ + struct uart_port port; + + /* Setup ioremapped serial port access */ + memset(&port, 0, sizeof(port)); + port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8); + port.irq = UART0_INT; + port.uartclk = clocks.uart0; + port.regshift = 0; + port.iotype = SERIAL_IO_MEM; + port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST; + port.line = 0; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 0 failed\n"); + } + + port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8); + port.irq = UART1_INT; + port.uartclk = clocks.uart1; + port.line = 1; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 1 failed\n"); + } + + port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8); + port.irq = UART2_INT; + port.uartclk = BASE_BAUD; + port.line = 2; + + if (early_serial_setup(&port) != 0) { + printk("Early serial init of port 2 failed\n"); + } +} + +static void __init +yucca_setup_arch(void) +{ + yucca_set_emacdata(); + +#if !defined(CONFIG_BDI_SWITCH) + /* + * The Abatron BDI JTAG debugger does not tolerate others + * mucking with the debug registers. + */ + mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM)); +#endif + + /* + * Determine various clocks. + * To be completely correct we should get SysClk + * from FPGA, because it can be changed by on-board switches + * --ebs + */ + /* 440GX and 440SPe clocking is the same - rd */ + ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200); + ocp_sys_info.opb_bus_freq = clocks.opb; + + /* init to some ~sane value until calibrate_delay() runs */ + loops_per_jiffy = 50000000/HZ; + + /* Setup PCIXn host bridges */ + yucca_setup_hoses(); + +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) + ROOT_DEV = Root_RAM0; + else +#endif +#ifdef CONFIG_ROOT_NFS + ROOT_DEV = Root_NFS; +#else + ROOT_DEV = Root_HDA1; +#endif + + yucca_early_serial_map(); + + /* Identify the system */ + printk("Yucca port (Roland Dreier )\n"); +} + +void __init platform_init(unsigned long r3, unsigned long r4, + unsigned long r5, unsigned long r6, unsigned long r7) +{ + ibm44x_platform_init(r3, r4, r5, r6, r7); + + ppc_md.setup_arch = yucca_setup_arch; + ppc_md.show_cpuinfo = yucca_show_cpuinfo; + ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory; + ppc_md.get_irq = NULL; /* Set in ppc4xx_pic_init() */ + + ppc_md.calibrate_decr = yucca_calibrate_decr; +#ifdef CONFIG_KGDB + ppc_md.early_serial_map = yucca_early_serial_map; +#endif +} diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h new file mode 100644 index 00000000000..01a4afea151 --- /dev/null +++ b/arch/ppc/platforms/4xx/yucca.h @@ -0,0 +1,111 @@ +/* + * arch/ppc/platforms/4xx/yucca.h + * + * Yucca board definitions + * + * Roland Dreier (based on luan.h by Matt Porter) + * + * Copyright 2004-2005 MontaVista Software Inc. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_YUCCA_H__ +#define __ASM_YUCCA_H__ + +#include +#include + +/* F/W TLB mapping used in bootloader glue to reset EMAC */ +#define PPC44x_EMAC0_MR0 0xa0000800 + +/* Location of MAC addresses in PIBS image */ +#define PIBS_FLASH_BASE 0xffe00000 +#define PIBS_MAC_BASE (PIBS_FLASH_BASE+0x1b0400) + +/* External timer clock frequency */ +#define YUCCA_TMR_CLK 25000000 + +/* + * FPGA registers + */ +#define YUCCA_FPGA_REG_BASE 0x00000004e2000000ULL +#define YUCCA_FPGA_REG_SIZE 0x24 + +#define FPGA_REG1A 0x1a + +#define FPGA_REG1A_PE0_GLED 0x8000 +#define FPGA_REG1A_PE1_GLED 0x4000 +#define FPGA_REG1A_PE2_GLED 0x2000 +#define FPGA_REG1A_PE0_YLED 0x1000 +#define FPGA_REG1A_PE1_YLED 0x0800 +#define FPGA_REG1A_PE2_YLED 0x0400 +#define FPGA_REG1A_PE0_PWRON 0x0200 +#define FPGA_REG1A_PE1_PWRON 0x0100 +#define FPGA_REG1A_PE2_PWRON 0x0080 +#define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040 +#define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020 +#define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010 +#define FPGA_REG1A_PE_SPREAD0 0x0008 +#define FPGA_REG1A_PE_SPREAD1 0x0004 +#define FPGA_REG1A_PE_SELSOURCE_0 0x0002 +#define FPGA_REG1A_PE_SELSOURCE_1 0x0001 + +#define FPGA_REG1C 0x1c + +#define FPGA_REG1C_PE0_ROOTPOINT 0x8000 +#define FPGA_REG1C_PE1_ENDPOINT 0x4000 +#define FPGA_REG1C_PE2_ENDPOINT 0x2000 +#define FPGA_REG1C_PE0_PRSNT 0x1000 +#define FPGA_REG1C_PE1_PRSNT 0x0800 +#define FPGA_REG1C_PE2_PRSNT 0x0400 +#define FPGA_REG1C_PE0_WAKE 0x0080 +#define FPGA_REG1C_PE1_WAKE 0x0040 +#define FPGA_REG1C_PE2_WAKE 0x0020 +#define FPGA_REG1C_PE0_PERST 0x0010 +#define FPGA_REG1C_PE1_PERST 0x0008 +#define FPGA_REG1C_PE2_PERST 0x0004 + +/* + * Serial port defines + */ +#define RS_TABLE_SIZE 3 + +/* PIBS defined UART mappings, used before early_serial_setup */ +#define UART0_IO_BASE 0xa0000200 +#define UART1_IO_BASE 0xa0000300 +#define UART2_IO_BASE 0xa0000600 + +#define BASE_BAUD 11059200 +#define STD_UART_OP(num) \ + { 0, BASE_BAUD, 0, UART##num##_INT, \ + (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \ + iomem_base: (void*)UART##num##_IO_BASE, \ + io_type: SERIAL_IO_MEM}, + +#define SERIAL_PORT_DFNS \ + STD_UART_OP(0) \ + STD_UART_OP(1) \ + STD_UART_OP(2) + +/* PCI support */ +#define YUCCA_PCIX_LOWER_IO 0x00000000 +#define YUCCA_PCIX_UPPER_IO 0x0000ffff +#define YUCCA_PCIX_LOWER_MEM 0x80000000 +#define YUCCA_PCIX_UPPER_MEM 0x8fffffff +#define YUCCA_PCIE_LOWER_MEM 0x90000000 +#define YUCCA_PCIE_MEM_SIZE 0x10000000 + +#define YUCCA_PCIX_MEM_SIZE 0x10000000 +#define YUCCA_PCIX_MEM_OFFSET 0x00000000 +#define YUCCA_PCIE_MEM_SIZE 0x10000000 +#define YUCCA_PCIE_MEM_OFFSET 0x00000000 + +#endif /* __ASM_YUCCA_H__ */ +#endif /* __KERNEL__ */ diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index 13dff1e51f1..dcd168f9a7a 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -54,6 +54,7 @@ obj-$(CONFIG_GT64260) += gt64260_pic.o obj-$(CONFIG_LOPEC) += pci_auto.o todc_time.o obj-$(CONFIG_HDPU) += pci_auto.o obj-$(CONFIG_LUAN) += pci_auto.o todc_time.o +obj-$(CONFIG_YUCCA) += pci_auto.o todc_time.o obj-$(CONFIG_KATANA) += pci_auto.o obj-$(CONFIG_MV64360) += mv64360_pic.o obj-$(CONFIG_MV64X60) += mv64x60.o mv64x60_win.o diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h index e992369cb8e..6c28ae7807f 100644 --- a/include/asm-ppc/ibm4xx.h +++ b/include/asm-ppc/ibm4xx.h @@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, #include #endif +#if defined(CONFIG_YUCCA) +#include +#endif + #if defined(CONFIG_OCOTEA) #include #endif -- cgit v1.2.3 From 3e9e7c1d0b7a36fb8affb973a054c5098e27baa8 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 7 Nov 2005 00:58:15 -0800 Subject: [PATCH] ppc32: cleanup AMCC PPC40x eval boards to support U-Boot Cleanup PPC40x eval boards (bubinga, walnut and sycamore) to support U-Boot as bootloader. The OpenBIOS bd_info struct is not used in the kernel anymore (only U-Boot now). uImage (U-Boot) tested on walnut, sycamore and bubinga zImage (OpenBIOS) tested on sycamore, bubinga and ebony Signed-off-by: Stefan Roese Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/boot/simple/Makefile | 21 +++++++- arch/ppc/boot/simple/misc.c | 16 ++++-- arch/ppc/boot/simple/openbios.c | 106 +++++++++++++++++++++++++++++++++++--- arch/ppc/platforms/4xx/Kconfig | 2 +- arch/ppc/platforms/4xx/bubinga.c | 2 +- arch/ppc/platforms/4xx/bubinga.h | 64 ++++++++++------------- arch/ppc/platforms/4xx/ebony.h | 4 +- arch/ppc/platforms/4xx/sycamore.c | 7 +-- arch/ppc/platforms/4xx/sycamore.h | 67 ++++++++++-------------- arch/ppc/platforms/4xx/walnut.c | 2 +- arch/ppc/platforms/4xx/walnut.h | 67 +++++++++--------------- include/asm-ppc/ibm_ocp.h | 19 +++++-- include/asm-ppc/ppcboot.h | 6 ++- 13 files changed, 237 insertions(+), 146 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/boot/simple/Makefile b/arch/ppc/boot/simple/Makefile index ff0904ee889..82df88b01bb 100644 --- a/arch/ppc/boot/simple/Makefile +++ b/arch/ppc/boot/simple/Makefile @@ -67,6 +67,12 @@ zimageinitrd-$(CONFIG_BAMBOO) := zImage.initrd-TREE entrypoint-$(CONFIG_BAMBOO) := 0x01000000 extra.o-$(CONFIG_BAMBOO) := pibs.o + zimage-$(CONFIG_BUBINGA) := zImage-TREE +zimageinitrd-$(CONFIG_BUBINGA) := zImage.initrd-TREE + end-$(CONFIG_BUBINGA) := bubinga + entrypoint-$(CONFIG_BUBINGA) := 0x01000000 + extra.o-$(CONFIG_BUBINGA) := openbios.o + zimage-$(CONFIG_EBONY) := zImage-TREE zimageinitrd-$(CONFIG_EBONY) := zImage.initrd-TREE end-$(CONFIG_EBONY) := ebony @@ -91,6 +97,18 @@ zimageinitrd-$(CONFIG_OCOTEA) := zImage.initrd-TREE entrypoint-$(CONFIG_OCOTEA) := 0x01000000 extra.o-$(CONFIG_OCOTEA) := pibs.o + zimage-$(CONFIG_SYCAMORE) := zImage-TREE +zimageinitrd-$(CONFIG_SYCAMORE) := zImage.initrd-TREE + end-$(CONFIG_SYCAMORE) := sycamore + entrypoint-$(CONFIG_SYCAMORE) := 0x01000000 + extra.o-$(CONFIG_SYCAMORE) := openbios.o + + zimage-$(CONFIG_WALNUT) := zImage-TREE +zimageinitrd-$(CONFIG_WALNUT) := zImage.initrd-TREE + end-$(CONFIG_WALNUT) := walnut + entrypoint-$(CONFIG_WALNUT) := 0x01000000 + extra.o-$(CONFIG_WALNUT) := openbios.o + extra.o-$(CONFIG_EV64260) := misc-ev64260.o end-$(CONFIG_EV64260) := ev64260 cacheflag-$(CONFIG_EV64260) := -include $(clear_L2_L3) @@ -168,7 +186,8 @@ OBJCOPY_ARGS := -O elf32-powerpc # head.o and relocate.o must be at the start. boot-y := head.o relocate.o $(extra.o-y) $(misc-y) -boot-$(CONFIG_40x) += embed_config.o +boot-$(CONFIG_REDWOOD_5) += embed_config.o +boot-$(CONFIG_REDWOOD_6) += embed_config.o boot-$(CONFIG_8xx) += embed_config.o boot-$(CONFIG_8260) += embed_config.o boot-$(CONFIG_BSEIP) += iic.o diff --git a/arch/ppc/boot/simple/misc.c b/arch/ppc/boot/simple/misc.c index e02de5b467a..f415d6c6236 100644 --- a/arch/ppc/boot/simple/misc.c +++ b/arch/ppc/boot/simple/misc.c @@ -23,7 +23,7 @@ #include #include #include -#ifdef CONFIG_44x +#ifdef CONFIG_4xx #include #endif #include @@ -88,6 +88,14 @@ get_mem_size(void) return 0; } +#if defined(CONFIG_40x) +#define PPC4xx_EMAC0_MR0 EMAC0_BASE +#endif + +#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0) +#define PPC4xx_EMAC0_MR0 PPC44x_EMAC0_MR0 +#endif + struct bi_record * decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) { @@ -103,13 +111,13 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) com_port = serial_init(0, NULL); #endif -#if defined(CONFIG_44x) && defined(PPC44x_EMAC0_MR0) +#if defined(PPC4xx_EMAC0_MR0) /* Reset MAL */ mtdcr(DCRN_MALCR(DCRN_MAL_BASE), MALCR_MMSR); /* Wait for reset */ while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* Reset EMAC */ - *(volatile unsigned long *)PPC44x_EMAC0_MR0 = 0x20000000; + *(volatile unsigned long *)PPC4xx_EMAC0_MR0 = 0x20000000; __asm__ __volatile__("eieio"); #endif @@ -164,7 +172,9 @@ decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum) puts(" "); puthex((unsigned long)(&__ramdisk_end));puts("\n"); } +#ifndef CONFIG_40x /* don't overwrite the 40x image located at 0x00400000! */ avail_ram = (char *)0x00400000; +#endif end_avail = (char *)0x00800000; puts("avail ram: "); puthex((unsigned long)avail_ram); puts(" "); puthex((unsigned long)end_avail); puts("\n"); diff --git a/arch/ppc/boot/simple/openbios.c b/arch/ppc/boot/simple/openbios.c index c732b6d70cf..81f11d8b30a 100644 --- a/arch/ppc/boot/simple/openbios.c +++ b/arch/ppc/boot/simple/openbios.c @@ -1,19 +1,43 @@ /* * arch/ppc/boot/simple/openbios.c * - * 2005 (c) SYSGO AG - g.jaeger@sysgo.com + * Copyright (c) 2005 DENX Software Engineering + * Stefan Roese + * + * Based on original work by + * 2005 (c) SYSGO AG - g.jaeger@sysgo.com + * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without * any warranty of any kind, whether express or implied. * - * Derived from arch/ppc/boot/simple/pibs.c (from MontaVista) */ #include #include #include #include -#include +#include +#include +#ifdef CONFIG_40x +#include +#endif + +#if defined(CONFIG_BUBINGA) +#define BOARD_INFO_VECTOR 0xFFF80B50 /* openbios 1.19 moved this vector down - armin */ +#else +#define BOARD_INFO_VECTOR 0xFFFE0B50 +#endif + +#ifdef CONFIG_40x +/* Supply a default Ethernet address for those eval boards that don't + * ship with one. This is an address from the MBX board I have, so + * it is unlikely you will find it on your network. + */ +static ushort def_enet_addr[] = { 0x0800, 0x3e26, 0x1559 }; + +extern unsigned long timebase_period_ns; +#endif /* CONFIG_40x */ extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, unsigned long cksum); @@ -23,15 +47,85 @@ extern unsigned long decompress_kernel(unsigned long load_addr, int num_words, bd_t hold_resid_buf __attribute__ ((__section__ (".data.boot"))); bd_t *hold_residual = &hold_resid_buf; +typedef struct openbios_board_info { + unsigned char bi_s_version[4]; /* Version of this structure */ + unsigned char bi_r_version[30]; /* Version of the IBM ROM */ + unsigned int bi_memsize; /* DRAM installed, in bytes */ +#ifdef CONFIG_405EP + unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ +#else /* CONFIG_405EP */ + unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ +#endif /* CONFIG_405EP */ + unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ + unsigned int bi_intfreq; /* Processor speed, in Hz */ + unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ + unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ +#ifdef CONFIG_405EP + unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */ + unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */ +#endif /* CONFIG_405EP */ +} openbios_bd_t; + void * load_kernel(unsigned long load_addr, int num_words, unsigned long cksum, void *ign1, void *ign2) { - decompress_kernel(load_addr, num_words, cksum); +#ifdef CONFIG_40x + openbios_bd_t *openbios_bd = NULL; + openbios_bd_t *(*get_board_info)(void) = + (openbios_bd_t *(*)(void))(*(unsigned long *)BOARD_INFO_VECTOR); + + /* + * On 40x platforms we not only need the MAC-addresses, but also the + * clocks and memsize. Now try to get all values using the OpenBIOS + * "get_board_info()" callback. + */ + if ((openbios_bd = get_board_info()) != NULL) { + /* + * Copy bd_info from OpenBIOS struct into U-Boot struct + * used by kernel + */ + hold_residual->bi_memsize = openbios_bd->bi_memsize; + hold_residual->bi_intfreq = openbios_bd->bi_intfreq; + hold_residual->bi_busfreq = openbios_bd->bi_busfreq; + hold_residual->bi_pci_busfreq = openbios_bd->bi_pci_busfreq; + memcpy(hold_residual->bi_pci_enetaddr, openbios_bd->bi_pci_enetaddr, 6); +#ifdef CONFIG_405EP + memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr[0], 6); + memcpy(hold_residual->bi_enet1addr, openbios_bd->bi_enetaddr[1], 6); + hold_residual->bi_opbfreq = openbios_bd->bi_opb_busfreq; + hold_residual->bi_procfreq = openbios_bd->bi_pllouta_freq; +#else /* CONFIG_405EP */ + memcpy(hold_residual->bi_enetaddr, openbios_bd->bi_enetaddr, 6); +#endif /* CONFIG_405EP */ + } else { + /* Hmmm...better try to stuff some defaults. + */ + hold_residual->bi_memsize = 16 * 1024 * 1024; + hold_residual->bi_intfreq = 200000000; + hold_residual->bi_busfreq = 100000000; + hold_residual->bi_pci_busfreq = 66666666; + + /* + * Only supply one mac-address in this fallback + */ + memcpy(hold_residual->bi_enetaddr, (void *)def_enet_addr, 6); +#ifdef CONFIG_405EP + hold_residual->bi_opbfreq = 50000000; + hold_residual->bi_procfreq = 200000000; +#endif /* CONFIG_405EP */ + } + timebase_period_ns = 1000000000 / hold_residual->bi_intfreq; +#endif /* CONFIG_40x */ + +#ifdef CONFIG_440GP /* simply copy the MAC addresses */ - memcpy(hold_residual->bi_enetaddr, (char *)EBONY_OPENBIOS_MAC_BASE, 6); - memcpy(hold_residual->bi_enet1addr, (char *)(EBONY_OPENBIOS_MAC_BASE+EBONY_OPENBIOS_MAC_OFFSET), 6); + memcpy(hold_residual->bi_enetaddr, (char *)OPENBIOS_MAC_BASE, 6); + memcpy(hold_residual->bi_enet1addr, (char *)(OPENBIOS_MAC_BASE+OPENBIOS_MAC_OFFSET), 6); +#endif /* CONFIG_440GP */ + + decompress_kernel(load_addr, num_words, cksum); return (void *)hold_residual; } diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig index e70e4c6ec78..d8837911bbc 100644 --- a/arch/ppc/platforms/4xx/Kconfig +++ b/arch/ppc/platforms/4xx/Kconfig @@ -225,7 +225,7 @@ config EMBEDDEDBOOT config IBM_OPENBIOS bool - depends on ASH || BUBINGA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT + depends on ASH || REDWOOD_5 || REDWOOD_6 default y config PPC4xx_DMA diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c index 3678abf8631..8110f55668c 100644 --- a/arch/ppc/platforms/4xx/bubinga.c +++ b/arch/ppc/platforms/4xx/bubinga.c @@ -89,7 +89,7 @@ bubinga_early_serial_map(void) * by 16. */ uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV); - uart_clock = __res.bi_pllouta_freq / uart_div; + uart_clock = __res.bi_procfreq / uart_div; /* Setup serial port access */ memset(&port, 0, sizeof(port)); diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h index b1df856f8e2..b5380cfaf5c 100644 --- a/arch/ppc/platforms/4xx/bubinga.h +++ b/arch/ppc/platforms/4xx/bubinga.h @@ -1,52 +1,34 @@ /* - * Support for IBM PPC 405EP evaluation board (Bubinga). + * arch/ppc/platforms/4xx/bubinga.h * - * Author: SAW (IBM), derived from walnut.h. - * Maintained by MontaVista Software + * Bubinga board definitions + * + * Copyright (c) 2005 DENX Software Engineering + * Stefan Roese + * + * Based on original work by + * SAW (IBM) + * 2003 (c) MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. * - * 2003 (c) MontaVista Softare Inc. This file is licensed under the - * terms of the GNU General Public License version 2. This program is - * licensed "as is" without any warranty of any kind, whether express - * or implied. */ #ifdef __KERNEL__ #ifndef __BUBINGA_H__ #define __BUBINGA_H__ -/* 405EP */ +#include #include - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[2][6]; /* Local Ethernet MAC address */ unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ - unsigned int bi_opb_busfreq; /* OPB Bus speed, in Hz */ - unsigned int bi_pllouta_freq; /* PLL OUTA speed, in Hz */ -} bd_t; - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - +#include /* Memory map for the Bubinga board. * Generic 4xx plus RTC. */ -extern void *bubinga_rtc_base; #define BUBINGA_RTC_PADDR ((uint)0xf0000000) #define BUBINGA_RTC_VADDR BUBINGA_RTC_PADDR #define BUBINGA_RTC_SIZE ((uint)8*1024) @@ -58,12 +40,18 @@ extern void *bubinga_rtc_base; * for typical configurations at various CPU speeds. * The base baud is calculated as (FWDA / EXT UART DIV / 16) */ -#define BASE_BAUD 0 +#define BASE_BAUD 0 -#define BUBINGA_FPGA_BASE 0xF0300000 +/* Flash */ +#define PPC40x_FPGA_BASE 0xF0300000 +#define PPC40x_FPGA_REG_OFFS 1 /* offset to flash map reg */ +#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) +#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) +#define PPC40x_FLASH_LOW 0xFFF00000 +#define PPC40x_FLASH_HIGH 0xFFF80000 +#define PPC40x_FLASH_SIZE 0x80000 -#define PPC4xx_MACHINE_NAME "IBM Bubinga" +#define PPC4xx_MACHINE_NAME "IBM Bubinga" -#endif /* !__ASSEMBLY__ */ #endif /* __BUBINGA_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h index d08faa46a0a..b91ad4272df 100644 --- a/arch/ppc/platforms/4xx/ebony.h +++ b/arch/ppc/platforms/4xx/ebony.h @@ -24,8 +24,8 @@ #define PPC44x_EMAC0_MR0 0xE0000800 /* Where to find the MAC info */ -#define EBONY_OPENBIOS_MAC_BASE 0xfffffe0c -#define EBONY_OPENBIOS_MAC_OFFSET 0x0c +#define OPENBIOS_MAC_BASE 0xfffffe0c +#define OPENBIOS_MAC_OFFSET 0x0c /* Default clock rates for Rev. B and Rev. C silicon */ #define EBONY_440GP_RB_SYSCLK 33000000 diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c index d8019eec470..281b4a2ffb9 100644 --- a/arch/ppc/platforms/4xx/sycamore.c +++ b/arch/ppc/platforms/4xx/sycamore.c @@ -88,9 +88,6 @@ ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin) void __init sycamore_setup_arch(void) { -#define SYCAMORE_PS2_BASE 0xF0100000 -#define SYCAMORE_FPGA_BASE 0xF0300000 - void *fpga_brdc; unsigned char fpga_brdc_data; void *fpga_enable; @@ -100,7 +97,7 @@ sycamore_setup_arch(void) ppc4xx_setup_arch(); - ibm_ocp_set_emac(0, 1); + ibm_ocp_set_emac(0, 0); kb_data = ioremap(SYCAMORE_PS2_BASE, 8); if (!kb_data) { @@ -111,7 +108,7 @@ sycamore_setup_arch(void) kb_cs = kb_data + 1; - fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8); + fpga_status = ioremap(PPC40x_FPGA_BASE, 8); if (!fpga_status) { printk(KERN_CRIT "sycamore_setup_arch() fpga_status ioremap failed\n"); diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h index 3e7b4e2c8c5..1cd6c824fd6 100644 --- a/arch/ppc/platforms/4xx/sycamore.h +++ b/arch/ppc/platforms/4xx/sycamore.h @@ -1,67 +1,52 @@ /* * arch/ppc/platforms/4xx/sycamore.h * - * Macros, definitions, and data structures specific to the IBM PowerPC - * 405GPr "Sycamore" evaluation board. + * Sycamore board definitions * - * Author: Armin Kuster + * Copyright (c) 2005 DENX Software Engineering + * Stefan Roese + * + * Based on original work by + * Armin Kuster + * 2000 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. * - * 2000 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. */ #ifdef __KERNEL__ #ifndef __ASM_SYCAMORE_H__ #define __ASM_SYCAMORE_H__ +#include #include +#include -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Sycamore" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ -} bd_t; - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - - -/* Memory map for the IBM "Sycamore" 405GP evaluation board. +/* Memory map for the IBM "Sycamore" 405GPr evaluation board. * Generic 4xx plus RTC. */ -extern void *sycamore_rtc_base; #define SYCAMORE_RTC_PADDR ((uint)0xf0000000) #define SYCAMORE_RTC_VADDR SYCAMORE_RTC_PADDR -#define SYCAMORE_RTC_SIZE ((uint)8*1024) +#define SYCAMORE_RTC_SIZE ((uint)8*1024) -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else #define BASE_BAUD 691200 -#endif -#define SYCAMORE_PS2_BASE 0xF0100000 -#define SYCAMORE_FPGA_BASE 0xF0300000 +#define SYCAMORE_PS2_BASE 0xF0100000 + +/* Flash */ +#define PPC40x_FPGA_BASE 0xF0300000 +#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */ +#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) +#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) +#define PPC40x_FLASH_LOW 0xFFF00000 +#define PPC40x_FLASH_HIGH 0xFFF80000 +#define PPC40x_FLASH_SIZE 0x80000 #define PPC4xx_MACHINE_NAME "IBM Sycamore" -#endif /* !__ASSEMBLY__ */ #endif /* __ASM_SYCAMORE_H__ */ #endif /* __KERNEL__ */ diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c index a33eda4b748..74cb33182d9 100644 --- a/arch/ppc/platforms/4xx/walnut.c +++ b/arch/ppc/platforms/4xx/walnut.c @@ -90,7 +90,7 @@ walnut_setup_arch(void) kb_cs = kb_data + 1; - fpga_status = ioremap(WALNUT_FPGA_BASE, 8); + fpga_status = ioremap(PPC40x_FPGA_BASE, 8); if (!fpga_status) { printk(KERN_CRIT "walnut_setup_arch() fpga_status ioremap failed\n"); diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h index 04cfbf3696b..dcf2691698c 100644 --- a/arch/ppc/platforms/4xx/walnut.h +++ b/arch/ppc/platforms/4xx/walnut.h @@ -1,72 +1,55 @@ /* * arch/ppc/platforms/4xx/walnut.h * - * Macros, definitions, and data structures specific to the IBM PowerPC - * 405GP "Walnut" evaluation board. + * Walnut board definitions * - * Authors: Grant Erickson , Frank Rowand - * , Debbie Chu or - * source@mvista.com + * Copyright (c) 2005 DENX Software Engineering + * Stefan Roese * - * Copyright (c) 1999 Grant Erickson + * Based on original work by + * Copyright (c) 1999 Grant Erickson + * Frank Rowand + * Debbie Chu + * 2000 (c) MontaVista, Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. * - * 2000 (c) MontaVista, Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. */ #ifdef __KERNEL__ #ifndef __ASM_WALNUT_H__ #define __ASM_WALNUT_H__ -/* We have a 405GP core */ +#include #include - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Walnut" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ -} bd_t; - -/* Some 4xx parts use a different timebase frequency from the internal clock. -*/ -#define bi_tbfreq bi_intfreq - +#include /* Memory map for the IBM "Walnut" 405GP evaluation board. * Generic 4xx plus RTC. */ -extern void *walnut_rtc_base; #define WALNUT_RTC_PADDR ((uint)0xf0000000) #define WALNUT_RTC_VADDR WALNUT_RTC_PADDR #define WALNUT_RTC_SIZE ((uint)8*1024) -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else #define BASE_BAUD 691200 -#endif #define WALNUT_PS2_BASE 0xF0100000 -#define WALNUT_FPGA_BASE 0xF0300000 + +/* Flash */ +#define PPC40x_FPGA_BASE 0xF0300000 +#define PPC40x_FPGA_REG_OFFS 5 /* offset to flash map reg */ +#define PPC40x_FLASH_ONBD_N(x) (x & 0x02) +#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01) +#define PPC40x_FLASH_LOW 0xFFF00000 +#define PPC40x_FLASH_HIGH 0xFFF80000 +#define PPC40x_FLASH_SIZE 0x80000 +#define WALNUT_FPGA_BASE PPC40x_FPGA_BASE #define PPC4xx_MACHINE_NAME "IBM Walnut" -#endif /* !__ASSEMBLY__ */ #endif /* __ASM_WALNUT_H__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h index 6f10a25bd62..9c21de1ff4e 100644 --- a/include/asm-ppc/ibm_ocp.h +++ b/include/asm-ppc/ibm_ocp.h @@ -131,9 +131,22 @@ static inline void ibm_ocp_set_emac(int start, int end) /* Copy MAC addresses to EMAC additions */ for (i=start; i<=end; i++) { def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i); - memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, - &__res.bi_enetaddr[i], - 6); + if (i == 0) + memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, + __res.bi_enetaddr, 6); +#if defined(CONFIG_405EP) || defined(CONFIG_44x) + else if (i == 1) + memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, + __res.bi_enet1addr, 6); +#endif +#if defined(CONFIG_440GX) + else if (i == 2) + memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, + __res.bi_enet2addr, 6); + else if (i == 3) + memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr, + __res.bi_enet3addr, 6); +#endif } } #endif diff --git a/include/asm-ppc/ppcboot.h b/include/asm-ppc/ppcboot.h index fe24e452020..6b7b63f71da 100644 --- a/include/asm-ppc/ppcboot.h +++ b/include/asm-ppc/ppcboot.h @@ -73,8 +73,8 @@ typedef struct bd_info { #if defined(CONFIG_HYMOD) hymod_conf_t bi_hymod_conf; /* hymod configuration information */ #endif -#if defined(CONFIG_EVB64260) || defined(CONFIG_44x) || defined(CONFIG_85xx) ||\ - defined(CONFIG_83xx) +#if defined(CONFIG_EVB64260) || defined(CONFIG_405EP) || defined(CONFIG_44x) || \ + defined(CONFIG_85xx) || defined(CONFIG_83xx) /* second onboard ethernet port */ unsigned char bi_enet1addr[6]; #endif @@ -96,5 +96,7 @@ typedef struct bd_info { #endif } bd_t; +#define bi_tbfreq bi_intfreq + #endif /* __ASSEMBLY__ */ #endif /* __ASM_PPCBOOT_H__ */ -- cgit v1.2.3 From 7869ec6d735e3802f0d442f585ae6bb7633222f6 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 7 Nov 2005 00:58:16 -0800 Subject: [PATCH] ppc32: Remove internal PCI arbiter check on PPC40x On PPC405GP/GPR it should be possible to enable PCI support, even when the internal PCI arbiter is disabled (e.g. when using an external PCI arbiter). The removed code didn't allow this, and also generated a warning on PPC405EP platforms. Signed-off-by: Stefan Roese Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/syslib/ppc405_pci.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/ppc405_pci.c b/arch/ppc/syslib/ppc405_pci.c index 81c83bf98df..d6d838b16da 100644 --- a/arch/ppc/syslib/ppc405_pci.c +++ b/arch/ppc/syslib/ppc405_pci.c @@ -89,13 +89,6 @@ ppc4xx_find_bridges(void) isa_mem_base = 0; pci_dram_offset = 0; -#if (PSR_PCI_ARBIT_EN > 1) - /* Check if running in slave mode */ - if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) { - printk("Running as PCI slave, kernel PCI disabled !\n"); - return; - } -#endif /* Setup PCI32 hose */ hose_a = pcibios_alloc_controller(); if (!hose_a) -- cgit v1.2.3 From 634e67ff917c079b102317d53556d758dc207969 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 7 Nov 2005 00:58:16 -0800 Subject: [PATCH] ppc32: Add missing initrd header on ppc440 This missing initrd header slipped though last time. Signed-off-by: Stefan Roese Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/syslib/ibm44x_common.c | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/ibm44x_common.c b/arch/ppc/syslib/ibm44x_common.c index a5bef9d163a..71db11d2215 100644 --- a/arch/ppc/syslib/ibm44x_common.c +++ b/arch/ppc/syslib/ibm44x_common.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From de672e4ade25502c28486da005be3eb79534017d Mon Sep 17 00:00:00 2001 From: Pantelis Antoniou Date: Mon, 7 Nov 2005 00:58:17 -0800 Subject: [PATCH] ppc32: Add CPM1 config option Kconfig patch needed by fs_enet to work. Works like CONFIG_CPM2. Cc: Kumar Cc: Benjamin Herrenschmidt Cc: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 114b90fdea2..f8db33d5527 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -746,6 +746,16 @@ config MPC834x bool default y if MPC834x_SYS +config CPM1 + bool + depends on 8xx + default y + help + The CPM1 (Communications Processor Module) is a coprocessor on + embedded CPUs made by Motorola. Selecting this option means that + you wish to build a kernel for a machine with a CPM1 coprocessor + on it (8xx, 827x, 8560). + config CPM2 bool depends on 8260 || MPC8560 || MPC8555 -- cgit v1.2.3 From 8c65b4a60450590e79a28e9717ceffa9e4debb3f Mon Sep 17 00:00:00 2001 From: Tim Schmielau Date: Mon, 7 Nov 2005 00:59:43 -0800 Subject: [PATCH] fix remaining missing includes Fix more include file problems that surfaced since I submitted the previous fix-missing-includes.patch. This should now allow not to include sched.h from module.h, which is done by a followup patch. Signed-off-by: Tim Schmielau Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mach-aaec2000/clock.c | 1 + arch/arm/mach-epxa10db/mm.c | 1 + arch/arm/mach-pxa/corgi_lcd.c | 1 + arch/ppc/syslib/ppc_sys.c | 1 + drivers/base/power/sysfs.c | 1 + drivers/char/agp/amd64-agp.c | 1 + drivers/hwmon/hwmon.c | 1 + drivers/infiniband/core/agent.c | 3 +++ drivers/infiniband/core/packer.c | 2 ++ drivers/infiniband/core/sysfs.c | 3 +++ drivers/infiniband/core/ud_header.c | 1 + drivers/infiniband/core/verbs.c | 1 + drivers/infiniband/hw/mthca/mthca_catas.c | 3 +++ drivers/infiniband/hw/mthca/mthca_srq.c | 3 +++ drivers/media/dvb/frontends/cx24110.c | 1 + drivers/message/i2o/exec-osm.c | 1 + drivers/mfd/mcp-core.c | 2 ++ drivers/pci/hotplug/pciehprm_nonacpi.c | 1 + drivers/pci/pci-driver.c | 1 + drivers/scsi/atari_dma_emul.c | 2 ++ drivers/scsi/raid_class.c | 2 ++ drivers/scsi/scsi_transport_sas.c | 2 ++ drivers/scsi/sym53c8xx_2/sym_hipd.c | 1 + fs/9p/error.c | 1 + include/asm-alpha/pgtable.h | 3 +++ include/asm-cris/processor.h | 2 ++ include/asm-frv/pgtable.h | 2 ++ include/asm-generic/pgtable.h | 1 + include/asm-i386/elf.h | 2 ++ include/asm-i386/pgtable.h | 3 +++ include/asm-ia64/pgtable.h | 1 + include/asm-m32r/pgtable.h | 3 +++ include/asm-mips/elf.h | 2 ++ include/asm-mips/pgtable.h | 3 +++ include/asm-parisc/pgtable.h | 3 ++- include/asm-powerpc/elf.h | 2 ++ include/asm-ppc/pgtable.h | 1 + include/asm-ppc64/pgtable.h | 1 + include/asm-s390/elf.h | 1 + include/asm-s390/pgtable.h | 1 + include/asm-sh/elf.h | 1 + include/asm-sh/pgtable.h | 2 ++ include/asm-sh64/pgtable.h | 2 ++ include/asm-x86_64/elf.h | 2 ++ include/asm-x86_64/pgtable.h | 2 ++ include/asm-xtensa/elf.h | 2 ++ include/asm-xtensa/pgtable.h | 3 +++ include/linux/irq.h | 1 + include/linux/memory.h | 3 +++ include/linux/sem.h | 2 ++ include/linux/wait.h | 1 + kernel/module.c | 1 + 52 files changed, 89 insertions(+), 1 deletion(-) (limited to 'arch/ppc') diff --git a/arch/arm/mach-aaec2000/clock.c b/arch/arm/mach-aaec2000/clock.c index 99e019169dd..0340ddc4824 100644 --- a/arch/arm/mach-aaec2000/clock.c +++ b/arch/arm/mach-aaec2000/clock.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include diff --git a/arch/arm/mach-epxa10db/mm.c b/arch/arm/mach-epxa10db/mm.c index e8832d0910e..cfd0d2182d4 100644 --- a/arch/arm/mach-epxa10db/mm.c +++ b/arch/arm/mach-epxa10db/mm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index 54162ba9541..698eb06545c 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/ppc/syslib/ppc_sys.c b/arch/ppc/syslib/ppc_sys.c index 62ee86e8071..603f0119081 100644 --- a/arch/ppc/syslib/ppc_sys.c +++ b/arch/ppc/syslib/ppc_sys.c @@ -14,6 +14,7 @@ * option) any later version. */ +#include #include int (*ppc_sys_device_fixup) (struct platform_device * pdev); diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c index 89c57875f3e..f3a0c562bcb 100644 --- a/drivers/base/power/sysfs.c +++ b/drivers/base/power/sysfs.c @@ -3,6 +3,7 @@ */ #include +#include #include "power.h" diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c index 0e6c3a31d34..78ce98a69f3 100644 --- a/drivers/char/agp/amd64-agp.c +++ b/drivers/char/agp/amd64-agp.c @@ -13,6 +13,7 @@ #include #include #include +#include #include /* PAGE_SIZE */ #include "agp.h" diff --git a/drivers/hwmon/hwmon.c b/drivers/hwmon/hwmon.c index 6f48579799b..dddd3eb9b38 100644 --- a/drivers/hwmon/hwmon.c +++ b/drivers/hwmon/hwmon.c @@ -16,6 +16,7 @@ #include #include #include +#include #define HWMON_ID_PREFIX "hwmon" #define HWMON_ID_FORMAT HWMON_ID_PREFIX "%d" diff --git a/drivers/infiniband/core/agent.c b/drivers/infiniband/core/agent.c index 7545775d38e..34b724afd28 100644 --- a/drivers/infiniband/core/agent.c +++ b/drivers/infiniband/core/agent.c @@ -37,6 +37,9 @@ * $Id: agent.c 1389 2004-12-27 22:56:47Z roland $ */ +#include +#include + #include "agent.h" #include "smi.h" diff --git a/drivers/infiniband/core/packer.c b/drivers/infiniband/core/packer.c index 35df5010e72..c972d723576 100644 --- a/drivers/infiniband/core/packer.c +++ b/drivers/infiniband/core/packer.c @@ -33,6 +33,8 @@ * $Id: packer.c 1349 2004-12-16 21:09:43Z roland $ */ +#include + #include static u64 value_read(int offset, int size, void *structure) diff --git a/drivers/infiniband/core/sysfs.c b/drivers/infiniband/core/sysfs.c index b8120650e71..08648b1a387 100644 --- a/drivers/infiniband/core/sysfs.c +++ b/drivers/infiniband/core/sysfs.c @@ -36,6 +36,9 @@ #include "core_priv.h" +#include +#include + #include struct ib_port { diff --git a/drivers/infiniband/core/ud_header.c b/drivers/infiniband/core/ud_header.c index 527b23450ab..997c07db6d8 100644 --- a/drivers/infiniband/core/ud_header.c +++ b/drivers/infiniband/core/ud_header.c @@ -34,6 +34,7 @@ */ #include +#include #include diff --git a/drivers/infiniband/core/verbs.c b/drivers/infiniband/core/verbs.c index 72d3ef786db..4186cc888ea 100644 --- a/drivers/infiniband/core/verbs.c +++ b/drivers/infiniband/core/verbs.c @@ -40,6 +40,7 @@ #include #include +#include #include #include diff --git a/drivers/infiniband/hw/mthca/mthca_catas.c b/drivers/infiniband/hw/mthca/mthca_catas.c index 7ac52af43b9..25ebab64bc4 100644 --- a/drivers/infiniband/hw/mthca/mthca_catas.c +++ b/drivers/infiniband/hw/mthca/mthca_catas.c @@ -32,6 +32,9 @@ * $Id$ */ +#include +#include + #include "mthca_dev.h" enum { diff --git a/drivers/infiniband/hw/mthca/mthca_srq.c b/drivers/infiniband/hw/mthca/mthca_srq.c index 292f55be8cb..26d5161fde0 100644 --- a/drivers/infiniband/hw/mthca/mthca_srq.c +++ b/drivers/infiniband/hw/mthca/mthca_srq.c @@ -32,6 +32,9 @@ * $Id: mthca_srq.c 3047 2005-08-10 03:59:35Z roland $ */ +#include +#include + #include "mthca_dev.h" #include "mthca_cmd.h" #include "mthca_memfree.h" diff --git a/drivers/media/dvb/frontends/cx24110.c b/drivers/media/dvb/frontends/cx24110.c index d4b97989e3e..654d7dc879d 100644 --- a/drivers/media/dvb/frontends/cx24110.c +++ b/drivers/media/dvb/frontends/cx24110.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "dvb_frontend.h" #include "cx24110.h" diff --git a/drivers/message/i2o/exec-osm.c b/drivers/message/i2o/exec-osm.c index b675b4ebbeb..9c339a2505b 100644 --- a/drivers/message/i2o/exec-osm.c +++ b/drivers/message/i2o/exec-osm.c @@ -33,6 +33,7 @@ #include #include #include +#include /* wait_event_interruptible_timeout() needs this */ #include /* HZ */ #include "core.h" diff --git a/drivers/mfd/mcp-core.c b/drivers/mfd/mcp-core.c index c75d713c01e..55ba23075c9 100644 --- a/drivers/mfd/mcp-core.c +++ b/drivers/mfd/mcp-core.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include #include diff --git a/drivers/pci/hotplug/pciehprm_nonacpi.c b/drivers/pci/hotplug/pciehprm_nonacpi.c index 33b2c69a082..76c727c74cc 100644 --- a/drivers/pci/hotplug/pciehprm_nonacpi.c +++ b/drivers/pci/hotplug/pciehprm_nonacpi.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c index ae986e590b4..94e68c54d27 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -10,6 +10,7 @@ #include #include #include +#include #include "pci.h" /* diff --git a/drivers/scsi/atari_dma_emul.c b/drivers/scsi/atari_dma_emul.c index 7026045527f..8d5d2a5da96 100644 --- a/drivers/scsi/atari_dma_emul.c +++ b/drivers/scsi/atari_dma_emul.c @@ -19,6 +19,8 @@ * this code. */ +#include +#include #include #define hades_dma_ctrl (*(unsigned char *) 0xffff8717) diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index f1ea5027865..caa0c362962 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -4,6 +4,8 @@ #include #include #include +#include +#include #include #include #include diff --git a/drivers/scsi/scsi_transport_sas.c b/drivers/scsi/scsi_transport_sas.c index 0cc766a9aa6..edabbd05d25 100644 --- a/drivers/scsi/scsi_transport_sas.c +++ b/drivers/scsi/scsi_transport_sas.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include #include diff --git a/drivers/scsi/sym53c8xx_2/sym_hipd.c b/drivers/scsi/sym53c8xx_2/sym_hipd.c index a1a58e1d5ad..a7420cad454 100644 --- a/drivers/scsi/sym53c8xx_2/sym_hipd.c +++ b/drivers/scsi/sym53c8xx_2/sym_hipd.c @@ -39,6 +39,7 @@ */ #include +#include /* for timeouts in units of HZ */ #include "sym_glue.h" #include "sym_nvram.h" diff --git a/fs/9p/error.c b/fs/9p/error.c index fee5d19179c..834cb179e38 100644 --- a/fs/9p/error.c +++ b/fs/9p/error.c @@ -33,6 +33,7 @@ #include #include +#include #include "debug.h" #include "error.h" diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h index 8393bf374b2..a985cd29b6d 100644 --- a/include/asm-alpha/pgtable.h +++ b/include/asm-alpha/pgtable.h @@ -17,6 +17,9 @@ #include /* For TASK_SIZE */ #include +struct mm_struct; +struct vm_area_struct; + /* Certain architectures need to do special things when PTEs * within a page table are directly modified. Thus, the following * hook is made available. diff --git a/include/asm-cris/processor.h b/include/asm-cris/processor.h index e8b2abb2ae5..dce41009eeb 100644 --- a/include/asm-cris/processor.h +++ b/include/asm-cris/processor.h @@ -16,6 +16,8 @@ #include #include +struct task_struct; + /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h index b247e99dff4..844666377dc 100644 --- a/include/asm-frv/pgtable.h +++ b/include/asm-frv/pgtable.h @@ -26,6 +26,8 @@ #include #include #include +struct mm_struct; +struct vm_area_struct; #endif #ifndef __ASSEMBLY__ diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h index 7dca30a26c5..358e4d309ce 100644 --- a/include/asm-generic/pgtable.h +++ b/include/asm-generic/pgtable.h @@ -128,6 +128,7 @@ do { \ #endif #ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT +struct mm_struct; static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) { pte_t old_pte = *ptep; diff --git a/include/asm-i386/elf.h b/include/asm-i386/elf.h index fa11117d3cf..4153d80e4d2 100644 --- a/include/asm-i386/elf.h +++ b/include/asm-i386/elf.h @@ -119,6 +119,8 @@ typedef struct user_fxsr_struct elf_fpxregset_t; */ #define elf_read_implies_exec(ex, executable_stack) (executable_stack != EXSTACK_DISABLE_X) +struct task_struct; + extern int dump_task_regs (struct task_struct *, elf_gregset_t *); extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); extern int dump_task_extended_fpu (struct task_struct *, struct user_fxsr_struct *); diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h index 03f3c8ac638..088a945bf26 100644 --- a/include/asm-i386/pgtable.h +++ b/include/asm-i386/pgtable.h @@ -25,6 +25,9 @@ #include #include +struct mm_struct; +struct vm_area_struct; + /* * ZERO_PAGE is a global shared page that is always zero: used * for zero-mapped memory areas etc.. diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h index 21e32a06bc8..c34ba80c1c3 100644 --- a/include/asm-ia64/pgtable.h +++ b/include/asm-ia64/pgtable.h @@ -127,6 +127,7 @@ # ifndef __ASSEMBLY__ +#include /* for mm_struct */ #include #include #include diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h index 1cd5fd4a5b2..75740debcd0 100644 --- a/include/asm-m32r/pgtable.h +++ b/include/asm-m32r/pgtable.h @@ -27,6 +27,9 @@ #include #include +struct mm_struct; +struct vm_area_struct; + extern pgd_t swapper_pg_dir[1024]; extern void paging_init(void); diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h index 7420f12742b..d2c9a25f845 100644 --- a/include/asm-mips/elf.h +++ b/include/asm-mips/elf.h @@ -275,6 +275,8 @@ do { \ #endif /* CONFIG_64BIT */ +struct task_struct; + extern void dump_regs(elf_greg_t *, struct pt_regs *regs); extern int dump_task_regs (struct task_struct *, elf_gregset_t *); extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h index 34facd99650..702a28fa7a3 100644 --- a/include/asm-mips/pgtable.h +++ b/include/asm-mips/pgtable.h @@ -19,6 +19,9 @@ #include #include +struct mm_struct; +struct vm_area_struct; + #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ PAGE_CACHABLE_DEFAULT) diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h index c28fb6f48c6..b4554711c3e 100644 --- a/include/asm-parisc/pgtable.h +++ b/include/asm-parisc/pgtable.h @@ -12,6 +12,7 @@ */ #include +#include /* for vm_area_struct */ #include #include #include @@ -418,7 +419,6 @@ extern void paging_init (void); #define PG_dcache_dirty PG_arch_1 -struct vm_area_struct; /* forward declaration (include/linux/mm.h) */ extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t); /* Encode and de-code a swap entry */ @@ -464,6 +464,7 @@ static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma, unsigned extern spinlock_t pa_dbit_lock; +struct mm_struct; static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { pte_t old_pte; diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h index d140577d0a0..feac3458d71 100644 --- a/include/asm-powerpc/elf.h +++ b/include/asm-powerpc/elf.h @@ -1,11 +1,13 @@ #ifndef _ASM_POWERPC_ELF_H #define _ASM_POWERPC_ELF_H +#include /* for task_struct */ #include #include #include #include #include +#include /* PowerPC relocations defined by the ABIs */ #define R_PPC_NONE 0 diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index b28a713ba86..6d1c39e8a6a 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -12,6 +12,7 @@ #include /* For TASK_SIZE */ #include #include +struct mm_struct; extern unsigned long va_to_phys(unsigned long address); extern pte_t *va_to_pte(unsigned long address); diff --git a/include/asm-ppc64/pgtable.h b/include/asm-ppc64/pgtable.h index fde93ec36ab..a9783ba7fe9 100644 --- a/include/asm-ppc64/pgtable.h +++ b/include/asm-ppc64/pgtable.h @@ -13,6 +13,7 @@ #include #include #include +struct mm_struct; #endif /* __ASSEMBLY__ */ #ifdef CONFIG_PPC_64K_PAGES diff --git a/include/asm-s390/elf.h b/include/asm-s390/elf.h index 3b8bd46832a..372d51cccd5 100644 --- a/include/asm-s390/elf.h +++ b/include/asm-s390/elf.h @@ -96,6 +96,7 @@ * ELF register definitions.. */ +#include /* for task_struct */ #include #include #include /* for save_access_regs */ diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h index df94f89038c..9be741bb149 100644 --- a/include/asm-s390/pgtable.h +++ b/include/asm-s390/pgtable.h @@ -36,6 +36,7 @@ #include struct vm_area_struct; /* forward declaration (include/linux/mm.h) */ +struct mm_struct; extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096))); extern void paging_init(void); diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h index 8fe00a1981c..1b63dfeea4f 100644 --- a/include/asm-sh/elf.h +++ b/include/asm-sh/elf.h @@ -111,6 +111,7 @@ typedef struct user_fpu_struct elf_fpregset_t; #ifdef __KERNEL__ #define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) +struct task_struct; extern int dump_task_regs (struct task_struct *, elf_gregset_t *); extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h index dee36bcbcf9..bb0efb31a8c 100644 --- a/include/asm-sh/pgtable.h +++ b/include/asm-sh/pgtable.h @@ -284,6 +284,8 @@ typedef pte_t *pte_addr_t; #define GET_IOSPACE(pfn) 0 #define GET_PFN(pfn) (pfn) +struct mm_struct; + /* * No page table caches to initialise */ diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h index 51b05818e4e..a1906a772df 100644 --- a/include/asm-sh64/pgtable.h +++ b/include/asm-sh64/pgtable.h @@ -24,6 +24,8 @@ #include #include +struct vm_area_struct; + extern void paging_init(void); /* We provide our own get_unmapped_area to avoid cache synonym issue */ diff --git a/include/asm-x86_64/elf.h b/include/asm-x86_64/elf.h index a60a35e7922..43862cd6a56 100644 --- a/include/asm-x86_64/elf.h +++ b/include/asm-x86_64/elf.h @@ -149,6 +149,8 @@ extern void set_personality_64bit(void); */ #define elf_read_implies_exec(ex, executable_stack) (executable_stack != EXSTACK_DISABLE_X) +struct task_struct; + extern int dump_task_regs (struct task_struct *, elf_gregset_t *); extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h index 7a07196a720..7309fffeec9 100644 --- a/include/asm-x86_64/pgtable.h +++ b/include/asm-x86_64/pgtable.h @@ -105,6 +105,8 @@ static inline void pgd_clear (pgd_t * pgd) #define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte, 0)) +struct mm_struct; + static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full) { pte_t pte; diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h index 64f1f53874f..de0667453b2 100644 --- a/include/asm-xtensa/elf.h +++ b/include/asm-xtensa/elf.h @@ -209,6 +209,8 @@ extern void xtensa_elf_core_copy_regs (xtensa_gregset_t *, struct pt_regs *); #define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) +struct task_struct; + extern void do_copy_regs (xtensa_gregset_t*, struct pt_regs*, struct task_struct*); extern void do_restore_regs (xtensa_gregset_t*, struct pt_regs*, diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h index 987e3b80231..7b15afb70c5 100644 --- a/include/asm-xtensa/pgtable.h +++ b/include/asm-xtensa/pgtable.h @@ -278,6 +278,8 @@ static inline void update_pte(pte_t *ptep, pte_t pteval) #endif } +struct mm_struct; + static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) { @@ -294,6 +296,7 @@ set_pmd(pmd_t *pmdp, pmd_t pmdval) #endif } +struct vm_area_struct; static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, diff --git a/include/linux/irq.h b/include/linux/irq.h index 69681c3b1f0..c516382fbec 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -10,6 +10,7 @@ */ #include +#include /* cpu_online_map */ #if !defined(CONFIG_ARCH_S390) diff --git a/include/linux/memory.h b/include/linux/memory.h index 0def328ab5c..9a424383e6c 100644 --- a/include/linux/memory.h +++ b/include/linux/memory.h @@ -54,6 +54,9 @@ struct memory_block { */ #define MEM_MAPPING_INVALID (1<<3) +struct notifier_block; +struct mem_section; + #ifndef CONFIG_MEMORY_HOTPLUG static inline int memory_dev_init(void) { diff --git a/include/linux/sem.h b/include/linux/sem.h index 106f9757339..3c1f1120fe8 100644 --- a/include/linux/sem.h +++ b/include/linux/sem.h @@ -79,6 +79,8 @@ struct seminfo { #ifdef __KERNEL__ +struct task_struct; + /* One semaphore structure for each semaphore in the system. */ struct sem { int semval; /* current value */ diff --git a/include/linux/wait.h b/include/linux/wait.h index d38c9fecdc3..d28518236b6 100644 --- a/include/linux/wait.h +++ b/include/linux/wait.h @@ -54,6 +54,7 @@ struct __wait_queue_head { }; typedef struct __wait_queue_head wait_queue_head_t; +struct task_struct; /* * Macros for declaration and initialisaton of the datatypes diff --git a/kernel/module.c b/kernel/module.c index ff5c500ab62..2ea929d51ad 100644 --- a/kernel/module.c +++ b/kernel/module.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include #include -- cgit v1.2.3 From 2b0c28d7f8846f80a436093e906f5175d1fa8f55 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 7 Nov 2005 01:00:19 -0800 Subject: [PATCH] RapidIO support: ppc32 Adds PPC32 RIO support. Init code for the MPC85xx RIO ports and glue for the STx GP3 board to use it. Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/Kconfig | 8 + arch/ppc/configs/stx_gp3_defconfig | 86 ++- arch/ppc/kernel/Makefile | 1 + arch/ppc/kernel/rio.c | 52 ++ arch/ppc/platforms/85xx/mpc85xx_ads_common.c | 10 + arch/ppc/platforms/85xx/stx_gp3.c | 14 + arch/ppc/syslib/Makefile | 1 + arch/ppc/syslib/ppc85xx_rio.c | 932 +++++++++++++++++++++++++++ arch/ppc/syslib/ppc85xx_rio.h | 21 + include/asm-ppc/rio.h | 18 + 10 files changed, 1109 insertions(+), 34 deletions(-) create mode 100644 arch/ppc/kernel/rio.c create mode 100644 arch/ppc/syslib/ppc85xx_rio.c create mode 100644 arch/ppc/syslib/ppc85xx_rio.h create mode 100644 include/asm-ppc/rio.h (limited to 'arch/ppc') diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index f8db33d5527..8fa51b0a32d 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig @@ -1257,6 +1257,14 @@ source "drivers/pci/Kconfig" source "drivers/pcmcia/Kconfig" +config RAPIDIO + bool "RapidIO support" if MPC8540 || MPC8560 + help + If you say Y here, the kernel will include drivers and + infrastructure code to support RapidIO interconnect devices. + +source "drivers/rapidio/Kconfig" + endmenu menu "Advanced setup" diff --git a/arch/ppc/configs/stx_gp3_defconfig b/arch/ppc/configs/stx_gp3_defconfig index 66dae836765..3fedc43e44a 100644 --- a/arch/ppc/configs/stx_gp3_defconfig +++ b/arch/ppc/configs/stx_gp3_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.11-rc2 -# Wed Jan 26 14:32:58 2005 +# Linux kernel version: 2.6.12-rc4 +# Tue May 24 18:11:04 2005 # CONFIG_MMU=y CONFIG_GENERIC_HARDIRQS=y @@ -11,6 +11,7 @@ CONFIG_HAVE_DEC_LOCK=y CONFIG_PPC=y CONFIG_PPC32=y CONFIG_GENERIC_NVRAM=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # # Code maturity level options @@ -18,6 +19,7 @@ CONFIG_GENERIC_NVRAM=y CONFIG_EXPERIMENTAL=y CONFIG_CLEAN_COMPILE=y CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 # # General setup @@ -29,7 +31,6 @@ CONFIG_SYSVIPC=y # CONFIG_BSD_PROCESS_ACCT is not set CONFIG_SYSCTL=y # CONFIG_AUDIT is not set -CONFIG_LOG_BUF_SHIFT=14 CONFIG_HOTPLUG=y CONFIG_KOBJECT_UEVENT=y # CONFIG_IKCONFIG is not set @@ -37,6 +38,9 @@ CONFIG_EMBEDDED=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_ALL is not set # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set @@ -46,6 +50,7 @@ CONFIG_CC_ALIGN_LABELS=0 CONFIG_CC_ALIGN_LOOPS=0 CONFIG_CC_ALIGN_JUMPS=0 # CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 # # Loadable module support @@ -69,9 +74,11 @@ CONFIG_KMOD=y CONFIG_E500=y CONFIG_BOOKE=y CONFIG_FSL_BOOKE=y +# CONFIG_PHYS_64BIT is not set # CONFIG_SPE is not set CONFIG_MATH_EMULATION=y # CONFIG_CPU_FREQ is not set +# CONFIG_PM is not set CONFIG_85xx=y CONFIG_PPC_INDIRECT_PCI_BE=y @@ -96,6 +103,7 @@ CONFIG_HIGHMEM=y CONFIG_BINFMT_ELF=y CONFIG_BINFMT_MISC=m # CONFIG_CMDLINE_BOOL is not set +CONFIG_ISA_DMA_API=y # # Bus options @@ -104,15 +112,15 @@ CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_PCI_LEGACY_PROC is not set # CONFIG_PCI_NAMES is not set +# CONFIG_PCI_DEBUG is not set # # PCCARD (PCMCIA/CardBus) support # # CONFIG_PCCARD is not set - -# -# PC-card bridges -# +CONFIG_RAPIDIO=y +CONFIG_RAPIDIO_8_BIT_TRANSPORT=y +CONFIG_RAPIDIO_DISC_TIMEOUT=30 # # Advanced setup @@ -152,7 +160,7 @@ CONFIG_PARPORT=m CONFIG_PARPORT_PC=m # CONFIG_PARPORT_PC_FIFO is not set # CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_OTHER is not set +# CONFIG_PARPORT_GSC is not set # CONFIG_PARPORT_1284 is not set # @@ -264,7 +272,6 @@ CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_BUSLOGIC is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_EATA is not set -# CONFIG_SCSI_EATA_PIO is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GDTH is not set # CONFIG_SCSI_IPS is not set @@ -274,7 +281,6 @@ CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_IMM is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set -# CONFIG_SCSI_QLOGIC_ISP is not set # CONFIG_SCSI_QLOGIC_FC is not set # CONFIG_SCSI_QLOGIC_1280 is not set CONFIG_SCSI_QLA2XXX=m @@ -283,6 +289,7 @@ CONFIG_SCSI_QLA2XXX=m # CONFIG_SCSI_QLA2300 is not set # CONFIG_SCSI_QLA2322 is not set # CONFIG_SCSI_QLA6312 is not set +# CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_NSP32 is not set @@ -322,7 +329,6 @@ CONFIG_NET=y # CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set -# CONFIG_NETLINK_DEV is not set CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y @@ -431,7 +437,7 @@ CONFIG_IP_NF_NAT_FTP=m # # Network testing # -# CONFIG_NET_PKTGEN is not set +CONFIG_NET_PKTGEN=y # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_HAMRADIO is not set @@ -499,6 +505,7 @@ CONFIG_GFAR_NAPI=y # Wan interfaces # # CONFIG_WAN is not set +CONFIG_RIONET=y # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PLIP is not set @@ -535,20 +542,6 @@ CONFIG_INPUT_JOYDEV=m CONFIG_INPUT_EVDEV=m # CONFIG_INPUT_EVBUG is not set -# -# Input I/O drivers -# -# CONFIG_GAMEPORT is not set -CONFIG_SOUND_GAMEPORT=y -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set - # # Input Device Drivers # @@ -566,6 +559,19 @@ CONFIG_MOUSE_PS2=y # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set +CONFIG_SOUND_GAMEPORT=y + # # Character devices # @@ -590,6 +596,7 @@ CONFIG_SERIAL_CPM_SCC2=y # CONFIG_SERIAL_CPM_SCC4 is not set # CONFIG_SERIAL_CPM_SMC1 is not set # CONFIG_SERIAL_CPM_SMC2 is not set +# CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 @@ -625,6 +632,11 @@ CONFIG_DRM=m # CONFIG_DRM_SIS is not set # CONFIG_RAW_DRIVER is not set +# +# TPM devices +# +# CONFIG_TCG_TPM is not set + # # I2C support # @@ -648,12 +660,12 @@ CONFIG_I2C_ALGOBIT=m # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_I810 is not set +# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_ISA is not set # CONFIG_I2C_MPC is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_PROSAVAGE is not set # CONFIG_I2C_SAVAGE4 is not set # CONFIG_SCx200_ACB is not set @@ -677,7 +689,9 @@ CONFIG_I2C_ALGOBIT=m # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_FSCHER is not set +# CONFIG_SENSORS_FSCPOS is not set # CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM75 is not set @@ -688,9 +702,11 @@ CONFIG_I2C_ALGOBIT=m # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_W83781D is not set @@ -700,10 +716,12 @@ CONFIG_I2C_ALGOBIT=m # # Other I2C Chip support # +# CONFIG_SENSORS_DS1337 is not set # CONFIG_SENSORS_EEPROM is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_RTC8564 is not set +# CONFIG_SENSORS_M41T00 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set @@ -732,7 +750,6 @@ CONFIG_I2C_ALGOBIT=m # Graphics support # # CONFIG_FB is not set -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Sound @@ -752,13 +769,9 @@ CONFIG_SOUND=m # # USB support # -# CONFIG_USB is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y - -# -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information -# +# CONFIG_USB is not set # # USB Gadget Support @@ -789,6 +802,10 @@ CONFIG_JBD_DEBUG=y CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set + +# +# XFS support +# # CONFIG_XFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_ROMFS_FS is not set @@ -859,7 +876,6 @@ CONFIG_NFS_V3=y CONFIG_ROOT_NFS=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y -# CONFIG_EXPORTFS is not set CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set @@ -942,8 +958,10 @@ CONFIG_ZLIB_INFLATE=m # # Kernel hacking # +# CONFIG_PRINTK_TIME is not set CONFIG_DEBUG_KERNEL=y # CONFIG_MAGIC_SYSRQ is not set +CONFIG_LOG_BUF_SHIFT=14 # CONFIG_SCHEDSTATS is not set # CONFIG_DEBUG_SLAB is not set # CONFIG_DEBUG_SPINLOCK is not set diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index c610ca933a2..76a55a438f2 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_POWER4) += cpu_setup_power4.o obj-$(CONFIG_MODULES) += module.o ppc_ksyms.o obj-$(CONFIG_NOT_COHERENT_CACHE) += dma-mapping.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_RAPIDIO) += rio.o obj-$(CONFIG_KGDB) += ppc-stub.o obj-$(CONFIG_SMP) += smp.o smp-tbsync.o obj-$(CONFIG_TAU) += temp.o diff --git a/arch/ppc/kernel/rio.c b/arch/ppc/kernel/rio.c new file mode 100644 index 00000000000..29487fedfc7 --- /dev/null +++ b/arch/ppc/kernel/rio.c @@ -0,0 +1,52 @@ +/* + * RapidIO PPC32 support + * + * Copyright 2005 MontaVista Software, Inc. + * Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +/** + * platform_rio_init - Do platform specific RIO init + * + * Any platform specific initialization of RapdIO + * hardware is done here as well as registration + * of any active master ports in the system. + */ +void __attribute__ ((weak)) + platform_rio_init(void) +{ + printk(KERN_WARNING "RIO: No platform_rio_init() present\n"); +} + +/** + * ppc_rio_init - Do PPC32 RIO init + * + * Calls platform-specific RIO init code and then calls + * rio_init_mports() to initialize any master ports that + * have been registered with the RIO subsystem. + */ +static int __init ppc_rio_init(void) +{ + printk(KERN_INFO "RIO: RapidIO init\n"); + + /* Platform specific initialization */ + platform_rio_init(); + + /* Enumerate all registered ports */ + rio_init_mports(); + + return 0; +} + +subsys_initcall(ppc_rio_init); diff --git a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c index bd3ac013675..16ad092d8a0 100644 --- a/arch/ppc/platforms/85xx/mpc85xx_ads_common.c +++ b/arch/ppc/platforms/85xx/mpc85xx_ads_common.c @@ -45,6 +45,8 @@ #include +#include + #include #ifndef CONFIG_PCI @@ -189,3 +191,11 @@ mpc85xx_exclude_device(u_char bus, u_char devfn) } #endif /* CONFIG_PCI */ + +#ifdef CONFIG_RAPIDIO +void platform_rio_init(void) +{ + /* 512MB RIO LAW at 0xc0000000 */ + mpc85xx_rio_setup(0xc0000000, 0x20000000); +} +#endif /* CONFIG_RAPIDIO */ diff --git a/arch/ppc/platforms/85xx/stx_gp3.c b/arch/ppc/platforms/85xx/stx_gp3.c index 1e1b85f8193..15ce9d07063 100644 --- a/arch/ppc/platforms/85xx/stx_gp3.c +++ b/arch/ppc/platforms/85xx/stx_gp3.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -57,6 +58,7 @@ #include #include +#include unsigned char __res[sizeof(bd_t)]; @@ -273,6 +275,18 @@ int mpc85xx_exclude_device(u_char bus, u_char devfn) } #endif /* CONFIG_PCI */ +#ifdef CONFIG_RAPIDIO +void +platform_rio_init(void) +{ + /* + * The STx firmware configures the RapidIO Local Access Window + * at 0xc0000000 with a size of 512MB. + */ + mpc85xx_rio_setup(0xc0000000, 0x20000000); +} +#endif /* CONFIG_RAPIDIO */ + void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5, unsigned long r6, unsigned long r7) diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile index dcd168f9a7a..5bd33baac24 100644 --- a/arch/ppc/syslib/Makefile +++ b/arch/ppc/syslib/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_PPC4xx_DMA) += ppc4xx_dma.o obj-$(CONFIG_PPC4xx_EDMA) += ppc4xx_sgdma.o ifeq ($(CONFIG_40x),y) obj-$(CONFIG_PCI) += pci_auto.o ppc405_pci.o +obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o endif endif obj-$(CONFIG_8xx) += m8xx_setup.o ppc8xx_pic.o $(wdt-mpc8xx-y) \ diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c new file mode 100644 index 00000000000..9d09c2715e0 --- /dev/null +++ b/arch/ppc/syslib/ppc85xx_rio.c @@ -0,0 +1,932 @@ +/* + * MPC85xx RapidIO support + * + * Copyright 2005 MontaVista Software, Inc. + * Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define RIO_REGS_BASE (CCSRBAR + 0xc0000) +#define RIO_ATMU_REGS_OFFSET 0x10c00 +#define RIO_MSG_REGS_OFFSET 0x11000 +#define RIO_MAINT_WIN_SIZE 0x400000 +#define RIO_DBELL_WIN_SIZE 0x1000 + +#define RIO_MSG_OMR_MUI 0x00000002 +#define RIO_MSG_OSR_TE 0x00000080 +#define RIO_MSG_OSR_QOI 0x00000020 +#define RIO_MSG_OSR_QFI 0x00000010 +#define RIO_MSG_OSR_MUB 0x00000004 +#define RIO_MSG_OSR_EOMI 0x00000002 +#define RIO_MSG_OSR_QEI 0x00000001 + +#define RIO_MSG_IMR_MI 0x00000002 +#define RIO_MSG_ISR_TE 0x00000080 +#define RIO_MSG_ISR_QFI 0x00000010 +#define RIO_MSG_ISR_DIQI 0x00000001 + +#define RIO_MSG_DESC_SIZE 32 +#define RIO_MSG_BUFFER_SIZE 4096 +#define RIO_MIN_TX_RING_SIZE 2 +#define RIO_MAX_TX_RING_SIZE 2048 +#define RIO_MIN_RX_RING_SIZE 2 +#define RIO_MAX_RX_RING_SIZE 2048 + +#define DOORBELL_DMR_DI 0x00000002 +#define DOORBELL_DSR_TE 0x00000080 +#define DOORBELL_DSR_QFI 0x00000010 +#define DOORBELL_DSR_DIQI 0x00000001 +#define DOORBELL_TID_OFFSET 0x03 +#define DOORBELL_SID_OFFSET 0x05 +#define DOORBELL_INFO_OFFSET 0x06 + +#define DOORBELL_MESSAGE_SIZE 0x08 +#define DBELL_SID(x) (*(u8 *)(x + DOORBELL_SID_OFFSET)) +#define DBELL_TID(x) (*(u8 *)(x + DOORBELL_TID_OFFSET)) +#define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) + +#define is_power_of_2(x) (((x) & ((x) - 1)) == 0) + +struct rio_atmu_regs { + u32 rowtar; + u32 pad1; + u32 rowbar; + u32 pad2; + u32 rowar; + u32 pad3[3]; +}; + +struct rio_msg_regs { + u32 omr; + u32 osr; + u32 pad1; + u32 odqdpar; + u32 pad2; + u32 osar; + u32 odpr; + u32 odatr; + u32 odcr; + u32 pad3; + u32 odqepar; + u32 pad4[13]; + u32 imr; + u32 isr; + u32 pad5; + u32 ifqdpar; + u32 pad6; + u32 ifqepar; + u32 pad7[250]; + u32 dmr; + u32 dsr; + u32 pad8; + u32 dqdpar; + u32 pad9; + u32 dqepar; + u32 pad10[26]; + u32 pwmr; + u32 pwsr; + u32 pad11; + u32 pwqbar; +}; + +struct rio_tx_desc { + u32 res1; + u32 saddr; + u32 dport; + u32 dattr; + u32 res2; + u32 res3; + u32 dwcnt; + u32 res4; +}; + +static u32 regs_win; +static struct rio_atmu_regs *atmu_regs; +static struct rio_atmu_regs *maint_atmu_regs; +static struct rio_atmu_regs *dbell_atmu_regs; +static u32 dbell_win; +static u32 maint_win; +static struct rio_msg_regs *msg_regs; + +static struct rio_dbell_ring { + void *virt; + dma_addr_t phys; +} dbell_ring; + +static struct rio_msg_tx_ring { + void *virt; + dma_addr_t phys; + void *virt_buffer[RIO_MAX_TX_RING_SIZE]; + dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; + int tx_slot; + int size; +} msg_tx_ring; + +static struct rio_msg_rx_ring { + void *virt; + dma_addr_t phys; + void *virt_buffer[RIO_MAX_RX_RING_SIZE]; + int rx_slot; + int size; +} msg_rx_ring; + +/** + * mpc85xx_rio_doorbell_send - Send a MPC85xx doorbell message + * @index: ID of RapidIO interface + * @destid: Destination ID of target device + * @data: 16-bit info field of RapidIO doorbell message + * + * Sends a MPC85xx doorbell message. Returns %0 on success or + * %-EINVAL on failure. + */ +static int mpc85xx_rio_doorbell_send(int index, u16 destid, u16 data) +{ + pr_debug("mpc85xx_doorbell_send: index %d destid %4.4x data %4.4x\n", + index, destid, data); + out_be32((void *)&dbell_atmu_regs->rowtar, destid << 22); + out_be16((void *)(dbell_win), data); + + return 0; +} + +/** + * mpc85xx_local_config_read - Generate a MPC85xx local config space read + * @index: ID of RapdiIO interface + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be read into + * + * Generates a MPC85xx local configuration space read. Returns %0 on + * success or %-EINVAL on failure. + */ +static int mpc85xx_local_config_read(int index, u32 offset, int len, u32 * data) +{ + pr_debug("mpc85xx_local_config_read: index %d offset %8.8x\n", index, + offset); + *data = in_be32((void *)(regs_win + offset)); + + return 0; +} + +/** + * mpc85xx_local_config_write - Generate a MPC85xx local config space write + * @index: ID of RapdiIO interface + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @data: Value to be written + * + * Generates a MPC85xx local configuration space write. Returns %0 on + * success or %-EINVAL on failure. + */ +static int mpc85xx_local_config_write(int index, u32 offset, int len, u32 data) +{ + pr_debug + ("mpc85xx_local_config_write: index %d offset %8.8x data %8.8x\n", + index, offset, data); + out_be32((void *)(regs_win + offset), data); + + return 0; +} + +/** + * mpc85xx_rio_config_read - Generate a MPC85xx read maintenance transaction + * @index: ID of RapdiIO interface + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Location to be read into + * + * Generates a MPC85xx read maintenance transaction. Returns %0 on + * success or %-EINVAL on failure. + */ +static int +mpc85xx_rio_config_read(int index, u16 destid, u8 hopcount, u32 offset, int len, + u32 * val) +{ + u8 *data; + + pr_debug + ("mpc85xx_rio_config_read: index %d destid %d hopcount %d offset %8.8x len %d\n", + index, destid, hopcount, offset, len); + out_be32((void *)&maint_atmu_regs->rowtar, + (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); + + data = (u8 *) maint_win + offset; + switch (len) { + case 1: + *val = in_8((u8 *) data); + break; + case 2: + *val = in_be16((u16 *) data); + break; + default: + *val = in_be32((u32 *) data); + break; + } + + return 0; +} + +/** + * mpc85xx_rio_config_write - Generate a MPC85xx write maintenance transaction + * @index: ID of RapdiIO interface + * @destid: Destination ID of transaction + * @hopcount: Number of hops to target device + * @offset: Offset into configuration space + * @len: Length (in bytes) of the maintenance transaction + * @val: Value to be written + * + * Generates an MPC85xx write maintenance transaction. Returns %0 on + * success or %-EINVAL on failure. + */ +static int +mpc85xx_rio_config_write(int index, u16 destid, u8 hopcount, u32 offset, + int len, u32 val) +{ + u8 *data; + pr_debug + ("mpc85xx_rio_config_write: index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n", + index, destid, hopcount, offset, len, val); + out_be32((void *)&maint_atmu_regs->rowtar, + (destid << 22) | (hopcount << 12) | ((offset & ~0x3) >> 9)); + + data = (u8 *) maint_win + offset; + switch (len) { + case 1: + out_8((u8 *) data, val); + break; + case 2: + out_be16((u16 *) data, val); + break; + default: + out_be32((u32 *) data, val); + break; + } + + return 0; +} + +/** + * rio_hw_add_outb_message - Add message to the MPC85xx outbound message queue + * @mport: Master port with outbound message queue + * @rdev: Target of outbound message + * @mbox: Outbound mailbox + * @buffer: Message to add to outbound queue + * @len: Length of message + * + * Adds the @buffer message to the MPC85xx outbound message queue. Returns + * %0 on success or %-EINVAL on failure. + */ +int +rio_hw_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, + void *buffer, size_t len) +{ + u32 omr; + struct rio_tx_desc *desc = + (struct rio_tx_desc *)msg_tx_ring.virt + msg_tx_ring.tx_slot; + int ret = 0; + + pr_debug + ("RIO: rio_hw_add_outb_message(): destid %4.4x mbox %d buffer %8.8x len %8.8x\n", + rdev->destid, mbox, (int)buffer, len); + + if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { + ret = -EINVAL; + goto out; + } + + /* Copy and clear rest of buffer */ + memcpy(msg_tx_ring.virt_buffer[msg_tx_ring.tx_slot], buffer, len); + if (len < (RIO_MAX_MSG_SIZE - 4)) + memset((void *)((u32) msg_tx_ring. + virt_buffer[msg_tx_ring.tx_slot] + len), 0, + RIO_MAX_MSG_SIZE - len); + + /* Set mbox field for message */ + desc->dport = mbox & 0x3; + + /* Enable EOMI interrupt, set priority, and set destid */ + desc->dattr = 0x28000000 | (rdev->destid << 2); + + /* Set transfer size aligned to next power of 2 (in double words) */ + desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); + + /* Set snooping and source buffer address */ + desc->saddr = 0x00000004 | msg_tx_ring.phys_buffer[msg_tx_ring.tx_slot]; + + /* Increment enqueue pointer */ + omr = in_be32((void *)&msg_regs->omr); + out_be32((void *)&msg_regs->omr, omr | RIO_MSG_OMR_MUI); + + /* Go to next descriptor */ + if (++msg_tx_ring.tx_slot == msg_tx_ring.size) + msg_tx_ring.tx_slot = 0; + + out: + return ret; +} + +EXPORT_SYMBOL_GPL(rio_hw_add_outb_message); + +/** + * mpc85xx_rio_tx_handler - MPC85xx outbound message interrupt handler + * @irq: Linux interrupt number + * @dev_instance: Pointer to interrupt-specific data + * @regs: Register context + * + * Handles outbound message interrupts. Executes a register outbound + * mailbox event handler and acks the interrupt occurence. + */ +static irqreturn_t +mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs) +{ + int osr; + struct rio_mport *port = (struct rio_mport *)dev_instance; + + osr = in_be32((void *)&msg_regs->osr); + + if (osr & RIO_MSG_OSR_TE) { + pr_info("RIO: outbound message transmission error\n"); + out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_TE); + goto out; + } + + if (osr & RIO_MSG_OSR_QOI) { + pr_info("RIO: outbound message queue overflow\n"); + out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_QOI); + goto out; + } + + if (osr & RIO_MSG_OSR_EOMI) { + u32 dqp = in_be32((void *)&msg_regs->odqdpar); + int slot = (dqp - msg_tx_ring.phys) >> 5; + port->outb_msg[0].mcback(port, -1, slot); + + /* Ack the end-of-message interrupt */ + out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI); + } + + out: + return IRQ_HANDLED; +} + +/** + * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox + * @mport: Master port implementing the outbound message unit + * @mbox: Mailbox to open + * @entries: Number of entries in the outbound mailbox ring + * + * Initializes buffer ring, request the outbound message interrupt, + * and enables the outbound message unit. Returns %0 on success and + * %-EINVAL or %-ENOMEM on failure. + */ +int rio_open_outb_mbox(struct rio_mport *mport, int mbox, int entries) +{ + int i, j, rc = 0; + + if ((entries < RIO_MIN_TX_RING_SIZE) || + (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { + rc = -EINVAL; + goto out; + } + + /* Initialize shadow copy ring */ + msg_tx_ring.size = entries; + + for (i = 0; i < msg_tx_ring.size; i++) { + if (! + (msg_tx_ring.virt_buffer[i] = + dma_alloc_coherent(NULL, RIO_MSG_BUFFER_SIZE, + &msg_tx_ring.phys_buffer[i], + GFP_KERNEL))) { + rc = -ENOMEM; + for (j = 0; j < msg_tx_ring.size; j++) + if (msg_tx_ring.virt_buffer[j]) + dma_free_coherent(NULL, + RIO_MSG_BUFFER_SIZE, + msg_tx_ring. + virt_buffer[j], + msg_tx_ring. + phys_buffer[j]); + goto out; + } + } + + /* Initialize outbound message descriptor ring */ + if (!(msg_tx_ring.virt = dma_alloc_coherent(NULL, + msg_tx_ring.size * + RIO_MSG_DESC_SIZE, + &msg_tx_ring.phys, + GFP_KERNEL))) { + rc = -ENOMEM; + goto out_dma; + } + memset(msg_tx_ring.virt, 0, msg_tx_ring.size * RIO_MSG_DESC_SIZE); + msg_tx_ring.tx_slot = 0; + + /* Point dequeue/enqueue pointers at first entry in ring */ + out_be32((void *)&msg_regs->odqdpar, msg_tx_ring.phys); + out_be32((void *)&msg_regs->odqepar, msg_tx_ring.phys); + + /* Configure for snooping */ + out_be32((void *)&msg_regs->osar, 0x00000004); + + /* Clear interrupt status */ + out_be32((void *)&msg_regs->osr, 0x000000b3); + + /* Hook up outbound message handler */ + if ((rc = + request_irq(MPC85xx_IRQ_RIO_TX, mpc85xx_rio_tx_handler, 0, + "msg_tx", (void *)mport)) < 0) + goto out_irq; + + /* + * Configure outbound message unit + * Snooping + * Interrupts (all enabled, except QEIE) + * Chaining mode + * Disable + */ + out_be32((void *)&msg_regs->omr, 0x00100220); + + /* Set number of entries */ + out_be32((void *)&msg_regs->omr, + in_be32((void *)&msg_regs->omr) | + ((get_bitmask_order(entries) - 2) << 12)); + + /* Now enable the unit */ + out_be32((void *)&msg_regs->omr, in_be32((void *)&msg_regs->omr) | 0x1); + + out: + return rc; + + out_irq: + dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE, + msg_tx_ring.virt, msg_tx_ring.phys); + + out_dma: + for (i = 0; i < msg_tx_ring.size; i++) + dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, + msg_tx_ring.virt_buffer[i], + msg_tx_ring.phys_buffer[i]); + + return rc; +} + +/** + * rio_close_outb_mbox - Shut down MPC85xx outbound mailbox + * @mport: Master port implementing the outbound message unit + * @mbox: Mailbox to close + * + * Disables the outbound message unit, free all buffers, and + * frees the outbound message interrupt. + */ +void rio_close_outb_mbox(struct rio_mport *mport, int mbox) +{ + /* Disable inbound message unit */ + out_be32((void *)&msg_regs->omr, 0); + + /* Free ring */ + dma_free_coherent(NULL, msg_tx_ring.size * RIO_MSG_DESC_SIZE, + msg_tx_ring.virt, msg_tx_ring.phys); + + /* Free interrupt */ + free_irq(MPC85xx_IRQ_RIO_TX, (void *)mport); +} + +/** + * mpc85xx_rio_rx_handler - MPC85xx inbound message interrupt handler + * @irq: Linux interrupt number + * @dev_instance: Pointer to interrupt-specific data + * @regs: Register context + * + * Handles inbound message interrupts. Executes a registered inbound + * mailbox event handler and acks the interrupt occurence. + */ +static irqreturn_t +mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs) +{ + int isr; + struct rio_mport *port = (struct rio_mport *)dev_instance; + + isr = in_be32((void *)&msg_regs->isr); + + if (isr & RIO_MSG_ISR_TE) { + pr_info("RIO: inbound message reception error\n"); + out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_TE); + goto out; + } + + /* XXX Need to check/dispatch until queue empty */ + if (isr & RIO_MSG_ISR_DIQI) { + /* + * We implement *only* mailbox 0, but can receive messages + * for any mailbox/letter to that mailbox destination. So, + * make the callback with an unknown/invalid mailbox number + * argument. + */ + port->inb_msg[0].mcback(port, -1, -1); + + /* Ack the queueing interrupt */ + out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI); + } + + out: + return IRQ_HANDLED; +} + +/** + * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox + * @mport: Master port implementing the inbound message unit + * @mbox: Mailbox to open + * @entries: Number of entries in the inbound mailbox ring + * + * Initializes buffer ring, request the inbound message interrupt, + * and enables the inbound message unit. Returns %0 on success + * and %-EINVAL or %-ENOMEM on failure. + */ +int rio_open_inb_mbox(struct rio_mport *mport, int mbox, int entries) +{ + int i, rc = 0; + + if ((entries < RIO_MIN_RX_RING_SIZE) || + (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { + rc = -EINVAL; + goto out; + } + + /* Initialize client buffer ring */ + msg_rx_ring.size = entries; + msg_rx_ring.rx_slot = 0; + for (i = 0; i < msg_rx_ring.size; i++) + msg_rx_ring.virt_buffer[i] = NULL; + + /* Initialize inbound message ring */ + if (!(msg_rx_ring.virt = dma_alloc_coherent(NULL, + msg_rx_ring.size * + RIO_MAX_MSG_SIZE, + &msg_rx_ring.phys, + GFP_KERNEL))) { + rc = -ENOMEM; + goto out; + } + + /* Point dequeue/enqueue pointers at first entry in ring */ + out_be32((void *)&msg_regs->ifqdpar, (u32) msg_rx_ring.phys); + out_be32((void *)&msg_regs->ifqepar, (u32) msg_rx_ring.phys); + + /* Clear interrupt status */ + out_be32((void *)&msg_regs->isr, 0x00000091); + + /* Hook up inbound message handler */ + if ((rc = + request_irq(MPC85xx_IRQ_RIO_RX, mpc85xx_rio_rx_handler, 0, + "msg_rx", (void *)mport)) < 0) { + dma_free_coherent(NULL, RIO_MSG_BUFFER_SIZE, + msg_tx_ring.virt_buffer[i], + msg_tx_ring.phys_buffer[i]); + goto out; + } + + /* + * Configure inbound message unit: + * Snooping + * 4KB max message size + * Unmask all interrupt sources + * Disable + */ + out_be32((void *)&msg_regs->imr, 0x001b0060); + + /* Set number of queue entries */ + out_be32((void *)&msg_regs->imr, + in_be32((void *)&msg_regs->imr) | + ((get_bitmask_order(entries) - 2) << 12)); + + /* Now enable the unit */ + out_be32((void *)&msg_regs->imr, in_be32((void *)&msg_regs->imr) | 0x1); + + out: + return rc; +} + +/** + * rio_close_inb_mbox - Shut down MPC85xx inbound mailbox + * @mport: Master port implementing the inbound message unit + * @mbox: Mailbox to close + * + * Disables the inbound message unit, free all buffers, and + * frees the inbound message interrupt. + */ +void rio_close_inb_mbox(struct rio_mport *mport, int mbox) +{ + /* Disable inbound message unit */ + out_be32((void *)&msg_regs->imr, 0); + + /* Free ring */ + dma_free_coherent(NULL, msg_rx_ring.size * RIO_MAX_MSG_SIZE, + msg_rx_ring.virt, msg_rx_ring.phys); + + /* Free interrupt */ + free_irq(MPC85xx_IRQ_RIO_RX, (void *)mport); +} + +/** + * rio_hw_add_inb_buffer - Add buffer to the MPC85xx inbound message queue + * @mport: Master port implementing the inbound message unit + * @mbox: Inbound mailbox number + * @buf: Buffer to add to inbound queue + * + * Adds the @buf buffer to the MPC85xx inbound message queue. Returns + * %0 on success or %-EINVAL on failure. + */ +int rio_hw_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) +{ + int rc = 0; + + pr_debug("RIO: rio_hw_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", + msg_rx_ring.rx_slot); + + if (msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot]) { + printk(KERN_ERR + "RIO: error adding inbound buffer %d, buffer exists\n", + msg_rx_ring.rx_slot); + rc = -EINVAL; + goto out; + } + + msg_rx_ring.virt_buffer[msg_rx_ring.rx_slot] = buf; + if (++msg_rx_ring.rx_slot == msg_rx_ring.size) + msg_rx_ring.rx_slot = 0; + + out: + return rc; +} + +EXPORT_SYMBOL_GPL(rio_hw_add_inb_buffer); + +/** + * rio_hw_get_inb_message - Fetch inbound message from the MPC85xx message unit + * @mport: Master port implementing the inbound message unit + * @mbox: Inbound mailbox number + * + * Gets the next available inbound message from the inbound message queue. + * A pointer to the message is returned on success or NULL on failure. + */ +void *rio_hw_get_inb_message(struct rio_mport *mport, int mbox) +{ + u32 imr; + u32 phys_buf, virt_buf; + void *buf = NULL; + int buf_idx; + + phys_buf = in_be32((void *)&msg_regs->ifqdpar); + + /* If no more messages, then bail out */ + if (phys_buf == in_be32((void *)&msg_regs->ifqepar)) + goto out2; + + virt_buf = (u32) msg_rx_ring.virt + (phys_buf - msg_rx_ring.phys); + buf_idx = (phys_buf - msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; + buf = msg_rx_ring.virt_buffer[buf_idx]; + + if (!buf) { + printk(KERN_ERR + "RIO: inbound message copy failed, no buffers\n"); + goto out1; + } + + /* Copy max message size, caller is expected to allocate that big */ + memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); + + /* Clear the available buffer */ + msg_rx_ring.virt_buffer[buf_idx] = NULL; + + out1: + imr = in_be32((void *)&msg_regs->imr); + out_be32((void *)&msg_regs->imr, imr | RIO_MSG_IMR_MI); + + out2: + return buf; +} + +EXPORT_SYMBOL_GPL(rio_hw_get_inb_message); + +/** + * mpc85xx_rio_dbell_handler - MPC85xx doorbell interrupt handler + * @irq: Linux interrupt number + * @dev_instance: Pointer to interrupt-specific data + * @regs: Register context + * + * Handles doorbell interrupts. Parses a list of registered + * doorbell event handlers and executes a matching event handler. + */ +static irqreturn_t +mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs) +{ + int dsr; + struct rio_mport *port = (struct rio_mport *)dev_instance; + + dsr = in_be32((void *)&msg_regs->dsr); + + if (dsr & DOORBELL_DSR_TE) { + pr_info("RIO: doorbell reception error\n"); + out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_TE); + goto out; + } + + if (dsr & DOORBELL_DSR_QFI) { + pr_info("RIO: doorbell queue full\n"); + out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_QFI); + goto out; + } + + /* XXX Need to check/dispatch until queue empty */ + if (dsr & DOORBELL_DSR_DIQI) { + u32 dmsg = + (u32) dbell_ring.virt + + (in_be32((void *)&msg_regs->dqdpar) & 0xfff); + u32 dmr; + struct rio_dbell *dbell; + int found = 0; + + pr_debug + ("RIO: processing doorbell, sid %2.2x tid %2.2x info %4.4x\n", + DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); + + list_for_each_entry(dbell, &port->dbells, node) { + if ((dbell->res->start <= DBELL_INF(dmsg)) && + (dbell->res->end >= DBELL_INF(dmsg))) { + found = 1; + break; + } + } + if (found) { + dbell->dinb(port, DBELL_SID(dmsg), DBELL_TID(dmsg), + DBELL_INF(dmsg)); + } else { + pr_debug + ("RIO: spurious doorbell, sid %2.2x tid %2.2x info %4.4x\n", + DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); + } + dmr = in_be32((void *)&msg_regs->dmr); + out_be32((void *)&msg_regs->dmr, dmr | DOORBELL_DMR_DI); + out_be32((void *)&msg_regs->dsr, DOORBELL_DSR_DIQI); + } + + out: + return IRQ_HANDLED; +} + +/** + * mpc85xx_rio_doorbell_init - MPC85xx doorbell interface init + * @mport: Master port implementing the inbound doorbell unit + * + * Initializes doorbell unit hardware and inbound DMA buffer + * ring. Called from mpc85xx_rio_setup(). Returns %0 on success + * or %-ENOMEM on failure. + */ +static int mpc85xx_rio_doorbell_init(struct rio_mport *mport) +{ + int rc = 0; + + /* Map outbound doorbell window immediately after maintenance window */ + if (!(dbell_win = + (u32) ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, + RIO_DBELL_WIN_SIZE))) { + printk(KERN_ERR + "RIO: unable to map outbound doorbell window\n"); + rc = -ENOMEM; + goto out; + } + + /* Initialize inbound doorbells */ + if (!(dbell_ring.virt = dma_alloc_coherent(NULL, + 512 * DOORBELL_MESSAGE_SIZE, + &dbell_ring.phys, + GFP_KERNEL))) { + printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); + rc = -ENOMEM; + iounmap((void *)dbell_win); + goto out; + } + + /* Point dequeue/enqueue pointers at first entry in ring */ + out_be32((void *)&msg_regs->dqdpar, (u32) dbell_ring.phys); + out_be32((void *)&msg_regs->dqepar, (u32) dbell_ring.phys); + + /* Clear interrupt status */ + out_be32((void *)&msg_regs->dsr, 0x00000091); + + /* Hook up doorbell handler */ + if ((rc = + request_irq(MPC85xx_IRQ_RIO_BELL, mpc85xx_rio_dbell_handler, 0, + "dbell_rx", (void *)mport) < 0)) { + iounmap((void *)dbell_win); + dma_free_coherent(NULL, 512 * DOORBELL_MESSAGE_SIZE, + dbell_ring.virt, dbell_ring.phys); + printk(KERN_ERR + "MPC85xx RIO: unable to request inbound doorbell irq"); + goto out; + } + + /* Configure doorbells for snooping, 512 entries, and enable */ + out_be32((void *)&msg_regs->dmr, 0x00108161); + + out: + return rc; +} + +static char *cmdline = NULL; + +static int mpc85xx_rio_get_hdid(int index) +{ + /* XXX Need to parse multiple entries in some format */ + if (!cmdline) + return -1; + + return simple_strtol(cmdline, NULL, 0); +} + +static int mpc85xx_rio_get_cmdline(char *s) +{ + if (!s) + return 0; + + cmdline = s; + return 1; +} + +__setup("riohdid=", mpc85xx_rio_get_cmdline); + +/** + * mpc85xx_rio_setup - Setup MPC85xx RapidIO interface + * @law_start: Starting physical address of RapidIO LAW + * @law_size: Size of RapidIO LAW + * + * Initializes MPC85xx RapidIO hardware interface, configures + * master port with system-specific info, and registers the + * master port with the RapidIO subsystem. + */ +void mpc85xx_rio_setup(int law_start, int law_size) +{ + struct rio_ops *ops; + struct rio_mport *port; + + ops = kmalloc(sizeof(struct rio_ops), GFP_KERNEL); + ops->lcread = mpc85xx_local_config_read; + ops->lcwrite = mpc85xx_local_config_write; + ops->cread = mpc85xx_rio_config_read; + ops->cwrite = mpc85xx_rio_config_write; + ops->dsend = mpc85xx_rio_doorbell_send; + + port = kmalloc(sizeof(struct rio_mport), GFP_KERNEL); + port->id = 0; + port->index = 0; + INIT_LIST_HEAD(&port->dbells); + port->iores.start = law_start; + port->iores.end = law_start + law_size; + port->iores.flags = IORESOURCE_MEM; + + rio_init_dbell_res(&port->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); + rio_init_mbox_res(&port->riores[RIO_INB_MBOX_RESOURCE], 0, 0); + rio_init_mbox_res(&port->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); + strcpy(port->name, "RIO0 mport"); + + port->ops = ops; + port->host_deviceid = mpc85xx_rio_get_hdid(port->id); + + rio_register_mport(port); + + regs_win = (u32) ioremap(RIO_REGS_BASE, 0x20000); + atmu_regs = (struct rio_atmu_regs *)(regs_win + RIO_ATMU_REGS_OFFSET); + maint_atmu_regs = atmu_regs + 1; + dbell_atmu_regs = atmu_regs + 2; + msg_regs = (struct rio_msg_regs *)(regs_win + RIO_MSG_REGS_OFFSET); + + /* Configure maintenance transaction window */ + out_be32((void *)&maint_atmu_regs->rowbar, 0x000c0000); + out_be32((void *)&maint_atmu_regs->rowar, 0x80077015); + + maint_win = (u32) ioremap(law_start, RIO_MAINT_WIN_SIZE); + + /* Configure outbound doorbell window */ + out_be32((void *)&dbell_atmu_regs->rowbar, 0x000c0400); + out_be32((void *)&dbell_atmu_regs->rowar, 0x8004200b); + mpc85xx_rio_doorbell_init(port); +} diff --git a/arch/ppc/syslib/ppc85xx_rio.h b/arch/ppc/syslib/ppc85xx_rio.h new file mode 100644 index 00000000000..c0827a2c3ee --- /dev/null +++ b/arch/ppc/syslib/ppc85xx_rio.h @@ -0,0 +1,21 @@ +/* + * MPC85xx RapidIO definitions + * + * Copyright 2005 MontaVista Software, Inc. + * Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __PPC_SYSLIB_PPC85XX_RIO_H +#define __PPC_SYSLIB_PPC85XX_RIO_H + +#include +#include + +extern void mpc85xx_rio_setup(int law_start, int law_size); + +#endif /* __PPC_SYSLIB_PPC85XX_RIO_H */ diff --git a/include/asm-ppc/rio.h b/include/asm-ppc/rio.h new file mode 100644 index 00000000000..0018bf80cb2 --- /dev/null +++ b/include/asm-ppc/rio.h @@ -0,0 +1,18 @@ +/* + * RapidIO architecture support + * + * Copyright 2005 MontaVista Software, Inc. + * Matt Porter + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef ASM_PPC_RIO_H +#define ASM_PPC_RIO_H + +extern void platform_rio_init(void); + +#endif /* ASM_PPC_RIO_H */ -- cgit v1.2.3 From 6978bbc097c2f665c336927a9d56ae39ef75fa56 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Mon, 7 Nov 2005 01:00:20 -0800 Subject: [PATCH] rapidio: message interface updates Updates the RIO messaging interface to pass a device instance into the event registeration and callbacks. Signed-off-by: Matt Porter Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/syslib/ppc85xx_rio.c | 16 +++++++++++----- drivers/rapidio/rio-sysfs.c | 4 ++-- drivers/rapidio/rio.c | 25 ++++++++++++++++--------- include/linux/rio.h | 10 ++++++---- include/linux/rio_drv.h | 12 ++++++------ 5 files changed, 41 insertions(+), 26 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/syslib/ppc85xx_rio.c b/arch/ppc/syslib/ppc85xx_rio.c index 9d09c2715e0..297f3b54917 100644 --- a/arch/ppc/syslib/ppc85xx_rio.c +++ b/arch/ppc/syslib/ppc85xx_rio.c @@ -135,6 +135,7 @@ static struct rio_msg_tx_ring { dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; int tx_slot; int size; + void *dev_id; } msg_tx_ring; static struct rio_msg_rx_ring { @@ -143,6 +144,7 @@ static struct rio_msg_rx_ring { void *virt_buffer[RIO_MAX_RX_RING_SIZE]; int rx_slot; int size; + void *dev_id; } msg_rx_ring; /** @@ -376,7 +378,7 @@ mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs) if (osr & RIO_MSG_OSR_EOMI) { u32 dqp = in_be32((void *)&msg_regs->odqdpar); int slot = (dqp - msg_tx_ring.phys) >> 5; - port->outb_msg[0].mcback(port, -1, slot); + port->outb_msg[0].mcback(port, msg_tx_ring.dev_id, -1, slot); /* Ack the end-of-message interrupt */ out_be32((void *)&msg_regs->osr, RIO_MSG_OSR_EOMI); @@ -389,6 +391,7 @@ mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs) /** * rio_open_outb_mbox - Initialize MPC85xx outbound mailbox * @mport: Master port implementing the outbound message unit + * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox to open * @entries: Number of entries in the outbound mailbox ring * @@ -396,7 +399,7 @@ mpc85xx_rio_tx_handler(int irq, void *dev_instance, struct pt_regs *regs) * and enables the outbound message unit. Returns %0 on success and * %-EINVAL or %-ENOMEM on failure. */ -int rio_open_outb_mbox(struct rio_mport *mport, int mbox, int entries) +int rio_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) { int i, j, rc = 0; @@ -407,6 +410,7 @@ int rio_open_outb_mbox(struct rio_mport *mport, int mbox, int entries) } /* Initialize shadow copy ring */ + msg_tx_ring.dev_id = dev_id; msg_tx_ring.size = entries; for (i = 0; i < msg_tx_ring.size; i++) { @@ -541,7 +545,7 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs) * make the callback with an unknown/invalid mailbox number * argument. */ - port->inb_msg[0].mcback(port, -1, -1); + port->inb_msg[0].mcback(port, msg_rx_ring.dev_id, -1, -1); /* Ack the queueing interrupt */ out_be32((void *)&msg_regs->isr, RIO_MSG_ISR_DIQI); @@ -554,6 +558,7 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs) /** * rio_open_inb_mbox - Initialize MPC85xx inbound mailbox * @mport: Master port implementing the inbound message unit + * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox to open * @entries: Number of entries in the inbound mailbox ring * @@ -561,7 +566,7 @@ mpc85xx_rio_rx_handler(int irq, void *dev_instance, struct pt_regs *regs) * and enables the inbound message unit. Returns %0 on success * and %-EINVAL or %-ENOMEM on failure. */ -int rio_open_inb_mbox(struct rio_mport *mport, int mbox, int entries) +int rio_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) { int i, rc = 0; @@ -572,6 +577,7 @@ int rio_open_inb_mbox(struct rio_mport *mport, int mbox, int entries) } /* Initialize client buffer ring */ + msg_rx_ring.dev_id = dev_id; msg_rx_ring.size = entries; msg_rx_ring.rx_slot = 0; for (i = 0; i < msg_rx_ring.size; i++) @@ -777,7 +783,7 @@ mpc85xx_rio_dbell_handler(int irq, void *dev_instance, struct pt_regs *regs) } } if (found) { - dbell->dinb(port, DBELL_SID(dmsg), DBELL_TID(dmsg), + dbell->dinb(port, dbell->dev_id, DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); } else { pr_debug diff --git a/drivers/rapidio/rio-sysfs.c b/drivers/rapidio/rio-sysfs.c index 73218a37506..30a11436e24 100644 --- a/drivers/rapidio/rio-sysfs.c +++ b/drivers/rapidio/rio-sysfs.c @@ -21,7 +21,7 @@ /* Sysfs support */ #define rio_config_attr(field, format_string) \ static ssize_t \ - field##_show(struct device *dev, char *buf) \ +field##_show(struct device *dev, struct device_attribute *attr, char *buf) \ { \ struct rio_dev *rdev = to_rio_dev(dev); \ \ @@ -35,7 +35,7 @@ rio_config_attr(asm_did, "0x%04x\n"); rio_config_attr(asm_vid, "0x%04x\n"); rio_config_attr(asm_rev, "0x%04x\n"); -static ssize_t routes_show(struct device *dev, char *buf) +static ssize_t routes_show(struct device *dev, struct device_attribute *attr, char *buf) { struct rio_dev *rdev = to_rio_dev(dev); char *str = buf; diff --git a/drivers/rapidio/rio.c b/drivers/rapidio/rio.c index adc299e2b07..3ca1011ceaa 100644 --- a/drivers/rapidio/rio.c +++ b/drivers/rapidio/rio.c @@ -48,6 +48,7 @@ u16 rio_local_get_device_id(struct rio_mport *port) /** * rio_request_inb_mbox - request inbound mailbox service * @mport: RIO master port from which to allocate the mailbox resource + * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox number to claim * @entries: Number of entries in inbound mailbox queue * @minb: Callback to execute when inbound message is received @@ -56,9 +57,10 @@ u16 rio_local_get_device_id(struct rio_mport *port) * a callback function to the resource. Returns %0 on success. */ int rio_request_inb_mbox(struct rio_mport *mport, + void *dev_id, int mbox, int entries, - void (*minb) (struct rio_mport * mport, int mbox, + void (*minb) (struct rio_mport * mport, void *dev_id, int mbox, int slot)) { int rc = 0; @@ -81,7 +83,7 @@ int rio_request_inb_mbox(struct rio_mport *mport, /* Hook the inbound message callback */ mport->inb_msg[mbox].mcback = minb; - rc = rio_open_inb_mbox(mport, mbox, entries); + rc = rio_open_inb_mbox(mport, dev_id, mbox, entries); } else rc = -ENOMEM; @@ -108,6 +110,7 @@ int rio_release_inb_mbox(struct rio_mport *mport, int mbox) /** * rio_request_outb_mbox - request outbound mailbox service * @mport: RIO master port from which to allocate the mailbox resource + * @dev_id: Device specific pointer to pass on event * @mbox: Mailbox number to claim * @entries: Number of entries in outbound mailbox queue * @moutb: Callback to execute when outbound message is sent @@ -116,10 +119,10 @@ int rio_release_inb_mbox(struct rio_mport *mport, int mbox) * a callback function to the resource. Returns 0 on success. */ int rio_request_outb_mbox(struct rio_mport *mport, + void *dev_id, int mbox, int entries, - void (*moutb) (struct rio_mport * mport, int mbox, - int slot)) + void (*moutb) (struct rio_mport * mport, void *dev_id, int mbox, int slot)) { int rc = 0; @@ -141,7 +144,7 @@ int rio_request_outb_mbox(struct rio_mport *mport, /* Hook the inbound message callback */ mport->outb_msg[mbox].mcback = moutb; - rc = rio_open_outb_mbox(mport, mbox, entries); + rc = rio_open_outb_mbox(mport, dev_id, mbox, entries); } else rc = -ENOMEM; @@ -168,6 +171,7 @@ int rio_release_outb_mbox(struct rio_mport *mport, int mbox) /** * rio_setup_inb_dbell - bind inbound doorbell callback * @mport: RIO master port to bind the doorbell callback + * @dev_id: Device specific pointer to pass on event * @res: Doorbell message resource * @dinb: Callback to execute when doorbell is received * @@ -176,8 +180,8 @@ int rio_release_outb_mbox(struct rio_mport *mport, int mbox) * satisfied. */ static int -rio_setup_inb_dbell(struct rio_mport *mport, struct resource *res, - void (*dinb) (struct rio_mport * mport, u16 src, u16 dst, +rio_setup_inb_dbell(struct rio_mport *mport, void *dev_id, struct resource *res, + void (*dinb) (struct rio_mport * mport, void *dev_id, u16 src, u16 dst, u16 info)) { int rc = 0; @@ -190,6 +194,7 @@ rio_setup_inb_dbell(struct rio_mport *mport, struct resource *res, dbell->res = res; dbell->dinb = dinb; + dbell->dev_id = dev_id; list_add_tail(&dbell->node, &mport->dbells); @@ -200,6 +205,7 @@ rio_setup_inb_dbell(struct rio_mport *mport, struct resource *res, /** * rio_request_inb_dbell - request inbound doorbell message service * @mport: RIO master port from which to allocate the doorbell resource + * @dev_id: Device specific pointer to pass on event * @start: Doorbell info range start * @end: Doorbell info range end * @dinb: Callback to execute when doorbell is received @@ -209,9 +215,10 @@ rio_setup_inb_dbell(struct rio_mport *mport, struct resource *res, * has been satisfied. */ int rio_request_inb_dbell(struct rio_mport *mport, + void *dev_id, u16 start, u16 end, - void (*dinb) (struct rio_mport * mport, u16 src, + void (*dinb) (struct rio_mport * mport, void *dev_id, u16 src, u16 dst, u16 info)) { int rc = 0; @@ -230,7 +237,7 @@ int rio_request_inb_dbell(struct rio_mport *mport, } /* Hook the doorbell callback */ - rc = rio_setup_inb_dbell(mport, res, dinb); + rc = rio_setup_inb_dbell(mport, dev_id, res, dinb); } else rc = -ENOMEM; diff --git a/include/linux/rio.h b/include/linux/rio.h index 5c29f2f477c..c7e907faae9 100644 --- a/include/linux/rio.h +++ b/include/linux/rio.h @@ -132,7 +132,7 @@ struct rio_dev { */ struct rio_msg { struct resource *res; - void (*mcback) (struct rio_mport * mport, int mbox, int slot); + void (*mcback) (struct rio_mport * mport, void *dev_id, int mbox, int slot); }; /** @@ -140,11 +140,13 @@ struct rio_msg { * @node: Node in list of doorbell events * @res: Doorbell resource * @dinb: Doorbell event callback + * @dev_id: Device specific pointer to pass on event */ struct rio_dbell { struct list_head node; struct resource *res; - void (*dinb) (struct rio_mport * mport, u16 src, u16 dst, u16 info); + void (*dinb) (struct rio_mport *mport, void *dev_id, u16 src, u16 dst, u16 info); + void *dev_id; }; /** @@ -314,9 +316,9 @@ extern int rio_hw_add_outb_message(struct rio_mport *, struct rio_dev *, int, void *, size_t); extern int rio_hw_add_inb_buffer(struct rio_mport *, int, void *); extern void *rio_hw_get_inb_message(struct rio_mport *, int); -extern int rio_open_inb_mbox(struct rio_mport *, int, int); +extern int rio_open_inb_mbox(struct rio_mport *, void *, int, int); extern void rio_close_inb_mbox(struct rio_mport *, int); -extern int rio_open_outb_mbox(struct rio_mport *, int, int); +extern int rio_open_outb_mbox(struct rio_mport *, void *, int, int); extern void rio_close_outb_mbox(struct rio_mport *, int); #endif /* __KERNEL__ */ diff --git a/include/linux/rio_drv.h b/include/linux/rio_drv.h index 7483dfc0dfa..3bd7cce19e2 100644 --- a/include/linux/rio_drv.h +++ b/include/linux/rio_drv.h @@ -348,8 +348,8 @@ static inline void rio_init_dbell_res(struct resource *res, u16 start, u16 end) .asm_did = RIO_ANY_ID, .asm_vid = RIO_ANY_ID /* Mailbox management */ -extern int rio_request_outb_mbox(struct rio_mport *, int, int, - void (*)(struct rio_mport *, int, int)); +extern int rio_request_outb_mbox(struct rio_mport *, void *, int, int, + void (*)(struct rio_mport *, void *,int, int)); extern int rio_release_outb_mbox(struct rio_mport *, int); /** @@ -370,8 +370,8 @@ static inline int rio_add_outb_message(struct rio_mport *mport, return rio_hw_add_outb_message(mport, rdev, mbox, buffer, len); } -extern int rio_request_inb_mbox(struct rio_mport *, int, int, - void (*)(struct rio_mport *, int, int)); +extern int rio_request_inb_mbox(struct rio_mport *, void *, int, int, + void (*)(struct rio_mport *, void *, int, int)); extern int rio_release_inb_mbox(struct rio_mport *, int); /** @@ -403,8 +403,8 @@ static inline void *rio_get_inb_message(struct rio_mport *mport, int mbox) } /* Doorbell management */ -extern int rio_request_inb_dbell(struct rio_mport *, u16, u16, - void (*)(struct rio_mport *, u16, u16, u16)); +extern int rio_request_inb_dbell(struct rio_mport *, void *, u16, u16, + void (*)(struct rio_mport *, void *, u16, u16, u16)); extern int rio_release_inb_dbell(struct rio_mport *, u16, u16); extern struct resource *rio_request_outb_dbell(struct rio_dev *, u16, u16); extern int rio_release_outb_dbell(struct rio_dev *, struct resource *); -- cgit v1.2.3 From 8f09f4a25a927080e1fa1331735c3d1b5664866b Mon Sep 17 00:00:00 2001 From: Nishanth Aravamudan Date: Mon, 7 Nov 2005 01:01:13 -0800 Subject: [PATCH] ppc: fix-up schedule_timeout() usage Use schedule_timeout_interruptible() instead of set_current_state()/schedule_timeout() to reduce kernel size. Also use human-time conversion functions instead of hard-coded HZ division to avoid rounding errors. Signed-off-by: Nishanth Aravamudan Cc: Benjamin Herrenschmidt Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/ppc/4xx_io/serial_sicc.c | 17 +++++++---------- arch/ppc/8260_io/fcc_enet.c | 3 +-- 2 files changed, 8 insertions(+), 12 deletions(-) (limited to 'arch/ppc') diff --git a/arch/ppc/4xx_io/serial_sicc.c b/arch/ppc/4xx_io/serial_sicc.c index e95c48d5757..84d96b857e4 100644 --- a/arch/ppc/4xx_io/serial_sicc.c +++ b/arch/ppc/4xx_io/serial_sicc.c @@ -1145,8 +1145,8 @@ static int set_serial_info(struct SICC_info *info, info->flags = ((state->flags & ~ASYNC_INTERNAL_FLAGS) | (info->flags & ASYNC_INTERNAL_FLAGS)); state->custom_divisor = new_serial.custom_divisor; - state->close_delay = new_serial.close_delay * HZ / 100; - state->closing_wait = new_serial.closing_wait * HZ / 100; + state->close_delay = msecs_to_jiffies(10 * new_serial.close_delay); + state->closing_wait = msecs_to_jiffies(10 * new_serial.closing_wait); info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0; port->fifosize = new_serial.xmit_fifo_size; @@ -1465,10 +1465,8 @@ static void siccuart_close(struct tty_struct *tty, struct file *filp) info->event = 0; info->tty = NULL; if (info->blocked_open) { - if (info->state->close_delay) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(info->state->close_delay); - } + if (info->state->close_delay) + schedule_timeout_interruptible(info->state->close_delay); wake_up_interruptible(&info->open_wait); } info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING); @@ -1496,7 +1494,7 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout) * Note: we have to use pretty tight timings here to satisfy * the NIST-PCTS. */ - char_time = (info->timeout - HZ/50) / info->port->fifosize; + char_time = (info->timeout - msecs_to_jiffies(20)) / info->port->fifosize; char_time = char_time / 5; if (char_time == 0) char_time = 1; @@ -1521,8 +1519,7 @@ static void siccuart_wait_until_sent(struct tty_struct *tty, int timeout) tty->index, jiffies, expire, char_time); while ((readb(info->port->uart_base + BL_SICC_LSR) & _LSR_TX_ALL) != _LSR_TX_ALL) { - set_current_state(TASK_INTERRUPTIBLE); - schedule_timeout(char_time); + schedule_timeout_interruptible(char_time); if (signal_pending(current)) break; if (timeout && time_after(jiffies, expire)) @@ -1773,7 +1770,7 @@ int __init siccuart_init(void) for (i = 0; i < SERIAL_SICC_NR; i++) { struct SICC_state *state = sicc_state + i; state->line = i; - state->close_delay = 5 * HZ / 10; + state->close_delay = msecs_to_jiffies(500); state->closing_wait = 30 * HZ; spin_lock_init(&state->sicc_lock); } diff --git a/arch/ppc/8260_io/fcc_enet.c b/arch/ppc/8260_io/fcc_enet.c index 2086c6ad114..4edeede9ccf 100644 --- a/arch/ppc/8260_io/fcc_enet.c +++ b/arch/ppc/8260_io/fcc_enet.c @@ -1309,8 +1309,7 @@ static void mii_dm9161_wait(uint mii_reg, struct net_device *dev) /* Davicom takes a bit to come up after a reset, * so wait here for a bit */ - set_current_state(TASK_UNINTERRUPTIBLE); - schedule_timeout(timeout); + schedule_timeout_uninterruptible(timeout); } static phy_info_t phy_info_dm9161 = { -- cgit v1.2.3 From b2325fe1b7e5654fac9e9419423aa2c58a3dbd83 Mon Sep 17 00:00:00 2001 From: Jesper Juhl Date: Mon, 7 Nov 2005 01:01:35 -0800 Subject: [PATCH] kfree cleanup: arch This is the arch/ part of the big kfree cleanup patch. Remove pointless checks for NULL prior to calling kfree() in arch/. Signed-off-by: Jesper Juhl Acked-by: Grant Grundler Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds --- arch/arm/mach-integrator/impd1.c | 3 +-- arch/cris/arch-v32/drivers/cryptocop.c | 14 +++++++------- arch/ia64/kernel/perfmon.c | 2 +- arch/powerpc/platforms/pseries/reconfig.c | 6 ++---- arch/ppc/8xx_io/cs4218_tdm.c | 3 +-- arch/ppc/syslib/prom.c | 6 ++---- arch/ppc64/kernel/lparcfg.c | 4 +--- arch/ppc64/kernel/scanlog.c | 3 +-- arch/s390/mm/extmem.c | 8 ++++---- arch/sparc64/kernel/us2e_cpufreq.c | 7 ++----- arch/sparc64/kernel/us3_cpufreq.c | 7 ++----- arch/um/kernel/sigio_user.c | 2 +- 12 files changed, 25 insertions(+), 40 deletions(-) (limited to 'arch/ppc') diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c index a1b153d1626..a4bafee77a0 100644 --- a/arch/arm/mach-integrator/impd1.c +++ b/arch/arm/mach-integrator/impd1.c @@ -420,8 +420,7 @@ static int impd1_probe(struct lm_device *dev) free_impd1: if (impd1 && impd1->base) iounmap(impd1->base); - if (impd1) - kfree(impd1); + kfree(impd1); release_lm: release_mem_region(dev->resource.start, SZ_4K); return ret; diff --git a/arch/cris/arch-v32/drivers/cryptocop.c b/arch/cris/arch-v32/drivers/cryptocop.c index ca72076c630..501fa52d8d3 100644 --- a/arch/cris/arch-v32/drivers/cryptocop.c +++ b/arch/cris/arch-v32/drivers/cryptocop.c @@ -277,7 +277,7 @@ struct file_operations cryptocop_fops = { static void free_cdesc(struct cryptocop_dma_desc *cdesc) { DEBUG(printk("free_cdesc: cdesc 0x%p, from_pool=%d\n", cdesc, cdesc->from_pool)); - if (cdesc->free_buf) kfree(cdesc->free_buf); + kfree(cdesc->free_buf); if (cdesc->from_pool) { unsigned long int flags; @@ -2950,15 +2950,15 @@ static int cryptocop_ioctl_process(struct inode *inode, struct file *filp, unsig put_page(outpages[i]); } - if (digest_result) kfree(digest_result); - if (inpages) kfree(inpages); - if (outpages) kfree(outpages); + kfree(digest_result); + kfree(inpages); + kfree(outpages); if (cop){ - if (cop->tfrm_op.indata) kfree(cop->tfrm_op.indata); - if (cop->tfrm_op.outdata) kfree(cop->tfrm_op.outdata); + kfree(cop->tfrm_op.indata); + kfree(cop->tfrm_op.outdata); kfree(cop); } - if (jc) kfree(jc); + kfree(jc); DEBUG(print_lock_status()); diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c index f7dfc107cb7..410d4804fa6 100644 --- a/arch/ia64/kernel/perfmon.c +++ b/arch/ia64/kernel/perfmon.c @@ -4940,7 +4940,7 @@ abort_locked: if (call_made && PFM_CMD_RW_ARG(cmd) && copy_to_user(arg, args_k, base_sz*count)) ret = -EFAULT; error_args: - if (args_k) kfree(args_k); + kfree(args_k); DPRINT(("cmd=%s ret=%ld\n", PFM_CMD_NAME(cmd), ret)); diff --git a/arch/powerpc/platforms/pseries/reconfig.c b/arch/powerpc/platforms/pseries/reconfig.c index 58c61219d08..d7d40033945 100644 --- a/arch/powerpc/platforms/pseries/reconfig.c +++ b/arch/powerpc/platforms/pseries/reconfig.c @@ -286,10 +286,8 @@ static struct property *new_property(const char *name, const int length, return new; cleanup: - if (new->name) - kfree(new->name); - if (new->value) - kfree(new->value); + kfree(new->name); + kfree(new->value); kfree(new); return NULL; } diff --git a/arch/ppc/8xx_io/cs4218_tdm.c b/arch/ppc/8xx_io/cs4218_tdm.c index 532caa388dc..49eb2a7e65c 100644 --- a/arch/ppc/8xx_io/cs4218_tdm.c +++ b/arch/ppc/8xx_io/cs4218_tdm.c @@ -1013,8 +1013,7 @@ static void CS_IrqCleanup(void) */ cpm_free_handler(CPMVEC_SMC2); - if (beep_buf) - kfree(beep_buf); + kfree(beep_buf); kd_mksound = orig_mksound; } #endif /* MODULE */ diff --git a/arch/ppc/syslib/prom.c b/arch/ppc/syslib/prom.c index 278da6ee62e..1b9aa0d6a92 100644 --- a/arch/ppc/syslib/prom.c +++ b/arch/ppc/syslib/prom.c @@ -1335,10 +1335,8 @@ release_OF_resource(struct device_node* node, int index) if (!res) return -ENODEV; - if (res->name) { - kfree(res->name); - res->name = NULL; - } + kfree(res->name); + res->name = NULL; release_resource(res); kfree(res); diff --git a/arch/ppc64/kernel/lparcfg.c b/arch/ppc64/kernel/lparcfg.c index e86155770bb..3e7b2f28ec8 100644 --- a/arch/ppc64/kernel/lparcfg.c +++ b/arch/ppc64/kernel/lparcfg.c @@ -599,9 +599,7 @@ int __init lparcfg_init(void) void __exit lparcfg_cleanup(void) { if (proc_ppc64_lparcfg) { - if (proc_ppc64_lparcfg->data) { - kfree(proc_ppc64_lparcfg->data); - } + kfree(proc_ppc64_lparcfg->data); remove_proc_entry("lparcfg", proc_ppc64_lparcfg->parent); } } diff --git a/arch/ppc64/kernel/scanlog.c b/arch/ppc64/kernel/scanlog.c index 215bf890030..2edc947f7c4 100644 --- a/arch/ppc64/kernel/scanlog.c +++ b/arch/ppc64/kernel/scanlog.c @@ -225,8 +225,7 @@ int __init scanlog_init(void) void __exit scanlog_cleanup(void) { if (proc_ppc64_scan_log_dump) { - if (proc_ppc64_scan_log_dump->data) - kfree(proc_ppc64_scan_log_dump->data); + kfree(proc_ppc64_scan_log_dump->data); remove_proc_entry("scan-log-dump", proc_ppc64_scan_log_dump->parent); } } diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c index c5348108ca3..506a33b51e4 100644 --- a/arch/s390/mm/extmem.c +++ b/arch/s390/mm/extmem.c @@ -234,8 +234,8 @@ query_segment_type (struct dcss_segment *seg) rc = 0; out_free: - if (qin) kfree(qin); - if (qout) kfree(qout); + kfree(qin); + kfree(qout); return rc; } @@ -394,7 +394,7 @@ __segment_load (char *name, int do_nonshared, unsigned long *addr, unsigned long segtype_string[seg->vm_segtype]); goto out; out_free: - kfree (seg); + kfree(seg); out: return rc; } @@ -505,7 +505,7 @@ segment_modify_shared (char *name, int do_nonshared) list_del(&seg->list); dcss_diag(DCSS_PURGESEG, seg->dcss_name, &dummy, &dummy); - kfree (seg); + kfree(seg); out_unlock: spin_unlock(&dcss_lock); return rc; diff --git a/arch/sparc64/kernel/us2e_cpufreq.c b/arch/sparc64/kernel/us2e_cpufreq.c index 686e526bec0..b35dc8dc995 100644 --- a/arch/sparc64/kernel/us2e_cpufreq.c +++ b/arch/sparc64/kernel/us2e_cpufreq.c @@ -388,10 +388,8 @@ err_out: kfree(driver); cpufreq_us2e_driver = NULL; } - if (us2e_freq_table) { - kfree(us2e_freq_table); - us2e_freq_table = NULL; - } + kfree(us2e_freq_table); + us2e_freq_table = NULL; return ret; } @@ -402,7 +400,6 @@ static void __exit us2e_freq_exit(void) { if (cpufreq_us2e_driver) { cpufreq_unregister_driver(cpufreq_us2e_driver); - kfree(cpufreq_us2e_driver); cpufreq_us2e_driver = NULL; kfree(us2e_freq_table); diff --git a/arch/sparc64/kernel/us3_cpufreq.c b/arch/sparc64/kernel/us3_cpufreq.c index 0340041f614..6d1f9a3c464 100644 --- a/arch/sparc64/kernel/us3_cpufreq.c +++ b/arch/sparc64/kernel/us3_cpufreq.c @@ -249,10 +249,8 @@ err_out: kfree(driver); cpufreq_us3_driver = NULL; } - if (us3_freq_table) { - kfree(us3_freq_table); - us3_freq_table = NULL; - } + kfree(us3_freq_table); + us3_freq_table = NULL; return ret; } @@ -263,7 +261,6 @@ static void __exit us3_freq_exit(void) { if (cpufreq_us3_driver) { cpufreq_unregister_driver(cpufreq_us3_driver); - kfree(cpufreq_us3_driver); cpufreq_us3_driver = NULL; kfree(us3_freq_table); diff --git a/arch/um/kernel/sigio_user.c b/arch/um/kernel/sigio_user.c index 3fbfd956bfe..48b1f644b9a 100644 --- a/arch/um/kernel/sigio_user.c +++ b/arch/um/kernel/sigio_user.c @@ -224,7 +224,7 @@ static int need_poll(int n) next_poll.used = n; return(0); } - if(next_poll.poll != NULL) kfree(next_poll.poll); + kfree(next_poll.poll); next_poll.poll = um_kmalloc_atomic(n * sizeof(struct pollfd)); if(next_poll.poll == NULL){ printk("need_poll : failed to allocate new pollfds\n"); -- cgit v1.2.3