From 32020effaf713c0c669864301bcd5dac6b9bb9e0 Mon Sep 17 00:00:00 2001 From: Chris Metcalf <cmetcalf@tilera.com> Date: Fri, 13 Aug 2010 08:32:21 -0400 Subject: arch/tile: Fix a couple of issues with the COMPAT code for TILE-Gx. First, the siginfo preamble wasn't quite right; we need to indicate that we are padding up to 4 ints of preamble for 64-bit code, and then for compat mode we need to pad differently, using only 3 ints. Second, the C ABI requires a save area of two registers, not two pointers, since in compat mode we have 64-bit registers all of which we need to save, even though we only have 32-bit VAs. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> --- arch/tile/include/arch/abi.h | 4 +--- arch/tile/include/asm/siginfo.h | 4 ++++ 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'arch/tile/include') diff --git a/arch/tile/include/arch/abi.h b/arch/tile/include/arch/abi.h index da8df5b9d91..8affc76f771 100644 --- a/arch/tile/include/arch/abi.h +++ b/arch/tile/include/arch/abi.h @@ -59,9 +59,7 @@ * The ABI requires callers to allocate a caller state save area of * this many bytes at the bottom of each stack frame. */ -#ifdef __tile__ -#define C_ABI_SAVE_AREA_SIZE (2 * __SIZEOF_POINTER__) -#endif +#define C_ABI_SAVE_AREA_SIZE (2 * (CHIP_WORD_SIZE() / 8)) /** * The operand to an 'info' opcode directing the backtracer to not diff --git a/arch/tile/include/asm/siginfo.h b/arch/tile/include/asm/siginfo.h index 0c12d1b9ddf..56d661bb010 100644 --- a/arch/tile/include/asm/siginfo.h +++ b/arch/tile/include/asm/siginfo.h @@ -17,6 +17,10 @@ #define __ARCH_SI_TRAPNO +#ifdef __LP64__ +# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int)) +#endif + #include <asm-generic/siginfo.h> /* -- cgit v1.2.3