Merge master.kernel.org:/home/rmk/linux-2.6-arm

* master.kernel.org:/home/rmk/linux-2.6-arm: (28 commits)
  [ARM] 5562/2: at91: add gpio button support for at91sam9g20ek
  [ARM] 5563/1: at91: at91sam9rlek lcd interface correction
  [ARM] 5565/2: Use PAGE_SIZE and RO_DATA() in link script
  [ARM] 5560/1: Avoid buffer overrun in case of an invalid IRQ
  [ARM] GTA02: build fixes (s3c2410_nand_set usage)
  [ARM] MINI2440: Add missing flash_bbt flat to NAND
  [ARM] s3c2410_defconfig: add MINI2440 machine to build
  [ARM] S3C: Fix S3C24XX build to not include s3c64xx IIS devices
  [ARM] S3C24XX: Fix missing s3c_iis_device.
  [ARM] MINI2440: remove duplicated #include
  [ARM] S3C24XX: Fix spi-bus configuration build errors
  OMAP: Fix IOMEM macro for assembly
  [ARM] S3C: Remove unused CONFIG_DEBUG_S3C_PORT
  [ARM] S3C24XX: Fix use of CONFIG_S3C24XX_PWM
  OMAP2/3: Initialize gpio debounce register
  OMAP: IOMMU: function flush_iotlb_page is not flushing correct entry
  OMAP3: RX51: Use OneNAND sync read / write
  OMAP2/3: gpmc-onenand: correct use of async timings
  OMAP3: DMA: Enable idlemodes for DMA OCP
  OMAP3: SRAM size fix for HS/EMU devices
  ...

1 files changed, 19 insertions, 2 deletions

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 2fd22f9c5f0..54fec53a48e 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -31,6 +31,8 @@ static struct platform_device gpmc_onenand_device = {
 static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 {
 	struct gpmc_timings t;
+	u32 reg;
+	int err;
 
 	const int t_cer = 15;
 	const int t_avdp = 12;
@@ -43,6 +45,11 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 	const int t_wpl = 40;
 	const int t_wph = 30;
 
+	/* Ensure sync read and sync write are disabled */
+	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+
 	memset(&t, 0, sizeof(t));
 	t.sync_clk = 0;
 	t.cs_on = 0;
@@ -74,7 +81,16 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 			  GPMC_CONFIG1_DEVICESIZE_16 |
 			  GPMC_CONFIG1_MUXADDDATA);
 
-	return gpmc_cs_set_timings(cs, &t);
+	err = gpmc_cs_set_timings(cs, &t);
+	if (err)
+		return err;
+
+	/* Ensure sync read and sync write are disabled */
+	reg = readw(onenand_base + ONENAND_REG_SYS_CFG1);
+	reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE;
+	writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
+
+	return 0;
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
@@ -124,7 +140,8 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
 	} else if (cfg->flags & ONENAND_SYNC_READWRITE) {
 		sync_read = 1;
 		sync_write = 1;
-	}
+	} else
+		return omap2_onenand_set_async_mode(cs, onenand_base);
 
 	if (!freq) {
 		/* Very first call freq is not known */