ux500: pm: update

commit 1d3e28fa4e85d54434614575f37a4171e32dfe0c
Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Date:   Tue Aug 23 12:28:26 2011 +0200

    [Android]: pm: usecase: limit cpu frequency to 400MHz during voice-call

    ST Ericsson ID: 357594

commit 70f52392190a111758836d5fca7fb533ad8b4453
Author: Rickard Andersson <rickard.andersson@stericsson.com>
Date:   Tue Aug 23 11:05:58 2011 +0200

    ux500: cpuidle: Correct PRCMU error messages

    Show correct error messages when PRCMU requested
    sleep fails.

    ST-Ericsson ID: -

commit 912e987c1e46815c8cf128bce3d7077d3b05e7d6
Author: Rickard Andersson <rickard.andersson@stericsson.com>
Date:   Tue Aug 23 11:00:01 2011 +0200

    ux500: cpuidle: Optimize stack sizes

    Optimze the stack sizes for arm registers and
    CP15 registers

    ST-Ericsson ID: -

commit df0c08abadbdbe19c8c00ca09c3197f3fb0ead29
Author: Rickard Andersson <rickard.andersson@stericsson.com>
Date:   Mon Aug 22 11:19:13 2011 +0200

    ux500: cpuidle: GIC freeze delay optimized

    GIC freeze delay was previously unnecessary long.

    ST-Ericsson ID: -

commit a28fec98e99d5115b62d3d704452f427ca2a20ac
Author: Rajagopala V <rajagopala.v@stericsson.com>
Date:   Wed Aug 24 13:16:39 2011 +0530

    u5500: cpuidle: fix coverity warning

    check for clockevents_program_event return value in
    cpuidle driver during wakeup

    ST-Ericsson ID: ER356883

commit b716ed3140664c6b4b80381b18945032b792b853
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Fri Aug 19 14:32:29 2011 +0530

    u5500: enable PRCMU QoS and debugging

    Dummy implementations are provided to get it to build.

    ST-Ericsson ID: 348762

commit 34cd29c2f8cd1ce8fa51be6d33624b441416d478
Author: om prakash <omprakash.pal@stericsson.com>
Date:   Tue Aug 23 14:08:52 2011 +0530

    cpuidle:Removed the CHECKED_RETURN error

    Removed the CHECKED_RETURN coverity error in cpuidle.

    ST-Ericsson ID: 354434

commit d9d500b6742ff1fcb12747cb55d7f26c89ef5c96
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Mon Aug 22 10:23:36 2011 +0530

    u5500: support cpufreq only on v2

    Support cpufreq only on 5500v2+ only, since that is where
    the other power management features will be enabled.

    ST-Ericsson ID: 355981

commit 74cf0e658bb9abe240d04427d9043f145dd0505b
Author: Hemanth Puranik <hemanth.puranik@stericsson.com>
Date:   Wed Aug 3 10:29:10 2011 +0530

    U5500: Print PRCMU firware version

    ST-Ericsson ID: WP332193

commit bb04cadb6948a3a68f409fa7828457ce64540172
Author: Vijaya Kumar Kilari <vijay.kilari@stericsson.com>
Date:   Thu Aug 11 11:49:27 2011 +0530

    U5500: Add MSP1 and Cable detect clock support

    MSP1 and CD clocks are managed by PRCMU FW
    so special handling for these clocks are required

    ST-Ericsson ID: 332193

commit 0d9b20560a729b4674d9f55c77572db04272edbd
Author: Rajagopala V <rajagopala.v@stericsson.com>
Date:   Fri Aug 5 16:52:41 2011 +0530

    u5500: prcmu: add irqs for db5500 temperature sensor

    add irqs to support db5500 temp sensor high and low
    interrupts so as to clearly distinguish whether sensor
    temperature has crossed min/max values

    ST-Ericsson ID: WP257616

commit 63877225cb09c38d0fbea2dcf01eb6670eb05549
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Wed Jul 13 09:01:22 2011 +0200

    ARM: u8500: pm: Do not touch TPIU registers if JTAG disabled

    If JTAG is disabled, the Linux cannot touch the TPIU registers.

    ST-Ericsson ID: 349265

commit 9fcee5876ff138e85356b63d392b2a050a68601e
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Mon Jul 11 15:27:49 2011 +0200

    ARM: ux500: prcmu-debug: Add ARM opp to debugfs

    Add arm opp to debugfs interface, plus some code clean-up/simplification.

    ST-Ericsson ID: -

commit 0e1f18385d2416e03af308cac1e38997f6bbf044
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Thu Jul 14 12:49:30 2011 +0200

    ARM: ux500: context: Do not touch TPIU when not clocked

    ST-Ericsson ID: 352300

commit 0ebdb6b6b2a7f9924bd2785654f0abfb1473dda0
Author: Jayarami Reddy <jayarami.reddy@stericsson.com>
Date:   Thu Jul 14 14:39:07 2011 +0530

    u5500: fix to boot the kernel in DB5500

commit a20f6a9088ac5d34634cd26207dd5a072f04c37b
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Mon Jul 11 15:26:40 2011 +0200

    ARM: ux500: prcmu-qos: Add ARM OPP qos

    Make it possible to request lowest ARM OPP. Must
    be bound to cpufreq to actually do something.

    ST-Ericsson ID: -

commit be6842df3ee21a9aa00216c84e93a643b4ddeabe
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Wed Jul 13 09:00:30 2011 +0200

    ARM: ux500: Read product settings at boot

    ST-Ericsson ID: 349265

commit 94843c6131bac39aa8e7d0ec4c9c2b34e2819c92
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Wed Jul 13 08:56:38 2011 +0200

    drivers: tee: Update with product id configuration

    Add structs and defines needed to detect product settings.

    ST-Ericsson ID: 349265

commit 4c70d615b782965c064b3f97963eff5a290acf68
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Wed Jul 6 08:26:41 2011 +0200

    ARM: ux500: prcmu-wdog: Remove check for fw bug

    In prcmu fw version 3.4.4 the issue with longer
    intervalls than 131 s was fixed.

    ST-Ericsson ID: -

commit f6ccbf262ddebe39584b4a4c01cfa16af1fbfac6
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Tue Jul 12 08:53:42 2011 +0200

    ARM: ux500: cpuidle: Remove duplicated ApIdle state

    The ARM PLL is handled automatic by the prcmu fw and
    cpuidle cannot affect it. Remove duplicated ApIdle
    state that does the same as the other ApIdle state.

    ST-Ericsson ID: -

commit bdf3c3dd8c22ffe0fbd8c674e8e6bdab83a5ec01
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Fri Jul 8 14:33:23 2011 +0530

    ux500: support ApDeepSleep on 5500

    ST-Ericsson ID: 332193

commit 5326d7744cd226e67253774f30a2bb57c9b2badc
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Mon Jul 11 11:27:45 2011 +0530

    u5500: fix prcmu_get_arm_opp()

    prcmu_set_arm_opp() maps between logical ARM OPP values and
    PRCMU firmware values, so prcmu_get_arm_opp() should do it too.

    ST-Ericsson ID: 332226

commit 6422856927e1230197ae674795eff6538df885e5
Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Date:   Thu Jul 7 08:33:59 2011 +0200

    ARM: u8500: prcmu-dbg: display AVS settings

    Add debugfs node showing AVS settings.

    root@ME:/ cat /debugfs/prcmu/avs
    VBB_RET      : 0x 0
    VBB_MAX_OPP  : 0xdb
    VBB_100_OPP  : 0xdb
    VBB_50_OPP   : 0xdb
    VARM_MAX_OPP : 0x2f
    VARM_100_OPP : 0x2e
    VARM_50_OPP  : 0x1d
    VARM_RET     : 0x 0
    VAPE_100_OPP : 0x2a
    VAPE_50_OPP  : 0x1a
    VMOD_100_OPP : 0x29
    VMOD_50_OPP  : 0x1a
    VSAFE        : 0x29

    ST-Ericsson ID: -

commit 3184873f10bff0c7c54db75d9c2694e21ebc40b0
Author: Pawel Szyszuk <pawel.szyszuk@stericsson.com>
Date:   Wed Jun 22 16:03:29 2011 +0200

    ARM: U5500: PRCMU CLKOUTx configuration API

    U5500 API for setting the programmable CLKOUTx source and divisor.
    New API used for setting the sources of camera clocks.

    ST-Ericsson ID: -

commit 98e9cfc32a25f6cf3b5d4c3456bb6ff6a34ff9cb
Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
Date:   Thu Jun 23 16:07:48 2011 +0200

    [ANDROID]: pm: usecase: add sysfs interface to disable the governor

    Move all the code to control the state of the governor in a separate function.

    ST-Ericsson ID: CR339643

commit 6e9ab8ab3013d0b372a51d94d617d24fd8b38664
Author: Rickard Andersson <rickard.andersson@stericsson.com>
Date:   Tue Jun 7 13:04:08 2011 +0200

    ARM: ux500: pm: Turn off unnecessary GIC IRQs in deep sleep

    In the sleep state ApDeepSleep turn off all IRQs in the
    GIC except for the PRCMU IRQs

    ST-Ericsson ID: ER338876

commit ba5f28731b27386cb90cf87c4e7b1910e09474a9
Author: Rickard Andersson <rickard.andersson@stericsson.com>
Date:   Fri May 27 08:56:47 2011 +0200

    ARM: ux500: pm: Deepsleep bugfix and optimization

    Fixing deep sleep sync problems. Also cache clean and saves to
    backup RAM is now only done when really needed.

    ST-Ericsson ID: ER338876

commit 0415c755958de0d613a9bd52f73b820cb3a2b916
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Tue Jun 28 18:18:36 2011 +0530

    u5500: handle SDMMC0 clock change on DB5500v2

    On DB5500v2, SDMMC0 is parented to SPARE1CLK instead of
    SDMMCCLK.

    Also, correct the PRCM_IRDACLK_MGT register address which is
    wrong even for v1.

    ST-Ericsson ID: 349062

commit 2036360d62f3c3f0cd722d751ba90a8739034c0f
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Mon Jun 27 20:25:06 2011 +0530

    u5500: cpufreq: DB5500v2 support

    ST-Ericsson ID: 349062

commit 190b11834463e835de2d792116dfd8673d775752
Author: Rabin Vincent <rabin.vincent@stericsson.com>
Date:   Wed Jun 22 07:45:00 2011 +0530

    u5500: allow SUSPEND_STANDBY and CPUIDLE to be enabled

    ST-Ericsson ID: 332226

commit 7c4906d6ee888df46baa64b690dfdfaf44502d86
Author: Pawel Szyszuk <pawel.szyszuk@stericsson.com>
Date:   Mon Jun 20 15:28:34 2011 +0200

    ARM: u5500: PRCMU reset API

    Added API for rebooting the board and for getting the last reboot code.

    ST-Ericsson ID: 341245

Change-Id: Ibbcd9e3528cd605c724b9c2c88ae3b41a27f2f1c

7 files changed, 611 insertions, 300 deletions

diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db5500.h b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
new file mode 100644
index 00000000000..ae76fef0e44
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db5500.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U5500 PRCMU API.
+ */
+#ifndef __MACH_PRCMU_U5500_H
+#define __MACH_PRCMU_U5500_H
+
+#ifdef CONFIG_U5500_PRCMU
+
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+int db5500_prcmu_request_clock(u8 clock, bool enable);
+
+int prcmu_resetout(u8 resoutn, u8 state);
+
+unsigned int prcmu_get_ddr_freq(void);
+
+#else /* !CONFIG_U5500_PRCMU */
+
+static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+	return -ENOSYS;
+}
+
+static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+	return -ENOSYS;
+}
+
+static inline int prcmu_resetout(u8 resoutn, u8 state)
+{
+	return 0;
+}
+
+static inline unsigned int prcmu_get_ddr_freq(void)
+{
+	return 0;
+}
+
+#endif /* CONFIG_U5500_PRCMU */
+
+#endif /* __MACH_PRCMU_U5500_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-db8500.h b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
new file mode 100644
index 00000000000..572d68b7213
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-db8500.h
@@ -0,0 +1,309 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U8500 specific PRCMU API.
+ */
+#ifndef __MACH_PRCMU_DB8500_H
+#define __MACH_PRCMU_DB8500_H
+
+/*
+ * Definitions for autonomous power management configuration.
+ */
+
+#define PRCMU_AUTO_PM_OFF 0
+#define PRCMU_AUTO_PM_ON 1
+
+#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
+#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
+
+enum prcmu_auto_pm_policy {
+	PRCMU_AUTO_PM_POLICY_NO_CHANGE,
+	PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
+	PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
+};
+
+/**
+ * struct prcmu_auto_pm_config - Autonomous power management configuration.
+ * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sia_power_on:       SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sia_policy:         SIA power policy. (enum prcmu_auto_pm_policy)
+ * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sva_power_on:       SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sva_policy:         SVA power policy. (enum prcmu_auto_pm_policy)
+ */
+struct prcmu_auto_pm_config {
+	u8 sia_auto_pm_enable;
+	u8 sia_power_on;
+	u8 sia_policy;
+	u8 sva_auto_pm_enable;
+	u8 sva_power_on;
+	u8 sva_policy;
+};
+
+/**
+ * enum hw_acc_dev - enum for hw accelerators
+ * @HW_ACC_SVAMMDSP: for SVAMMDSP
+ * @HW_ACC_SVAPIPE:  for SVAPIPE
+ * @HW_ACC_SIAMMDSP: for SIAMMDSP
+ * @HW_ACC_SIAPIPE: for SIAPIPE
+ * @HW_ACC_SGA: for SGA
+ * @HW_ACC_B2R2: for B2R2
+ * @HW_ACC_MCDE: for MCDE
+ * @HW_ACC_ESRAM1: for ESRAM1
+ * @HW_ACC_ESRAM2: for ESRAM2
+ * @HW_ACC_ESRAM3: for ESRAM3
+ * @HW_ACC_ESRAM4: for ESRAM4
+ * @NUM_HW_ACC: number of hardware accelerators
+ *
+ * Different hw accelerators which can be turned ON/
+ * OFF or put into retention (MMDSPs and ESRAMs).
+ * Used with EPOD API.
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_dev{
+	HW_ACC_SVAMMDSP,
+	HW_ACC_SVAPIPE,
+	HW_ACC_SIAMMDSP,
+	HW_ACC_SIAPIPE,
+	HW_ACC_SGA,
+	HW_ACC_B2R2,
+	HW_ACC_MCDE,
+	HW_ACC_ESRAM1,
+	HW_ACC_ESRAM2,
+	HW_ACC_ESRAM3,
+	HW_ACC_ESRAM4,
+	NUM_HW_ACC
+};
+
+/**
+ * enum hw_acc_state - State definition for hardware accelerator
+ * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * @HW_OFF: The hardware accelerator must be switched off
+ * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ *               internal RAM in retention
+ * @HW_ON: The hwa hardware accelerator hwa must be switched on
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_state {
+	HW_NO_CHANGE = 0x00,
+	HW_OFF = 0x01,
+	HW_OFF_RAMRET = 0x02,
+	HW_ON = 0x04
+};
+
+/**
+ * enum romcode_write - Romcode message written by A9 AND read by XP70
+ * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ *                 romcode. The xp70 will go into self-reset
+ */
+enum romcode_write {
+	RDY_2_DS = 0x09,
+	RDY_2_XP70_RST = 0x10
+};
+
+/**
+ * enum romcode_read - Romcode message written by XP70 and read by A9
+ * @INIT: Init value when romcode field is not used
+ * @FS_2_DS: Value set when power state is going from ApExecute to
+ *          ApDeepSleep
+ * @END_DS: Value set when ApDeepSleep power state is reached coming from
+ *         ApExecute state
+ * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ *           ApExecute
+ * @END_FS: Value set when ApExecute power state is reached coming from
+ *         ApDeepSleep state
+ * @SWR: Value set when power state is going to ApReset
+ * @END_SWR: Value set when the xp70 finished executing ApReset actions and
+ *          waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read {
+	INIT = 0x00,
+	FS_2_DS = 0x0A,
+	END_DS = 0x0B,
+	DS_TO_FS = 0x0C,
+	END_FS = 0x0D,
+	SWR = 0x0E,
+	END_SWR = 0x0F
+};
+
+/**
+ * enum ap_pwrst - current power states defined in PRCMU firmware
+ * @NO_PWRST: Current power state init
+ * @AP_BOOT: Current power state is apBoot
+ * @AP_EXECUTE: Current power state is apExecute
+ * @AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * @AP_SLEEP: Current power state is apSleep
+ * @AP_IDLE: Current power state is apIdle
+ * @AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst {
+	NO_PWRST = 0x00,
+	AP_BOOT = 0x01,
+	AP_EXECUTE = 0x02,
+	AP_DEEP_SLEEP = 0x03,
+	AP_SLEEP = 0x04,
+	AP_IDLE = 0x05,
+	AP_RESET = 0x06
+};
+
+#ifdef CONFIG_U8500_PRCMU
+
+bool prcmu_is_u8400(void);
+
+int prcmu_request_ape_opp_100_voltage(bool enable);
+
+int prcmu_release_usb_wakeup_state(void);
+
+int prcmu_set_clock_divider(u8 clock, u8 divider);
+
+void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+	struct prcmu_auto_pm_config *idle);
+bool prcmu_is_auto_pm_enabled(void);
+
+/* NOTE! Use regulator framework instead */
+int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
+
+/* TODO: Check if anyone is using these. */
+int prcmu_set_rc_a2p(enum romcode_write);
+enum romcode_read prcmu_get_rc_p2a(void);
+enum ap_pwrst prcmu_get_xp70_current_state(void);
+
+/* TODO: Common API with DB5500? */
+bool prcmu_has_arm_maxopp(void);
+int prcmu_config_hotdog(u8 threshold);
+int prcmu_config_hotmon(u8 low, u8 high);
+int prcmu_start_temp_sense(u16 cycles32k);
+int prcmu_stop_temp_sense(void);
+void prcmu_enable_spi2(void);
+void prcmu_disable_spi2(void);
+
+int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
+int prcmu_enable_a9wdog(u8 id);
+int prcmu_disable_a9wdog(u8 id);
+int prcmu_kick_a9wdog(u8 id);
+int prcmu_load_a9wdog(u8 id, u32 val);
+
+#else /* !CONFIG_U8500_PRCMU */
+
+static inline bool prcmu_is_u8400(void)
+{
+	return false;
+}
+
+static inline int prcmu_request_ape_opp_100_voltage(bool enable)
+{
+	return 0;
+}
+
+static inline int prcmu_release_usb_wakeup_state(void)
+{
+	return 0;
+}
+
+static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
+{
+	return 0;
+}
+
+static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+	struct prcmu_auto_pm_config *idle)
+{
+}
+
+static inline bool prcmu_is_auto_pm_enabled(void)
+{
+	return false;
+}
+
+static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
+{
+	return 0;
+}
+
+static inline int prcmu_set_rc_a2p(enum romcode_write code)
+{
+	return 0;
+}
+
+static inline enum romcode_read prcmu_get_rc_p2a(void)
+{
+	return INIT;
+}
+
+static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
+{
+	return AP_EXECUTE;
+}
+
+static inline bool prcmu_has_arm_maxopp(void)
+{
+	return false;
+}
+
+static inline int prcmu_config_hotdog(u8 threshold)
+{
+	return 0;
+}
+
+static inline int prcmu_config_hotmon(u8 low, u8 high)
+{
+	return 0;
+}
+
+static inline int prcmu_start_temp_sense(u16 cycles32k)
+{
+	return 0;
+}
+
+static inline int prcmu_stop_temp_sense(void)
+{
+	return 0;
+}
+
+static inline int prcmu_enable_spi2(void)
+{
+	return 0;
+}
+
+static inline int prcmu_disable_spi2(void)
+{
+	return 0;
+}
+
+static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
+{
+	return 0;
+}
+
+static inline int prcmu_enable_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_disable_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_kick_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_load_a9wdog(u8 id, u32 val)
+{
+	return 0;
+}
+
+#endif /* CONFIG_U8500_PRCMU */
+
+#endif /* __MACH_PRCMU_DB8500_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
new file mode 100644
index 00000000000..7995ed1f77f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-fw-api.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * PRCMU f/w APIs
+ */
+#ifndef __MACH_PRCMU_FW_API_H
+#define __MACH_PRCMU_FW_API_H
+
+#warning <mach/prcmu-fw-api.h> has been replaced by <mach/prcmu.h>
+#include <mach/prcmu.h>
+
+#endif /* __MACH_PRCMU_FW_API_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-qos.h b/arch/arm/mach-ux500/include/mach/prcmu-qos.h
new file mode 100644
index 00000000000..915ed52a593
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-qos.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) ST Ericsson SA 2011
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCMU QoS
+ */
+#ifndef __MACH_PRCMU_QOS_H
+#define __MACH_PRCMU_QOS_H
+
+#include <linux/notifier.h>
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_ARM_OPP 3
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
+#if defined(CONFIG_U8500_PRCMU) || defined(CONFIG_U5500_PRCMU)
+
+unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
+void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
+void prcmu_qos_force_opp(int, s32);
+void prcmu_qos_voice_call_override(bool enable);
+
+#else /* !CONFIG_U8500_PRCMU */
+
+static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
+{
+	return 0;
+}
+
+static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
+
+static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
+
+static inline void prcmu_qos_voice_call_override(bool enable) {}
+
+#endif /* CONFIG_U8500_PRCMU */
+
+#ifdef CONFIG_UX500_PRCMU_QOS_POWER
+
+int prcmu_qos_requirement(int pm_qos_class);
+int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
+int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
+void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
+int prcmu_qos_add_notifier(int prcmu_qos_class,
+			   struct notifier_block *notifier);
+int prcmu_qos_remove_notifier(int prcmu_qos_class,
+			      struct notifier_block *notifier);
+
+#else
+
+static inline int prcmu_qos_requirement(int prcmu_qos_class)
+{
+	return 0;
+}
+
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+					    char *name, s32 value)
+{
+	return 0;
+}
+
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+					       char *name, s32 new_value)
+{
+	return 0;
+}
+
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
+{
+}
+
+static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
+					 struct notifier_block *notifier)
+{
+	return 0;
+}
+static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
+					    struct notifier_block *notifier)
+{
+	return 0;
+}
+
+#endif
+
+#endif /* __MACH_PRCMU_QOS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
index 4f6f2f0394c..5478a553d60 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -1,59 +1,15 @@
 /*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
+ * Copyright (c) 2009 ST-Ericsson SA
  *
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit registers
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
  */
-
 #ifndef __MACH_PRCMU_REGS_H
 #define __MACH_PRCMU_REGS_H
 
 #include <mach/hardware.h>
 
-#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
-
-#define PRCM_ACLK_MGT_OFF		0x004
-#define PRCM_SVACLK_MGT_OFF		0x008
-#define PRCM_SIACLK_MGT_OFF		0x00C
-#define PRCM_SGACLK_MGT_OFF		0x014
-#define PRCM_UARTCLK_MGT_OFF		0x018
-#define PRCM_MSP02CLK_MGT_OFF		0x01C
-#define PRCM_I2CCLK_MGT_OFF		0x020
-#define PRCM_SDMMCCLK_MGT_OFF		0x024
-#define PRCM_SLIMCLK_MGT_OFF		0x028
-#define PRCM_PER1CLK_MGT_OFF		0x02C
-#define PRCM_PER2CLK_MGT_OFF		0x030
-#define PRCM_PER3CLK_MGT_OFF		0x034
-#define PRCM_PER5CLK_MGT_OFF		0x038
-#define PRCM_PER6CLK_MGT_OFF		0x03C
-#define PRCM_PER7CLK_MGT_OFF		0x040
-#define PRCM_PWMCLK_MGT_OFF		0x044 /* for DB5500 */
-#define PRCM_IRDACLK_MGT_OFF		0x048 /* for DB5500 */
-#define PRCM_IRRCCLK_MGT_OFF		0x04C /* for DB5500 */
-#define PRCM_LCDCLK_MGT_OFF		0x044
-#define PRCM_BMLCLK_MGT_OFF		0x04C
-#define PRCM_HSITXCLK_MGT_OFF		0x050
-#define PRCM_HSIRXCLK_MGT_OFF		0x054
-#define PRCM_HDMICLK_MGT_OFF		0x058
-#define PRCM_APEATCLK_MGT_OFF		0x05C
-#define PRCM_APETRACECLK_MGT_OFF	0x060
-#define PRCM_MCDECLK_MGT_OFF		0x064
-#define PRCM_IPI2CCLK_MGT_OFF		0x068
-#define PRCM_DSIALTCLK_MGT_OFF		0x06C
-#define PRCM_DMACLK_MGT_OFF		0x074
-#define PRCM_B2R2CLK_MGT_OFF		0x078
-#define PRCM_TVCLK_MGT_OFF		0x07C
-#define PRCM_UNIPROCLK_MGT_OFF		0x278
-#define PRCM_SSPCLK_MGT_OFF		0x280
-#define PRCM_RNGCLK_MGT_OFF		0x284
-#define PRCM_UICCCLK_MGT_OFF		0x27C
-#define PRCM_MSP1CLK_MGT_OFF		0x288
-
 #define PRCM_ARM_PLLDIVPS	(_PRCMU_BASE + 0x118)
 #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE		0x3f
 #define PRCM_ARM_PLLDIVPS_MAX_MASK		0xf
@@ -69,15 +25,11 @@
 #define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON	0x100
 
 #define PRCM_ARMCLKFIX_MGT	(_PRCMU_BASE + 0x0)
-#define PRCM_A9PL_FORCE_CLKEN	(_PRCMU_BASE + 0x19C)
 #define PRCM_A9_RESETN_CLR	(_PRCMU_BASE + 0x1f4)
 #define PRCM_A9_RESETN_SET	(_PRCMU_BASE + 0x1f0)
 #define PRCM_ARM_LS_CLAMP	(_PRCMU_BASE + 0x30c)
 #define PRCM_SRAM_A9		(_PRCMU_BASE + 0x308)
 
-#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN BIT(0)
-#define PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN BIT(1)
-
 /* ARM WFI Standby signal register */
 #define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
 #define PRCM_IOCR		(_PRCMU_BASE + 0x310)
@@ -104,18 +56,12 @@
 #define PRCM_ARMITVAL127TO96	(_PRCMU_BASE + 0x26C)
 
 #define PRCM_HOSTACCESS_REQ	(_PRCMU_BASE + 0x334)
-#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ 0x1
 #define ARM_WAKEUP_MODEM	0x1
 
-#define PRCM_ARM_IT1_CLR	(_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_CLEAR	(_PRCMU_BASE + 0x48C)
 #define PRCM_ARM_IT1_VAL	(_PRCMU_BASE + 0x494)
 #define PRCM_HOLD_EVT		(_PRCMU_BASE + 0x174)
 
-#define PRCM_MOD_AWAKE_STATUS	(_PRCMU_BASE + 0x4A0)
-#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_COREPD_AWAKE	BIT(0)
-#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_AAPD_AWAKE	BIT(1)
-#define PRCM_MOD_AWAKE_STATUS_PRCM_MOD_VMODEM_OFF_ISO	BIT(2)
-
 #define PRCM_ITSTATUS0		(_PRCMU_BASE + 0x148)
 #define PRCM_ITSTATUS1		(_PRCMU_BASE + 0x150)
 #define PRCM_ITSTATUS2		(_PRCMU_BASE + 0x158)
@@ -136,21 +82,16 @@
 #define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
 #define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
-#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + PRCM_LCDCLK_MGT_OFF)
-#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + PRCM_MCDECLK_MGT_OFF)
-#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + PRCM_HDMICLK_MGT_OFF)
-#define PRCM_TVCLK_MGT             (_PRCMU_BASE + PRCM_TVCLK_MGT_OFF)
+#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)
+#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)
+#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)
+#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)
 #define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
 #define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 #define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
 #define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
-
 #define PRCM_CLKOCR		   (_PRCMU_BASE + 0x1CC)
-#define PRCM_CLKOCR_CLKOUT0_REF_CLK	(1 << 0)
-#define PRCM_CLKOCR_CLKOUT0_MASK	BITS(0, 13)
-#define PRCM_CLKOCR_CLKOUT1_REF_CLK	(1 << 16)
-#define PRCM_CLKOCR_CLKOUT1_MASK	BITS(16, 29)
 
 /* ePOD and memory power signal control registers */
 #define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
@@ -165,41 +106,5 @@
 #define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
 #define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
 
-/* PRCMU HW semaphore */
-#define PRCM_SEM                   (_PRCMU_BASE + 0x400)
-#define PRCM_SEM_PRCM_SEM BIT(0)
-
-#define PRCM_TCR                   (_PRCMU_BASE + 0x1C8)
-#define PRCM_TCR_TENSEL_MASK       BITS(0, 7)
-#define PRCM_TCR_STOP_TIMERS       BIT(16)
-#define PRCM_TCR_DOZE_MODE         BIT(17)
-
-#define PRCM_CLKOCR_CLKODIV0_SHIFT	0
-#define PRCM_CLKOCR_CLKODIV0_MASK	BITS(0, 5)
-#define PRCM_CLKOCR_CLKOSEL0_SHIFT	6
-#define PRCM_CLKOCR_CLKOSEL0_MASK	BITS(6, 8)
-#define PRCM_CLKOCR_CLKODIV1_SHIFT	16
-#define PRCM_CLKOCR_CLKODIV1_MASK	BITS(16, 21)
-#define PRCM_CLKOCR_CLKOSEL1_SHIFT	22
-#define PRCM_CLKOCR_CLKOSEL1_MASK	BITS(22, 24)
-#define PRCM_CLKOCR_CLK1TYPE		BIT(28)
-
-#define PRCM_CLK_MGT_CLKPLLDIV_MASK	BITS(0, 4)
-#define PRCM_CLK_MGT_CLKPLLSW_MASK	BITS(5, 7)
-#define PRCM_CLK_MGT_CLKEN		BIT(8)
-
-/* GPIOCR register */
-#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
-
-#define PRCM_DDR_SUBSYS_APE_MINBW	(_PRCMU_BASE + 0x438)
-#define PRCM_CGATING_BYPASS		(_PRCMU_BASE + 0x134)
-#define PRCM_CGATING_BYPASS_ICN2	BIT(6)
-
-/* Miscellaneous unit registers */
-#define PRCM_RESOUTN_SET		(_PRCMU_BASE + 0x214)
-#define PRCM_RESOUTN_CLR		(_PRCMU_BASE + 0x218)
-
-/* System reset register */
-#define PRCM_APE_SOFTRST 		(_PRCMU_BASE + 0x228)
 
 #endif /* __MACH_PRCMU__REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 92fd7f79a4d..5638b970752 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -9,8 +9,7 @@
 #define __MACH_PRCMU_H
 
 #include <linux/interrupt.h>
-#include <linux/notifier.h>
-#include <asm/mach-types.h>
+#include <mach/prcmu-qos.h>
 
 /* PRCMU Wakeup defines */
 enum prcmu_wakeup_index {
@@ -28,6 +27,15 @@ enum prcmu_wakeup_index {
 };
 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
 
+/* Low power states */
+#define PRCMU_AP_NO_CHANGE 0x00
+#define PRCMU_AP_SLEEP 0x01
+#define PRCMU_AP_DEEP_SLEEP 0x04
+#define PRCMU_AP_IDLE 0x05
+#define PRCMU_AP_DEEP_IDLE 0x07
+/* Legacy names */
+#define APEXECUTE_TO_APSLEEP PRCMU_AP_SLEEP
+
 /* EPOD (power domain) IDs */
 
 /*
@@ -80,8 +88,31 @@ enum prcmu_wakeup_index {
 #define EPOD_STATE_ON_CLK_OFF	0x03
 #define EPOD_STATE_ON		0x04
 
+/* DB5500 CLKOUT IDs */
+enum {
+	DB5500_CLKOUT0 = 0,
+	DB5500_CLKOUT1,
+};
+
+/* DB5500 CLKOUTx sources */
+enum {
+	DB5500_CLKOUT_REF_CLK_SEL0,
+	DB5500_CLKOUT_RTC_CLK0_SEL0,
+	DB5500_CLKOUT_ULP_CLK_SEL0,
+	DB5500_CLKOUT_STATIC0,
+	DB5500_CLKOUT_REFCLK,
+	DB5500_CLKOUT_ULPCLK,
+	DB5500_CLKOUT_ARMCLK,
+	DB5500_CLKOUT_SYSACC0CLK,
+	DB5500_CLKOUT_SOC0PLLCLK,
+	DB5500_CLKOUT_SOC1PLLCLK,
+	DB5500_CLKOUT_DDRPLLCLK,
+	DB5500_CLKOUT_TVCLK,
+	DB5500_CLKOUT_IRDACLK,
+};
+
 /*
- * CLKOUT sources
+ * DB8500 CLKOUT sources
  */
 #define PRCMU_CLKSRC_CLK38M		0x00
 #define PRCMU_CLKSRC_ACLK		0x01
@@ -111,6 +142,7 @@ enum prcmu_clock {
 	PRCMU_MSP1CLK,
 	PRCMU_I2CCLK,
 	PRCMU_SDMMCCLK,
+	PRCMU_SPARE1CLK,
 	PRCMU_SLIMCLK,
 	PRCMU_PER1CLK,
 	PRCMU_PER2CLK,
@@ -141,6 +173,7 @@ enum prcmu_clock {
 	PRCMU_SVACLK,
 	PRCMU_NUM_REG_CLOCKS,
 	PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+	PRCMU_CDCLK,
 	PRCMU_TIMCLK,
 	PRCMU_PLLSOC0,
 	PRCMU_PLLSOC1,
@@ -215,159 +248,52 @@ enum ddr_pwrst {
 	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
 };
 
-#include <linux/mfd/db8500-prcmu.h>
-#include <linux/mfd/db5500-prcmu.h>
+#include <mach/prcmu-db8500.h>
+#include <mach/prcmu-db5500.h>
 
-#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500)
+#if defined(CONFIG_U8500_PRCMU) || defined(CONFIG_U5500_PRCMU)
 
-static inline void __init prcmu_early_init(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_early_init();
-	else
-		return db8500_prcmu_early_init();
-}
+void __init prcmu_early_init(void);
 
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-		bool keep_ap_pll)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_set_power_state(state, keep_ulp_clk,
-			keep_ap_pll);
-	else
-		return db8500_prcmu_set_power_state(state, keep_ulp_clk,
-			keep_ap_pll);
-}
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
 
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_set_epod(epod_id, epod_state);
-	else
-		return db8500_prcmu_set_epod(epod_id, epod_state);
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups)
-{
-	if (machine_is_u5500())
-		db5500_prcmu_enable_wakeups(wakeups);
-	else
-		db8500_prcmu_enable_wakeups(wakeups);
-}
+int prcmu_set_epod(u16 epod_id, u8 epod_state);
 
+void prcmu_enable_wakeups(u32 wakeups);
 static inline void prcmu_disable_wakeups(void)
 {
 	prcmu_enable_wakeups(0);
 }
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events)
-{
-	if (machine_is_u5500())
-		db5500_prcmu_config_abb_event_readout(abb_events);
-	else
-		db8500_prcmu_config_abb_event_readout(abb_events);
-}
-
-static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
-{
-	if (machine_is_u5500())
-		db5500_prcmu_get_abb_event_buffer(buf);
-	else
-		db8500_prcmu_get_abb_event_buffer(buf);
-}
+void prcmu_config_abb_event_readout(u32 abb_events);
+void prcmu_get_abb_event_buffer(void __iomem **buf);
 
 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 
 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_request_clock(clock, enable);
-	else
-		return db8500_prcmu_request_clock(clock, enable);
-}
+int prcmu_request_clock(u8 clock, bool enable);
 
 int prcmu_set_ape_opp(u8 opp);
 int prcmu_get_ape_opp(void);
+int prcmu_set_arm_opp(u8 opp);
+int prcmu_get_arm_opp(void);
 int prcmu_set_ddr_opp(u8 opp);
 int prcmu_get_ddr_opp(void);
 
-static inline int prcmu_set_arm_opp(u8 opp)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_set_arm_opp(opp);
-	else
-		return db8500_prcmu_set_arm_opp(opp);
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_get_arm_opp();
-	else
-		return db8500_prcmu_get_arm_opp();
-}
-
-static inline void prcmu_system_reset(u16 reset_code)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_system_reset(reset_code);
-	else
-		return db8500_prcmu_system_reset(reset_code);
-}
-
-static inline u16 prcmu_get_reset_code(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_get_reset_code();
-	else
-		return db8500_prcmu_get_reset_code();
-}
+void prcmu_system_reset(u16 reset_code);
+u16 prcmu_get_reset_code(void);
 
 void prcmu_ac_wake_req(void);
 void prcmu_ac_sleep_req(void);
 void prcmu_modem_reset(void);
-static inline bool prcmu_is_ac_wake_requested(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_is_ac_wake_requested();
-	else
-		return db8500_prcmu_is_ac_wake_requested();
-}
+bool prcmu_is_ac_wake_requested(void);
 
-static inline int prcmu_set_display_clocks(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_set_display_clocks();
-	else
-		return db8500_prcmu_set_display_clocks();
-}
+int prcmu_set_display_clocks(void);
+int prcmu_disable_dsipll(void);
+int prcmu_enable_dsipll(void);
+int prcmu_config_esram0_deep_sleep(u8 state);
 
-static inline int prcmu_disable_dsipll(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_disable_dsipll();
-	else
-		return db8500_prcmu_disable_dsipll();
-}
-
-static inline int prcmu_enable_dsipll(void)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_enable_dsipll();
-	else
-		return db8500_prcmu_enable_dsipll();
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
-	if (machine_is_u5500())
-		return db5500_prcmu_config_esram0_deep_sleep(state);
-	else
-		return db8500_prcmu_config_esram0_deep_sleep(state);
-}
 #else
 
 static inline void __init prcmu_early_init(void) {}
@@ -484,71 +410,4 @@ static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
 
 #endif
 
-/* PRCMU QoS APE OPP class */
-#define PRCMU_QOS_APE_OPP 1
-#define PRCMU_QOS_DDR_OPP 2
-#define PRCMU_QOS_DEFAULT_VALUE -1
-
-#ifdef CONFIG_UX500_PRCMU_QOS_POWER
-
-unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
-void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
-void prcmu_qos_force_opp(int, s32);
-void prcmu_qos_voice_call_override(bool enable);
-int prcmu_qos_requirement(int pm_qos_class);
-int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
-int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
-void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
-int prcmu_qos_add_notifier(int prcmu_qos_class,
-			   struct notifier_block *notifier);
-int prcmu_qos_remove_notifier(int prcmu_qos_class,
-			      struct notifier_block *notifier);
-
-#else
-
-static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
-{
-	return 0;
-}
-
-static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
-
-static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
-
-static inline void prcmu_qos_voice_call_override(bool enable) {}
-
-static inline int prcmu_qos_requirement(int prcmu_qos_class)
-{
-	return 0;
-}
-
-static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
-					    char *name, s32 value)
-{
-	return 0;
-}
-
-static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
-					       char *name, s32 new_value)
-{
-	return 0;
-}
-
-static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
-{
-}
-
-static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
-					 struct notifier_block *notifier)
-{
-	return 0;
-}
-static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
-					    struct notifier_block *notifier)
-{
-	return 0;
-}
-
-#endif
-
 #endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/regulator.h b/arch/arm/mach-ux500/include/mach/regulator.h
new file mode 100644
index 00000000000..75ff3340359
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/regulator.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Bengt Jonsson <bengt.jonsson@stericsson.com> for ST-Ericsson,
+ *	   Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
+ *
+ * License Terms: GNU General Public License v2
+ *
+ */
+
+#ifndef MACH_UX500_REGULATOR_H
+#define MACH_UX500_REGULATOR_H
+
+#include <linux/device.h>
+
+struct ux500_regulator;
+
+#ifdef CONFIG_REGULATOR
+/*
+ * NOTE! The device will be connected to the correct regulator by this
+ * new framework. A list with connections will match up dev_name(dev)
+ * to the specific regulator. This follows the same principle as the
+ * normal regulator framework.
+ *
+ * This framework shall only be used in special cases when a regulator
+ * has to be enabled/disabled in atomic context.
+ */
+
+/**
+ * ux500_regulator_get()
+ *
+ * @dev: Drivers device struct
+ *
+ * Returns a ux500_regulator struct. Shall be used as argument for
+ * ux500_regulator_atomic_enable/disable calls.
+ * Return ERR_PTR(-EINVAL) upon no matching regulator found.
+ */
+struct ux500_regulator *__must_check ux500_regulator_get(struct device *dev);
+
+/**
+ * ux500_regulator_atomic_enable()
+ *
+ * @regulator: Regulator handle, provided from ux500_regulator_get.
+ *
+ * The enable/disable functions keep an internal counter, so every
+ * enable must be paired with an disable in order to turn off regulator.
+ */
+int ux500_regulator_atomic_enable(struct ux500_regulator *regulator);
+
+/**
+ * ux500_regulator_atomic_disable()
+ *
+ * @regulator: Regulator handle, provided from ux500_regulator_get.
+ *
+ */
+int ux500_regulator_atomic_disable(struct ux500_regulator *regulator);
+
+/**
+ * ux500_regulator_put()
+ *
+ * @regulator: Regulator handle, provided from ux500_regulator_get.
+ */
+void ux500_regulator_put(struct ux500_regulator *regulator);
+#else
+static inline struct ux500_regulator *__must_check
+ux500_regulator_get(struct device *dev)
+{
+	return ERR_PTR(-EINVAL);
+}
+
+static inline int
+ux500_regulator_atomic_enable(struct ux500_regulator *regulator)
+{
+	return -EINVAL;
+}
+
+static inline int
+ux500_regulator_atomic_disable(struct ux500_regulator *regulator)
+{
+	return -EINVAL;
+}
+
+static inline void ux500_regulator_put(struct ux500_regulator *regulator)
+{
+}
+#endif
+
+#endif