mach-ux500: Fixing and use the right timers (mtu+prcmu+rtc)

Signed-off-by: Philippe Langlais <philippe.langlais@stericsson.com>

7 files changed, 26 insertions, 90 deletions

diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 2c576e99ba5..5368e528d01 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -25,11 +25,10 @@ CONFIG_MACH_U8500=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_U5500=y
+CONFIG_U8500_PRCMU_TIMER=y
 CONFIG_DB8500_MLOADER=y
-CONFIG_U8500_CPUIDLE_DEEPEST_STATE=3
 CONFIG_UX500_SUSPEND=y
 CONFIG_UX500_SUSPEND_STANDBY=y
-CONFIG_UX500_SUSPEND_MEM=y
 CONFIG_UX500_SUSPEND_DBG=y
 CONFIG_UX500_SUSPEND_DBG_WAKE_ON_UART=y
 CONFIG_NO_HZ=y
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 37a3bbeec64..82fb5d44bf9 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -5,6 +5,7 @@ config UX500_SOC_COMMON
 	default y
 	select ARM_GIC
 	select HAS_MTU
+	select NOMADIK_GPIO
 	select ARM_ERRATA_753970
 
 menu "Ux500 SoC"
@@ -66,6 +67,26 @@ config KEYLAYOUT_LAYOUT2
 
 endchoice
 
+choice
+	prompt "Ux500 sched_clock timer"
+	default UX500_MTU_TIMER
+
+config U8500_PRCMU_TIMER
+	bool "PRCMU Timer sched_clock"
+	depends on UX500_SOC_DB8500 && U8500_CPUIDLE
+	help
+	  Add support for an always on sched_clock, required for
+	  proper cpuidle and suspend.
+
+config UX500_MTU_TIMER
+	bool "Multi Timer Unit sched_clock"
+	help
+	  Add sched_clock support for the Multi Timer Unit.
+	  Since mtu isn't always on cpuidle will not
+	  work with this clock.
+
+endchoice
+
 config UX500_DEBUG_UART
 	int "Ux500 UART to use for low-level debug"
 	default 2
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8d4ab234072..3371208a5aa 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -42,6 +42,8 @@ static struct map_desc u8500_io_desc[] __initdata = {
 	__IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
 	__IO_DEV_DESC(U8500_TWD_BASE, SZ_4K),
 	__IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
+	__IO_DEV_DESC(U8500_MTU1_BASE, SZ_4K),
+	__IO_DEV_DESC(U8500_RTC_BASE, SZ_4K),
 	__IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
 	__IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
 
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 9d0fcc8bb96..a1467757fb1 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -121,30 +121,3 @@ static int ux500_l2x0_init(void)
 }
 early_initcall(ux500_l2x0_init);
 #endif
-
-static void __init ux500_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
-	/* Setup the local timer base */
-	if (cpu_is_u5500())
-		twd_base = __io_address(U5500_TWD_BASE);
-	else if (cpu_is_u8500())
-		twd_base = __io_address(U8500_TWD_BASE);
-	else
-		ux500_unknown_soc();
-#endif
-	if (cpu_is_u5500())
-		mtu_base = __io_address(U5500_MTU0_BASE);
-	else if (cpu_is_u8500ed())
-		mtu_base = __io_address(U8500_MTU0_BASE_ED);
-	else if (cpu_is_u8500())
-		mtu_base = __io_address(U8500_MTU0_BASE);
-	else
-		ux500_unknown_soc();
-
-	nmdk_timer_init();
-}
-
-struct sys_timer ux500_timer = {
-	.init	= ux500_timer_init,
-};
diff --git a/arch/arm/mach-ux500/include/mach/mtu.h b/arch/arm/mach-ux500/include/mach/mtu.h
deleted file mode 100644
index d778c24e3e3..00000000000
--- a/arch/arm/mach-ux500/include/mach/mtu.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (C) 2009 ST-Ericsson SA
- * MultiTimerUnit register definitions, copied from Nomadik 8815
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef __ASM_ARCH_MTU_H
-#define __ASM_ARCH_MTU_H
-
-/*
- * The MTU device hosts four different counters, with 4 set of
- * registers. These are register names.
- */
-
-#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
-#define MTU_RIS		0x04	/* Raw interrupt status */
-#define MTU_MIS		0x08	/* Masked interrupt status */
-#define MTU_ICR		0x0C	/* Interrupt clear register */
-
-/* per-timer registers take 0..3 as argument */
-#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
-#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
-#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
-#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */
-
-/* bits for the control register */
-#define MTU_CRn_ENA		0x80
-#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
-#define MTU_CRn_PRESCALE_MASK	0x0c
-#define MTU_CRn_PRESCALE_1		0x00
-#define MTU_CRn_PRESCALE_16		0x04
-#define MTU_CRn_PRESCALE_256		0x08
-#define MTU_CRn_32BITS		0x02
-#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/
-
-/* Other registers are usual amba/primecell registers, currently not used */
-#define MTU_ITCR	0xff0
-#define MTU_ITOP	0xff4
-
-#define MTU_PERIPH_ID0	0xfe0
-#define MTU_PERIPH_ID1	0xfe4
-#define MTU_PERIPH_ID2	0xfe8
-#define MTU_PERIPH_ID3	0xfeC
-
-#define MTU_PCELL0	0xff0
-#define MTU_PCELL1	0xff4
-#define MTU_PCELL2	0xff8
-#define MTU_PCELL3	0xffC
-
-
-#ifdef CONFIG_LOCAL_TIMERS
-extern void __iomem *twd_base;
-#endif
-
-#endif /* __ASM_ARCH_MTU_H */
-
diff --git a/arch/arm/mach-ux500/timer-db8500.c b/arch/arm/mach-ux500/timer-db8500.c
index 6bf78bc2816..c552b62e4e3 100644
--- a/arch/arm/mach-ux500/timer-db8500.c
+++ b/arch/arm/mach-ux500/timer-db8500.c
@@ -77,7 +77,7 @@ static void __init u8500_timer_init(void)
 #endif
 }
 
-struct sys_timer u8500_timer = {
+struct sys_timer ux500_timer = {
 	.init		= u8500_timer_init,
 	.suspend	= u8500_timer_suspend,
 	.resume		= u8500_timer_reset,
diff --git a/arch/arm/mach-ux500/timer-mtu.c b/arch/arm/mach-ux500/timer-mtu.c
index f9a4c405aa7..60d44f118bd 100644
--- a/arch/arm/mach-ux500/timer-mtu.c
+++ b/arch/arm/mach-ux500/timer-mtu.c
@@ -23,7 +23,7 @@
 #include <linux/boottime.h>
 #include <linux/cnt32_to_63.h>
 #include <asm/mach/time.h>
-#include <mach/mtu.h>
+#include <plat/mtu.h>
 #include <mach/setup.h>
 
 #define TIMER_CTRL	0x80	/* No divisor */