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| author | KaiGai Kohei <kaigai@ak.jp.nec.com> | 2006-05-19 00:43:53 +0900 |
|---|---|---|
| committer | KaiGai Kohei <kaigai@ak.jp.nec.com> | 2006-05-19 00:43:53 +0900 |
| commit | 20a92fc74c5c91c7bc5693d51acc2b99aceb0465 (patch) | |
| tree | 41bf535f38ff1a29c560bcf622e9b4ef03c2c106 /arch/i386/kernel/mpparse.c | |
| parent | 21b9879bf2817aca343cdda11ade6a87f5373e74 (diff) | |
| parent | f6a673b3f4f93c1c50e1b18f29254b0531b722a8 (diff) | |
Merge git://git.infradead.org/mtd-2.6
Diffstat (limited to 'arch/i386/kernel/mpparse.c')
| -rw-r--r-- | arch/i386/kernel/mpparse.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c index 34d21e21e01..6b1392d33ed 100644 --- a/arch/i386/kernel/mpparse.c +++ b/arch/i386/kernel/mpparse.c @@ -1130,7 +1130,17 @@ int mp_register_gsi (u32 gsi, int triggering, int polarity) */ int irq = gsi; if (gsi < MAX_GSI_NUM) { - if (gsi > 15) + /* + * Retain the VIA chipset work-around (gsi > 15), but + * avoid a problem where the 8254 timer (IRQ0) is setup + * via an override (so it's not on pin 0 of the ioapic), + * and at the same time, the pin 0 interrupt is a PCI + * type. The gsi > 15 test could cause these two pins + * to be shared as IRQ0, and they are not shareable. + * So test for this condition, and if necessary, avoid + * the pin collision. + */ + if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0)) gsi = pci_irq++; /* * Don't assign IRQ used by ACPI SCI |