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authorLinus Torvalds <torvalds@linux-foundation.org>2010-04-12 18:36:11 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2010-04-12 18:36:11 -0700
commit4505a4938917f4872efcc90bc1e5f4f0ce903b47 (patch)
treee049aed70101694b599ae53e6f56bff66d37f8a7 /arch/mips/kernel/traps.c
parentfedfb947b2235c1085df97cf52f688b808c3a515 (diff)
parentf6be75d03c8870be91e6e2a195648ece04b6bb16 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (36 commits) MIPS: Calculate proper ebase value for 64-bit kernels MIPS: Alchemy: DB1200: Remove custom wait implementation MIPS: Big Sur: Make defconfig more useful. MIPS: Fix __vmalloc() etc. on MIPS for non-GPL modules MIPS: Sibyte: Fix M3 TLB exception handler workaround. MIPS: BCM63xx: Fix build failure in board_bcm963xx.c MIPS: uasm: Add OR instruction. MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions. MIPS: BCM63xx: Initialize gpio_out_low & out_high to current value at boot. MIPS: BCM63xx: Register SSB SPROM fallback in board's first stage callback MIPS: BCM63xx: Fix typo in cpu-feature-overrides file. MIPS: BCM63xx: Add support for second uart. MIPS: BCM63xx: Fix double gpio registration. MIPS: BCM63xx: Add DWVS0 board MIPS: BCM63xx: Add the RTA1025W-16 BCM6348-based board to suppported boards. MIPS: BCM63xx: Fix BCM6338 and BCM6345 gpio count MIPS: libgcc.h: Checkpatch cleanup MIPS: Loongson-2F: Flush the branch target history in BTB and RAS MIPS: Move signal trampolines off of the stack. MIPS: Preliminary VDSO ...
Diffstat (limited to 'arch/mips/kernel/traps.c')
-rw-r--r--arch/mips/kernel/traps.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 4e00f9bc23e..1a4dd657ccb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1599,7 +1599,7 @@ void __init trap_init(void)
ebase = (unsigned long)
__alloc_bootmem(size, 1 << fls(size), 0);
} else {
- ebase = CAC_BASE;
+ ebase = CKSEG0;
if (cpu_has_mips_r2)
ebase += (read_c0_ebase() & 0x3ffff000);
}