ux500: align u5500 PRCMU & CPUFREQ management with u8500 (multiple commits in one)

Signed-off-by: Philippe Langlais <philippe.langlais@linaro.org>

Merge of following commits too:

u5500: add support for sysclk

basic sysclk support added in PRCMU driver and
clock framework driver updated.

Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>

U5500: Support for ESRAM12 EPOD in PRCMU driver

Signed-off-by: Vijaya Kumar Kilari <vijay.kilari@stericsson.com>

ux500: regulator: handle different base offset of ePOD ID

5500 ePOD ids are offseted for some reason in the PRCMU driver.  Adjust the ids
to index the local arrays to avoid memory corruption.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>

ux500: pm: support PRCMU status check on 5500

This also removes unused 8500v1 code.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>

arm: ux500: prcmu_ac_wake_req workaround

This patch adds a check in prcmu_ac_wake_req that the modem is
awake (in terms of the value in the PRCM_MOD_AWAKE_STATUS
register) after the AC_WAKE_ACK has been received from the PRCMU
FW. If the check fails, a retry is made.

This seems to be necessary, since the modem can generate an
AC_WAKE_ACK, and then still go to sleep.

Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>

U5500: Add support for PRCMU Mailbox0

Add PRCMU mailbox 0 support for irq wakeup
enable and disable

Signed-off-by: Vijaya Kumar K <vijay.kilari@stericsson.com>

U5500: Add support for power state transition

PRCMU driver is updated to provide API for
system power state transition

Signed-off-by: Vijaya Kumar K <vijay.kilari@stericsson.com>

ARM: ux500: prcmu: Add A9 watchdog interface

Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>

U5500 : ab5500 core interrupt hander update

AB5500 interrupts will be now handled by PRCMU and then
routed to AB5500 core driver.AB5500 irq handler will
no more read the latch registers to find the interrupt
reason.Instead PRCMU will read the latch registers and
provide the values to core driver.

Signed-off-by: Bibek Basu <bibek.basu@stericsson.com>

ARM: ux500: prcmu-dbg: Tiny code clean-up

Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>

u5500: add mailbox1 and related function support

Add cpufreq-db5500.c file for db5500 CPUfreq support.

PRCMU mailbox1 and related functions' support is added.
List of functions implemented:
- prcmu_get/set_arm_opp
- read_mailbox_1

Signed-off-by: Shreshtha Kumar Sahu <shreshthakumar.sahu@stericsson.com>

Fix for PRCMU

u5500: PRCMU IRQ should be NO_SUSPEND

As on 8500.

Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>

ARM: u5500: PRCMU reset API

Added API for rebooting the board and for getting the last reboot code.

Signed-off-by: Pawel Szyszuk <pawel.szyszuk@stericsson.com>

1 files changed, 81 insertions, 78 deletions

diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index a03b51e991a..60d27f7bfc1 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -145,20 +145,6 @@ enum ap_pwrst_trans {
 };
 
 /**
- * enum ddr_pwrst - DDR power states definition
- * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
- * @DDR_PWR_STATE_ON:
- * @DDR_PWR_STATE_OFFLOWLAT:
- * @DDR_PWR_STATE_OFFHIGHLAT:
- */
-enum ddr_pwrst {
-	DDR_PWR_STATE_UNCHANGED     = 0x00,
-	DDR_PWR_STATE_ON            = 0x01,
-	DDR_PWR_STATE_OFFLOWLAT     = 0x02,
-	DDR_PWR_STATE_OFFHIGHLAT    = 0x03
-};
-
-/**
  * enum hw_acc_state - State definition for hardware accelerator
  * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
  * @HW_OFF: The hardware accelerator must be switched off
@@ -507,30 +493,12 @@ struct prcmu_auto_pm_config {
 	u8 sva_policy;
 };
 
-/*
- * Definitions for controlling ESRAM0 in deep sleep.
- */
-#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
-#define ESRAM0_DEEP_SLEEP_STATE_RET 2
-
-#ifdef CONFIG_MFD_DB8500_PRCMU
-void __init prcmu_early_init(void);
-int prcmu_set_display_clocks(void);
-int prcmu_disable_dsipll(void);
-int prcmu_enable_dsipll(void);
-#else
-static inline void __init prcmu_early_init(void) {}
-#endif
-
 #ifdef CONFIG_MFD_DB8500_PRCMU
 
+void db8500_prcmu_early_init(void);
 int prcmu_set_rc_a2p(enum romcode_write);
 enum romcode_read prcmu_get_rc_p2a(void);
 enum ap_pwrst prcmu_get_xp70_current_state(void);
-void prcmu_config_abb_event_readout(u32 abb_events);
-void prcmu_get_abb_event_buffer(void __iomem **buf);
-int prcmu_set_arm_opp(u8 opp);
-int prcmu_get_arm_opp(void);
 bool prcmu_has_arm_maxopp(void);
 bool prcmu_is_u8400(void);
 int prcmu_set_ape_opp(u8 opp);
@@ -539,8 +507,6 @@ int prcmu_request_ape_opp_100_voltage(bool enable);
 int prcmu_release_usb_wakeup_state(void);
 int prcmu_set_ddr_opp(u8 opp);
 int prcmu_get_ddr_opp(void);
-unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
-void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
 /* NOTE! Use regulator framework instead */
 int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
@@ -549,7 +515,6 @@ bool prcmu_is_auto_pm_enabled(void);
 
 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
 int prcmu_set_clock_divider(u8 clock, u8 divider);
-int prcmu_config_esram0_deep_sleep(u8 state);
 int prcmu_config_hotdog(u8 threshold);
 int prcmu_config_hotmon(u8 low, u8 high);
 int prcmu_start_temp_sense(u16 cycles32k);
@@ -560,18 +525,35 @@ int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
 void prcmu_ac_wake_req(void);
 void prcmu_ac_sleep_req(void);
 void prcmu_modem_reset(void);
-bool prcmu_is_ac_wake_requested(void);
 void prcmu_enable_spi2(void);
 void prcmu_disable_spi2(void);
 
+int prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
+int prcmu_enable_a9wdog(u8 id);
+int prcmu_disable_a9wdog(u8 id);
+int prcmu_kick_a9wdog(u8 id);
+int prcmu_load_a9wdog(u8 id, u32 val);
+
 void db8500_prcmu_system_reset(u16 reset_code);
 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
 void db8500_prcmu_enable_wakeups(u32 wakeups);
 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
 int db8500_prcmu_request_clock(u8 clock, bool enable);
+int db8500_prcmu_set_display_clocks(void);
+int db8500_prcmu_disable_dsipll(void);
+int db8500_prcmu_enable_dsipll(void);
+void db8500_prcmu_config_abb_event_readout(u32 abb_events);
+void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
+int db8500_prcmu_config_esram0_deep_sleep(u8 state);
+u16 db8500_prcmu_get_reset_code(void);
+bool db8500_prcmu_is_ac_wake_requested(void);
+int db8500_prcmu_set_arm_opp(u8 opp);
+int db8500_prcmu_get_arm_opp(void);
 
 #else /* !CONFIG_MFD_DB8500_PRCMU */
 
+static inline void db8500_prcmu_early_init(void) {}
+
 static inline int prcmu_set_rc_a2p(enum romcode_write code)
 {
 	return 0;
@@ -587,20 +569,6 @@ static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
 	return AP_EXECUTE;
 }
 
-static inline void prcmu_disable_wakeups(void) {}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
-	return 0;
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
-	return ARM_100_OPP;
-}
-
 static inline bool prcmu_has_arm_maxopp(void)
 {
 	return false;
@@ -641,13 +609,6 @@ static inline int prcmu_get_ddr_opp(void)
 	return DDR_100_OPP;
 }
 
-static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
-{
-	return 0;
-}
-
-static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
-
 static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
 {
 	return 0;
@@ -673,11 +634,6 @@ static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
 	return 0;
 }
 
-int prcmu_config_esram0_deep_sleep(u8 state)
-{
-	return 0;
-}
-
 static inline int prcmu_config_hotdog(u8 threshold)
 {
 	return 0;
@@ -714,54 +670,101 @@ static inline void prcmu_ac_sleep_req(void) {}
 
 static inline void prcmu_modem_reset(void) {}
 
-static inline bool prcmu_is_ac_wake_requested(void)
+static inline int prcmu_enable_spi2(void)
 {
-	return false;
+	return 0;
 }
 
-#ifndef CONFIG_UX500_SOC_DB5500
-static inline int prcmu_set_display_clocks(void)
+static inline int prcmu_disable_spi2(void)
 {
 	return 0;
 }
 
-static inline int prcmu_disable_dsipll(void)
+static inline void db8500_prcmu_system_reset(u16 reset_code) {}
+
+static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+	bool keep_ap_pll)
 {
 	return 0;
 }
 
-static inline int prcmu_enable_dsipll(void)
+static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
+
+static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
 {
 	return 0;
 }
-#endif
 
-static inline int prcmu_enable_spi2(void)
+static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
 {
 	return 0;
 }
 
-static inline int prcmu_disable_spi2(void)
+static inline int db8500_prcmu_set_display_clocks(void)
 {
 	return 0;
 }
 
-static inline void db8500_prcmu_system_reset(u16 reset_code) {}
+static inline int db8500_prcmu_disable_dsipll(void)
+{
+	return 0;
+}
 
-static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
-	bool keep_ap_pll)
+static inline int db8500_prcmu_enable_dsipll(void)
 {
 	return 0;
 }
 
-static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
+static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
+{
+	return 0;
+}
 
-static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
+static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
+
+static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
+
+static inline u16 db8500_prcmu_get_reset_code(void)
 {
 	return 0;
 }
 
-static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
+static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
+{
+	return 0;
+}
+
+static inline int prcmu_enable_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_disable_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_kick_a9wdog(u8 id)
+{
+	return 0;
+}
+
+static inline int prcmu_load_a9wdog(u8 id, u32 val)
+{
+	return 0;
+}
+
+static inline bool db8500_prcmu_is_ac_wake_requested(void)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_set_arm_opp(u8 opp)
+{
+	return 0;
+}
+
+static inline int db8500_prcmu_get_arm_opp(void)
 {
 	return 0;
 }