diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-ux500/Kconfig-arch | 4 | ||||
-rw-r--r-- | arch/arm/mach-ux500/devices-db5500.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-ux500/devices-db8500.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-ux500/prcmu-db5500.c | 8 | ||||
-rw-r--r-- | arch/arm/mach-ux500/prcmu-db8500.c | 9 |
5 files changed, 25 insertions, 2 deletions
diff --git a/arch/arm/mach-ux500/Kconfig-arch b/arch/arm/mach-ux500/Kconfig-arch index 013c76d8e74..a3ea7ad3d78 100644 --- a/arch/arm/mach-ux500/Kconfig-arch +++ b/arch/arm/mach-ux500/Kconfig-arch @@ -13,6 +13,7 @@ menu "Display selection" config DISPLAY_GENERIC_PRIMARY bool "Generic primary display support" depends on (MACH_U8500 || MACH_U5500) + select MCDE_DISPLAY_DSI default y choice @@ -98,6 +99,7 @@ config DISPLAY_GENERIC_DSI_PRIMARY_AUTO_SYNC config DISPLAY_SONY_ACX424AKP_DSI_PRIMARY bool "Sony acx424akp DSI display" select MCDE_DISPLAY_SONY_ACX424AKP_DSI + select MCDE_DISPLAY_DSI help Say yes here when using a sony acx424akp DSI display @@ -105,6 +107,7 @@ config DISPLAY_GENERIC_DSI_SECONDARY bool "Sub display support" depends on MACH_U8500 select MCDE_DISPLAY_GENERIC_DSI + select MCDE_DISPLAY_DSI help Say yes here if sub display exists @@ -131,6 +134,7 @@ config DISPLAY_AV8100_TERTIARY bool "AV8100 HDMI/CVBS display support" depends on (MACH_U8500 || MACH_U5500) select MCDE_DISPLAY_AV8100 + select MCDE_DISPLAY_DSI help Say yes here if HDMI output support diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c index 641f037f102..3f614b493b7 100644 --- a/arch/arm/mach-ux500/devices-db5500.c +++ b/arch/arm/mach-ux500/devices-db5500.c @@ -209,8 +209,10 @@ static struct mcde_platform_data mcde_pdata = { .num_overlays = 3, .regulator_mcde_epod_id = "vsupply", .regulator_esram_epod_id = "v-esram12", +#ifdef CONFIG_MCDE_DISPLAY_DSI .clock_dsi_id = "hdmi", .clock_dsi_lp_id = "tv", +#endif .clock_mcde_id = "mcde", .platform_set_clocks = mcde_platform_set_display_clocks, .platform_enable_dsipll = mcde_platform_enable_dsipll, diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 08bff83cac7..014945ade4e 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -223,11 +223,15 @@ static struct mcde_platform_data mcde_pdata = { .syncmux = 0x00, /* DPI channel A and B on output pins A and B resp */ .num_channels = 4, .num_overlays = 6, +#ifdef CONFIG_MCDE_DISPLAY_DSI .regulator_vana_id = "v-ana", +#endif .regulator_mcde_epod_id = "vsupply", .regulator_esram_epod_id = "v-esram34", +#ifdef CONFIG_MCDE_DISPLAY_DSI .clock_dsi_id = "hdmi", .clock_dsi_lp_id = "tv", +#endif .clock_dpi_id = "lcd", .clock_mcde_id = "mcde", .platform_set_clocks = mcde_platform_set_display_clocks, diff --git a/arch/arm/mach-ux500/prcmu-db5500.c b/arch/arm/mach-ux500/prcmu-db5500.c index 3293596572a..6c71981912b 100644 --- a/arch/arm/mach-ux500/prcmu-db5500.c +++ b/arch/arm/mach-ux500/prcmu-db5500.c @@ -1448,6 +1448,7 @@ int prcmu_resetout(u8 resoutn, u8 state) int prcmu_enable_dsipll(void) { int i; + int ret = 0; /* Enable DSIPLL_RESETN resets */ writel(PRCMU_RESET_DSIPLL, _PRCMU_BASE + PRCM_APE_RESETN_CLR); @@ -1470,9 +1471,14 @@ int prcmu_enable_dsipll(void) break; udelay(100); } + + if ((readl(_PRCMU_BASE + PRCM_PLLDSI_LOCKP) & + PRCMU_PLLDSI_LOCKP_LOCKED) + != PRCMU_PLLDSI_LOCKP_LOCKED) + ret = -EIO; /* Release DSIPLL_RESETN */ writel(PRCMU_RESET_DSIPLL, _PRCMU_BASE + PRCM_APE_RESETN_SET); - return 0; + return ret; } int prcmu_disable_dsipll(void) diff --git a/arch/arm/mach-ux500/prcmu-db8500.c b/arch/arm/mach-ux500/prcmu-db8500.c index 9744018c7fd..b19b334d234 100644 --- a/arch/arm/mach-ux500/prcmu-db8500.c +++ b/arch/arm/mach-ux500/prcmu-db8500.c @@ -559,6 +559,7 @@ static struct { int prcmu_enable_dsipll(void) { int i; + int ret = 0; unsigned int plldsifreq; /* Clear DSIPLL_RESETN */ @@ -589,9 +590,15 @@ int prcmu_enable_dsipll(void) break; udelay(100); } + + if ((readl(_PRCMU_BASE + PRCM_PLLDSI_LOCKP) & + PRCMU_PLLDSI_LOCKP_LOCKED) + != PRCMU_PLLDSI_LOCKP_LOCKED) + ret = -EIO; + /* Set DSIPLL_RESETN */ writel(PRCMU_RESET_DSIPLL, (_PRCMU_BASE + PRCM_APE_RESETN_SET)); - return 0; + return ret; } int prcmu_disable_dsipll(void) |