From f1cb9eba5b0ae36b2065b27cff1a5330f5a08da4 Mon Sep 17 00:00:00 2001 From: Sandeep Patil Date: Tue, 21 Oct 2008 14:06:24 +0100 Subject: [ARM] S3C24A0: Correct S3C2410_PA_GPIO in S3C24XX_VA_GPIO The definition of S3C24XX_VA_GPIO used S3C2410_PA_GPIO where it should have read S3C24XX_PA_GPIO. Signed-off-by: Sandeep Patil Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-s3c2410') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 23c470c2e5b..6e08594d716 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -88,7 +88,7 @@ */ #define S3C2410_PA_GPIO (0x56000000) -#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) +#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) #define S3C24XX_SZ_GPIO SZ_1M /* RTC */ -- cgit v1.2.3 From ce46a9c497ed788146449c230765ee5d6dd3cb53 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:06:26 +0100 Subject: [ARM] S3C24XX: Split map.h into plat-s3c24xx and mach-s3c2410 Split the map.h definitions into common S3C24XX code by adding arch/arm/plat-s3c24xx/include/plat/map.h and altering the machine specific header for the S3C24A0. As we add a new we move the original one in arch/arm/plat-s3c include directory to be called map-base.h to distinguish the two files. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 80 +------------------------ arch/arm/mach-s3c24a0/include/mach/map.h | 5 ++ arch/arm/plat-s3c/include/plat/map-base.h | 40 +++++++++++++ arch/arm/plat-s3c/include/plat/map.h | 40 ------------- arch/arm/plat-s3c24xx/devs.c | 8 +-- arch/arm/plat-s3c24xx/include/plat/map.h | 99 +++++++++++++++++++++++++++++++ 6 files changed, 151 insertions(+), 121 deletions(-) create mode 100644 arch/arm/plat-s3c/include/plat/map-base.h delete mode 100644 arch/arm/plat-s3c/include/plat/map.h create mode 100644 arch/arm/plat-s3c24xx/include/plat/map.h (limited to 'arch/arm/mach-s3c2410') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 6e08594d716..6b30361a080 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -13,34 +13,20 @@ #ifndef __ASM_ARCH_MAP_H #define __ASM_ARCH_MAP_H +#include #include #define S3C2410_ADDR(x) S3C_ADDR(x) -/* interrupt controller is the first thing we put in, to make - * the assembly code for the irq detection easier - */ -#define S3C24XX_VA_IRQ S3C_VA_IRQ -#define S3C2410_PA_IRQ (0x4A000000) -#define S3C24XX_SZ_IRQ SZ_1M - -/* memory controller registers */ -#define S3C24XX_VA_MEMCTRL S3C_VA_MEM -#define S3C2410_PA_MEMCTRL (0x48000000) -#define S3C24XX_SZ_MEMCTRL SZ_1M - /* USB host controller */ #define S3C2410_PA_USBHOST (0x49000000) -#define S3C24XX_SZ_USBHOST SZ_1M /* DMA controller */ #define S3C2410_PA_DMA (0x4B000000) #define S3C24XX_SZ_DMA SZ_1M /* Clock and Power management */ -#define S3C24XX_VA_CLKPWR S3C_VA_SYS #define S3C2410_PA_CLKPWR (0x4C000000) -#define S3C24XX_SZ_CLKPWR SZ_1M /* LCD controller */ #define S3C2410_PA_LCD (0x4D000000) @@ -48,48 +34,12 @@ /* NAND flash controller */ #define S3C2410_PA_NAND (0x4E000000) -#define S3C24XX_SZ_NAND SZ_1M - -/* UARTs */ -#define S3C24XX_VA_UART S3C_VA_UART -#define S3C2410_PA_UART (0x50000000) -#define S3C24XX_SZ_UART SZ_1M - -/* Timers */ -#define S3C24XX_VA_TIMER S3C_VA_TIMER -#define S3C2410_PA_TIMER (0x51000000) -#define S3C24XX_SZ_TIMER SZ_1M - -/* USB Device port */ -#define S3C2410_PA_USBDEV (0x52000000) -#define S3C24XX_SZ_USBDEV SZ_1M - -/* Watchdog */ -#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG -#define S3C2410_PA_WATCHDOG (0x53000000) -#define S3C24XX_SZ_WATCHDOG SZ_1M /* IIC hardware controller */ #define S3C2410_PA_IIC (0x54000000) -#define S3C24XX_SZ_IIC SZ_1M /* IIS controller */ #define S3C2410_PA_IIS (0x55000000) -#define S3C24XX_SZ_IIS SZ_1M - -/* GPIO ports */ - -/* the calculation for the VA of this must ensure that - * it is the same distance apart from the UART in the - * phsyical address space, as the initial mapping for the IO - * is done as a 1:1 maping. This puts it (currently) at - * 0xFA800000, which is not in the way of any current mapping - * by the base system. -*/ - -#define S3C2410_PA_GPIO (0x56000000) -#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) -#define S3C24XX_SZ_GPIO SZ_1M /* RTC */ #define S3C2410_PA_RTC (0x57000000) @@ -97,15 +47,12 @@ /* ADC */ #define S3C2410_PA_ADC (0x58000000) -#define S3C24XX_SZ_ADC SZ_1M /* SPI */ #define S3C2410_PA_SPI (0x59000000) -#define S3C24XX_SZ_SPI SZ_1M /* SDI */ #define S3C2410_PA_SDI (0x5A000000) -#define S3C24XX_SZ_SDI SZ_1M /* CAMIF */ #define S3C2440_PA_CAMIF (0x4F000000) @@ -120,13 +67,6 @@ #define S3C2443_PA_HSMMC (0x4A800000) #define S3C2443_SZ_HSMMC (256) -/* ISA style IO, for each machine to sort out mappings for, if it - * implements it. We reserve two 16M regions for ISA. - */ - -#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) -#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) - /* physical addresses of all the chip-select areas */ #define S3C2410_CS0 (0x00000000) @@ -158,21 +98,7 @@ #define S3C24XX_PA_RTC S3C2410_PA_RTC #define S3C24XX_PA_ADC S3C2410_PA_ADC #define S3C24XX_PA_SPI S3C2410_PA_SPI - -/* deal with the registers that move under the 2412/2413 */ - -#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) -#ifndef __ASSEMBLY__ -extern void __iomem *s3c24xx_va_gpio2; -#endif -#ifdef CONFIG_CPU_S3C2412_ONLY -#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) -#else -#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 -#endif -#else -#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO -#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO -#endif +#define S3C24XX_PA_SDI S3C2410_PA_SDI +#define S3C24XX_PA_NAND S3C2410_PA_NAND #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h index 65a146fd78e..2ce1839de4e 100644 --- a/arch/arm/mach-s3c24a0/include/mach/map.h +++ b/arch/arm/mach-s3c24a0/include/mach/map.h @@ -14,6 +14,9 @@ #ifndef __ASM_ARCH_24A0_MAP_H #define __ASM_ARCH_24A0_MAP_H __FILE__ +#include +#include + #define S3C24A0_PA_IO_BASE (0x40000000) #define S3C24A0_PA_CLKPWR (0x40000000) #define S3C24A0_PA_IRQ (0x40200000) @@ -74,5 +77,7 @@ #define S3C24XX_PA_RTC S3C24A0_PA_RTC #define S3C24XX_PA_ADC S3C24A0_PA_ADC #define S3C24XX_PA_SPI S3C24A0_PA_SPI +#define S3C24XX_PA_SDI S3C24A0_PA_SDI +#define S3C24XX_PA_NAND S3C24A0_PA_NAND #endif /* __ASM_ARCH_24A0_MAP_H */ diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h new file mode 100644 index 00000000000..b84289d32a5 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/map-base.h @@ -0,0 +1,40 @@ +/* linux/include/asm-arm/plat-s3c/map.h + * + * Copyright 2003, 2007 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C - Memory map definitions (virtual addresses) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_MAP_H +#define __ASM_PLAT_MAP_H __FILE__ + +/* Fit all our registers in at 0xF4000000 upwards, trying to use as + * little of the VA space as possible so vmalloc and friends have a + * better chance of getting memory. + * + * we try to ensure stuff like the IRQ registers are available for + * an single MOVS instruction (ie, only 8 bits of set data) + */ + +#define S3C_ADDR_BASE (0xF4000000) + +#ifndef __ASSEMBLY__ +#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) +#else +#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) +#endif + +#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ +#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ +#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ +#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ +#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ +#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ + +#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/plat-s3c/include/plat/map.h b/arch/arm/plat-s3c/include/plat/map.h deleted file mode 100644 index b84289d32a5..00000000000 --- a/arch/arm/plat-s3c/include/plat/map.h +++ /dev/null @@ -1,40 +0,0 @@ -/* linux/include/asm-arm/plat-s3c/map.h - * - * Copyright 2003, 2007 Simtec Electronics - * http://armlinux.simtec.co.uk/ - * Ben Dooks - * - * S3C - Memory map definitions (virtual addresses) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_PLAT_MAP_H -#define __ASM_PLAT_MAP_H __FILE__ - -/* Fit all our registers in at 0xF4000000 upwards, trying to use as - * little of the VA space as possible so vmalloc and friends have a - * better chance of getting memory. - * - * we try to ensure stuff like the IRQ registers are available for - * an single MOVS instruction (ie, only 8 bits of set data) - */ - -#define S3C_ADDR_BASE (0xF4000000) - -#ifndef __ASSEMBLY__ -#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) -#else -#define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) -#endif - -#define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ -#define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ -#define S3C_VA_MEM S3C_ADDR(0x00200000) /* system control */ -#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ -#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ -#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ - -#endif /* __ASM_PLAT_MAP_H */ diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c index adf535aaf43..ea445850ff4 100644 --- a/arch/arm/plat-s3c24xx/devs.c +++ b/arch/arm/plat-s3c24xx/devs.c @@ -192,8 +192,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd) static struct resource s3c_nand_resource[] = { [0] = { - .start = S3C2410_PA_NAND, - .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1, + .start = S3C24XX_PA_NAND, + .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1, .flags = IORESOURCE_MEM, } }; @@ -382,8 +382,8 @@ struct platform_device s3c_device_adc = { static struct resource s3c_sdi_resource[] = { [0] = { - .start = S3C2410_PA_SDI, - .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1, + .start = S3C24XX_PA_SDI, + .end = S3C24XX_PA_SDI + S3C24XX_SZ_SDI - 1, .flags = IORESOURCE_MEM, }, [1] = { diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h new file mode 100644 index 00000000000..6222ba8341d --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/map.h @@ -0,0 +1,99 @@ +/* linux/include/asm-arm/plat-s3c24xx/map.h + * + * Copyright (c) 2008 Simtec Electronics + * Ben Dooks + * + * S3C24XX - Memory map definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_PLAT_S3C24XX_MAP_H +#define __ASM_PLAT_S3C24XX_MAP_H + +/* interrupt controller is the first thing we put in, to make + * the assembly code for the irq detection easier + */ +#define S3C24XX_VA_IRQ S3C_VA_IRQ +#define S3C2410_PA_IRQ (0x4A000000) +#define S3C24XX_SZ_IRQ SZ_1M + +/* memory controller registers */ +#define S3C24XX_VA_MEMCTRL S3C_VA_MEM +#define S3C2410_PA_MEMCTRL (0x48000000) +#define S3C24XX_SZ_MEMCTRL SZ_1M + +/* UARTs */ +#define S3C24XX_VA_UART S3C_VA_UART +#define S3C2410_PA_UART (0x50000000) +#define S3C24XX_SZ_UART SZ_1M + +/* Timers */ +#define S3C24XX_VA_TIMER S3C_VA_TIMER +#define S3C2410_PA_TIMER (0x51000000) +#define S3C24XX_SZ_TIMER SZ_1M + +/* Clock and Power management */ +#define S3C24XX_VA_CLKPWR S3C_VA_SYS +#define S3C24XX_SZ_CLKPWR SZ_1M + +/* USB Device port */ +#define S3C2410_PA_USBDEV (0x52000000) +#define S3C24XX_SZ_USBDEV SZ_1M + +/* Watchdog */ +#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG +#define S3C2410_PA_WATCHDOG (0x53000000) +#define S3C24XX_SZ_WATCHDOG SZ_1M + +/* Standard size definitions for peripheral blocks. */ + +#define S3C24XX_SZ_IIC SZ_1M +#define S3C24XX_SZ_IIS SZ_1M +#define S3C24XX_SZ_ADC SZ_1M +#define S3C24XX_SZ_SPI SZ_1M +#define S3C24XX_SZ_SDI SZ_1M +#define S3C24XX_SZ_NAND SZ_1M +#define S3C24XX_SZ_USBHOST SZ_1M + +/* GPIO ports */ + +/* the calculation for the VA of this must ensure that + * it is the same distance apart from the UART in the + * phsyical address space, as the initial mapping for the IO + * is done as a 1:1 maping. This puts it (currently) at + * 0xFA800000, which is not in the way of any current mapping + * by the base system. +*/ + +#define S3C2410_PA_GPIO (0x56000000) +#define S3C24XX_VA_GPIO ((S3C24XX_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART) +#define S3C24XX_SZ_GPIO SZ_1M + + +/* ISA style IO, for each machine to sort out mappings for, if it + * implements it. We reserve two 16M regions for ISA. + */ + +#define S3C24XX_VA_ISA_WORD S3C2410_ADDR(0x02000000) +#define S3C24XX_VA_ISA_BYTE S3C2410_ADDR(0x03000000) + +/* deal with the registers that move under the 2412/2413 */ + +#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413) +#ifndef __ASSEMBLY__ +extern void __iomem *s3c24xx_va_gpio2; +#endif +#ifdef CONFIG_CPU_S3C2412_ONLY +#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10) +#else +#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2 +#endif +#else +#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO +#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO +#endif + +#endif /* __ASM_PLAT_S3C24XX_MAP_H */ -- cgit v1.2.3 From 9bc1aaeac0118611c30edf84995ebad5adfd6822 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:06:35 +0100 Subject: [ARM] S3C24XX: Split timer pending code out Split the timer pending code out to a seperate per-machine header so that when compiling for mach-s3c2410 or mach-s3c24a0 we can use the right timer code without having to #ifdef the timer driver. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/tick.h | 15 +++++++++++++++ arch/arm/mach-s3c24a0/include/mach/tick.h | 15 +++++++++++++++ arch/arm/plat-s3c/time.c | 7 ++----- 3 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 arch/arm/mach-s3c2410/include/mach/tick.h create mode 100644 arch/arm/mach-s3c24a0/include/mach/tick.h (limited to 'arch/arm/mach-s3c2410') diff --git a/arch/arm/mach-s3c2410/include/mach/tick.h b/arch/arm/mach-s3c2410/include/mach/tick.h new file mode 100644 index 00000000000..544da41979d --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/tick.h @@ -0,0 +1,15 @@ +/* linux/arch/arm/mach-s3c2410/include/mach/tick.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C2410 - timer tick support + */ + +#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) + +static inline int s3c24xx_ostimer_pending(void) +{ + return __raw_readl(S3C2410_SRCPND) & SRCPND_TIMER4; +} diff --git a/arch/arm/mach-s3c24a0/include/mach/tick.h b/arch/arm/mach-s3c24a0/include/mach/tick.h new file mode 100644 index 00000000000..9dea8ba6fb7 --- /dev/null +++ b/arch/arm/mach-s3c24a0/include/mach/tick.h @@ -0,0 +1,15 @@ +/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h + * + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * S3C24A0 - timer tick support + */ + +#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0)) + +static inline int s3c24xx_ostimer_pending(void) +{ + return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4; +} diff --git a/arch/arm/plat-s3c/time.c b/arch/arm/plat-s3c/time.c index c6861a05a29..d35e149f4eb 100644 --- a/arch/arm/plat-s3c/time.c +++ b/arch/arm/plat-s3c/time.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -91,12 +92,9 @@ static inline unsigned long timer_ticks_to_usec(unsigned long ticks) * IRQs are disabled before entering here from do_gettimeofday() */ -#define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0)) - static unsigned long s3c2410_gettimeoffset (void) { unsigned long tdone; - unsigned long irqpend; unsigned long tval; /* work out how many ticks have gone since last timer interrupt */ @@ -106,8 +104,7 @@ static unsigned long s3c2410_gettimeoffset (void) /* check to see if there is an interrupt pending */ - irqpend = __raw_readl(S3C2410_SRCPND); - if (irqpend & SRCPND_TIMER4) { + if (s3c24xx_ostimer_pending()) { /* re-read the timer, and try and fix up for the missed * interrupt. Note, the interrupt may go off before the * timer has re-loaded from wrapping. -- cgit v1.2.3 From e1a2bd1d2f368faaf377fdf8404a685280a3d0a3 Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:06:45 +0100 Subject: [ARM] S3C64XX: Add system boot-time support Add the necessary defines for to function and build an working header code block. Signed-off-by: Ben Doioks --- arch/arm/mach-s3c2410/include/mach/uncompress.h | 1 + arch/arm/mach-s3c6400/include/mach/uncompress.h | 26 +++++++++++++++++++++++++ arch/arm/plat-s3c/include/plat/uncompress.h | 2 +- arch/arm/plat-s3c24xx/include/plat/map.h | 1 + 4 files changed, 29 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-s3c6400/include/mach/uncompress.h (limited to 'arch/arm/mach-s3c2410') diff --git a/arch/arm/mach-s3c2410/include/mach/uncompress.h b/arch/arm/mach-s3c2410/include/mach/uncompress.h index ab39491beee..c9432103750 100644 --- a/arch/arm/mach-s3c2410/include/mach/uncompress.h +++ b/arch/arm/mach-s3c2410/include/mach/uncompress.h @@ -1,3 +1,4 @@ + /* arch/arm/mach-s3c2410/include/mach/uncompress.h * * Copyright (c) 2003, 2007 Simtec Electronics diff --git a/arch/arm/mach-s3c6400/include/mach/uncompress.h b/arch/arm/mach-s3c6400/include/mach/uncompress.h new file mode 100644 index 00000000000..cc822c57cc1 --- /dev/null +++ b/arch/arm/mach-s3c6400/include/mach/uncompress.h @@ -0,0 +1,26 @@ +/* arch/arm/mach-s3c6400/include/mach/uncompress.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * http://armlinux.simtec.co.uk/ + * Ben Dooks + * + * S3C6400 - uncompress code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __ASM_ARCH_UNCOMPRESS_H +#define __ASM_ARCH_UNCOMPRESS_H + +#include +#include + +static void arch_detect_cpu(void) +{ + /* we do not need to do any cpu detection here at the moment. */ +} + +#endif /* __ASM_ARCH_UNCOMPRESS_H */ diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index 8a8a927292e..eeef32c4312 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h @@ -37,7 +37,7 @@ static void arch_detect_cpu(void); /* how many bytes we allow into the FIFO at a time in FIFO mode */ #define FIFO_MAX (14) -#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT) +#define uart_base S3C_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT) static __inline__ void uart_wr(unsigned int reg, unsigned int val) diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h index 6222ba8341d..e7be0c0d370 100644 --- a/arch/arm/plat-s3c24xx/include/plat/map.h +++ b/arch/arm/plat-s3c24xx/include/plat/map.h @@ -29,6 +29,7 @@ #define S3C24XX_VA_UART S3C_VA_UART #define S3C2410_PA_UART (0x50000000) #define S3C24XX_SZ_UART SZ_1M +#define S3C_UART_OFFSET (0x4000) /* Timers */ #define S3C24XX_VA_TIMER S3C_VA_TIMER -- cgit v1.2.3 From b690ace50be7d10d77cb7a6d5ef1bd9de649852f Mon Sep 17 00:00:00 2001 From: Ben Dooks Date: Tue, 21 Oct 2008 14:07:03 +0100 Subject: [ARM] S3C6400: serial support for S3C6400 and S3C6410 SoCs Add support to the Samsung serial driver for the S3C6400 and S3C6410 serial ports. Signed-off-by: Ben Dooks --- arch/arm/mach-s3c2410/include/mach/map.h | 2 + arch/arm/mach-s3c24a0/include/mach/map.h | 2 + arch/arm/plat-s3c/include/plat/regs-serial.h | 6 ++ drivers/serial/Kconfig | 10 +- drivers/serial/Makefile | 1 + drivers/serial/s3c6400.c | 151 +++++++++++++++++++++++++++ drivers/serial/samsung.c | 8 +- include/linux/serial_core.h | 2 + 8 files changed, 178 insertions(+), 4 deletions(-) create mode 100644 drivers/serial/s3c6400.c (limited to 'arch/arm/mach-s3c2410') diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h index 6b30361a080..918e3463297 100644 --- a/arch/arm/mach-s3c2410/include/mach/map.h +++ b/arch/arm/mach-s3c2410/include/mach/map.h @@ -101,4 +101,6 @@ #define S3C24XX_PA_SDI S3C2410_PA_SDI #define S3C24XX_PA_NAND S3C2410_PA_NAND +#define S3C_PA_UART S3C24XX_PA_UART + #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h index 2ce1839de4e..6667355a47a 100644 --- a/arch/arm/mach-s3c24a0/include/mach/map.h +++ b/arch/arm/mach-s3c24a0/include/mach/map.h @@ -80,4 +80,6 @@ #define S3C24XX_PA_SDI S3C24A0_PA_SDI #define S3C24XX_PA_NAND S3C24A0_PA_NAND +#define S3C_PA_UART S3C24A0_PA_UART + #endif /* __ASM_ARCH_24A0_MAP_H */ diff --git a/arch/arm/plat-s3c/include/plat/regs-serial.h b/arch/arm/plat-s3c/include/plat/regs-serial.h index 18ba31c7174..3ca28585cf8 100644 --- a/arch/arm/plat-s3c/include/plat/regs-serial.h +++ b/arch/arm/plat-s3c/include/plat/regs-serial.h @@ -77,6 +77,12 @@ #define S3C2440_UCON_FCLK (3<<10) #define S3C2443_UCON_EPLL (3<<10) +#define S3C6400_UCON_CLKMASK (3<<10) +#define S3C6400_UCON_PCLK (0<<10) +#define S3C6400_UCON_PCLK2 (2<<10) +#define S3C6400_UCON_UCLK0 (1<<10) +#define S3C6400_UCON_UCLK1 (3<<10) + #define S3C2440_UCON2_FCLK_EN (1<<15) #define S3C2440_UCON0_DIVMASK (15 << 12) #define S3C2440_UCON1_DIVMASK (15 << 12) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index f71a2e8a5f6..e4ae499e587 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -447,7 +447,7 @@ config SERIAL_CLPS711X_CONSOLE config SERIAL_SAMSUNG tristate "Samsung SoC serial support" - depends on ARM && PLAT_S3C24XX + depends on ARM && PLAT_S3C select SERIAL_CORE help Support for the on-chip UARTs on the Samsung S3C24XX series CPUs, @@ -515,6 +515,14 @@ config SERIAL_S3C24A0 help Serial port support for the Samsung S3C24A0 SoC +config SERIAL_S3C6400 + tristate "Samsung S3C6400/S3C6410 Serial port support" + depends on SERIAL_SAMSUNG && (CPU_S3C600 || CPU_S3C6410) + default y + help + Serial port support for the Samsung S3C6400 and S3C6410 + SoCs + config SERIAL_DZ bool "DECstation DZ serial driver" depends on MACH_DECSTATION && 32BIT diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 7769aece54c..dfe775ac45b 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o +obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o obj-$(CONFIG_SERIAL_MUX) += mux.o obj-$(CONFIG_SERIAL_68328) += 68328serial.o diff --git a/drivers/serial/s3c6400.c b/drivers/serial/s3c6400.c new file mode 100644 index 00000000000..06936d13393 --- /dev/null +++ b/drivers/serial/s3c6400.c @@ -0,0 +1,151 @@ +/* linux/drivers/serial/s3c6400.c + * + * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs. + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks + * http://armlinux.simtec.co.uk/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "samsung.h" + +static int s3c6400_serial_setsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + if (strcmp(clk->name, "uclk0") == 0) { + ucon &= ~S3C6400_UCON_CLKMASK; + ucon |= S3C6400_UCON_UCLK0; + } else if (strcmp(clk->name, "uclk1") == 0) + ucon |= S3C6400_UCON_UCLK1; + else if (strcmp(clk->name, "pclk") == 0) { + /* See notes about transitioning from UCLK to PCLK */ + ucon &= ~S3C6400_UCON_UCLK0; + } else { + printk(KERN_ERR "unknown clock source %s\n", clk->name); + return -EINVAL; + } + + wr_regl(port, S3C2410_UCON, ucon); + return 0; +} + + +static int s3c6400_serial_getsource(struct uart_port *port, + struct s3c24xx_uart_clksrc *clk) +{ + u32 ucon = rd_regl(port, S3C2410_UCON); + + clk->divisor = 1; + + switch (ucon & S3C6400_UCON_CLKMASK) { + case S3C6400_UCON_UCLK0: + clk->name = "uclk0"; + break; + + case S3C6400_UCON_UCLK1: + clk->name = "uclk1"; + break; + + case S3C6400_UCON_PCLK: + case S3C6400_UCON_PCLK2: + clk->name = "pclk"; + break; + } + + return 0; +} + +static int s3c6400_serial_resetport(struct uart_port *port, + struct s3c2410_uartcfg *cfg) +{ + unsigned long ucon = rd_regl(port, S3C2410_UCON); + + dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n", + port, port->mapbase, cfg); + + /* ensure we don't change the clock settings... */ + + ucon &= S3C6400_UCON_CLKMASK; + + wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); + wr_regl(port, S3C2410_ULCON, cfg->ulcon); + + /* reset both fifos */ + + wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); + wr_regl(port, S3C2410_UFCON, cfg->ufcon); + + return 0; +} + +static struct s3c24xx_uart_info s3c6400_uart_inf = { + .name = "Samsung S3C6400 UART", + .type = PORT_S3C6400, + .fifosize = 64, + .rx_fifomask = S3C2440_UFSTAT_RXMASK, + .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, + .rx_fifofull = S3C2440_UFSTAT_RXFULL, + .tx_fifofull = S3C2440_UFSTAT_TXFULL, + .tx_fifomask = S3C2440_UFSTAT_TXMASK, + .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, + .get_clksrc = s3c6400_serial_getsource, + .set_clksrc = s3c6400_serial_setsource, + .reset_port = s3c6400_serial_resetport, +}; + +/* device management */ + +static int s3c6400_serial_probe(struct platform_device *dev) +{ + dbg("s3c6400_serial_probe: dev=%p\n", dev); + return s3c24xx_serial_probe(dev, &s3c6400_uart_inf); +} + +static struct platform_driver s3c6400_serial_drv = { + .probe = s3c6400_serial_probe, + .remove = s3c24xx_serial_remove, + .driver = { + .name = "s3c6400-uart", + .owner = THIS_MODULE, + }, +}; + +s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf); + +static int __init s3c6400_serial_init(void) +{ + return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf); +} + +static void __exit s3c6400_serial_exit(void) +{ + platform_driver_unregister(&s3c6400_serial_drv); +} + +module_init(s3c6400_serial_init); +module_exit(s3c6400_serial_exit); + +MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver"); +MODULE_AUTHOR("Ben Dooks "); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:s3c6400-uart"); diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c index bb8b57aae3a..44fc38afa22 100644 --- a/drivers/serial/samsung.c +++ b/drivers/serial/samsung.c @@ -47,9 +47,9 @@ #include #include +#include #include -#include #include "samsung.h" @@ -756,6 +756,8 @@ static const char *s3c24xx_serial_type(struct uart_port *port) return "S3C2440"; case PORT_S3C2412: return "S3C2412"; + case PORT_S3C6400: + return "S3C6400/10"; default: return NULL; } @@ -1034,8 +1036,8 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); - port->mapbase = res->start; - port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART); + port->mapbase = res->start; + port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000); ret = platform_get_irq(platdev, 0); if (ret < 0) port->irq = 0; diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 4e4f1277f3b..feb3b939ec4 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -158,6 +158,8 @@ /* SH-SCI */ #define PORT_SCIFA 83 +#define PORT_S3C6400 84 + #ifdef __KERNEL__ #include -- cgit v1.2.3