From 52e3134423c3af4431fedb34f77e31cfff91e0c3 Mon Sep 17 00:00:00 2001 From: David Brownell Date: Mon, 3 Mar 2008 12:43:23 -0800 Subject: ARM: OMAP: Use gpiolib Update OMAP to use the new GPIO implementation framework. This is just a quick'n'dirty update ... more code could now be removed, ideally as part of cleaning up the entire OMAP GPIO infrastructure ... Signed-off-by: David Brownell Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 107 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 89 insertions(+), 18 deletions(-) (limited to 'arch/arm/plat-omap/gpio.c') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8c78e4e57b5..56889fdb074 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -136,7 +136,6 @@ struct gpio_bank { u16 irq; u16 virtual_irq_start; int method; - u32 reserved_map; #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) u32 suspend_wakeup; u32 saved_wakeup; @@ -150,6 +149,7 @@ struct gpio_bank { u32 saved_risingdetect; #endif spinlock_t lock; + struct gpio_chip chip; }; #define METHOD_MPUIO 0 @@ -903,19 +903,17 @@ int omap_request_gpio(int gpio) { struct gpio_bank *bank; unsigned long flags; + int status; if (check_gpio(gpio) < 0) return -EINVAL; + status = gpio_request(gpio, NULL); + if (status < 0) + return status; + bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); - if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) { - printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio); - dump_stack(); - spin_unlock_irqrestore(&bank->lock, flags); - return -1; - } - bank->reserved_map |= (1 << get_gpio_index(gpio)); /* Set trigger to none. You need to enable the desired trigger with * request_irq() or set_irq_type(). @@ -945,10 +943,11 @@ void omap_free_gpio(int gpio) return; bank = get_gpio_bank(gpio); spin_lock_irqsave(&bank->lock, flags); - if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) { + if (unlikely(!gpiochip_is_requested(&bank->chip, + get_gpio_index(gpio)))) { + spin_unlock_irqrestore(&bank->lock, flags); printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio); dump_stack(); - spin_unlock_irqrestore(&bank->lock, flags); return; } #ifdef CONFIG_ARCH_OMAP16XX @@ -965,9 +964,9 @@ void omap_free_gpio(int gpio) __raw_writel(1 << get_gpio_index(gpio), reg); } #endif - bank->reserved_map &= ~(1 << get_gpio_index(gpio)); _reset_gpio(bank, gpio); spin_unlock_irqrestore(&bank->lock, flags); + gpio_free(gpio); } /* @@ -1266,6 +1265,53 @@ static inline void mpuio_init(void) {} /*---------------------------------------------------------------------*/ +/* REVISIT these are stupid implementations! replace by ones that + * don't switch on METHOD_* and which mostly avoid spinlocks + */ + +static int gpio_input(struct gpio_chip *chip, unsigned offset) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_direction(bank, offset, 1); + spin_unlock_irqrestore(&bank->lock, flags); + return 0; +} + +static int gpio_get(struct gpio_chip *chip, unsigned offset) +{ + return omap_get_gpio_datain(chip->base + offset); +} + +static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_dataout(bank, offset, value); + _set_gpio_direction(bank, offset, 0); + spin_unlock_irqrestore(&bank->lock, flags); + return 0; +} + +static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) +{ + struct gpio_bank *bank; + unsigned long flags; + + bank = container_of(chip, struct gpio_bank, chip); + spin_lock_irqsave(&bank->lock, flags); + _set_gpio_dataout(bank, offset, value); + spin_unlock_irqrestore(&bank->lock, flags); +} + +/*---------------------------------------------------------------------*/ + static int initialized; #if !defined(CONFIG_ARCH_OMAP3) static struct clk * gpio_ick; @@ -1293,6 +1339,7 @@ static struct lock_class_key gpio_lock_class; static int __init _omap_gpio_init(void) { int i; + int gpio = 0; struct gpio_bank *bank; #if defined(CONFIG_ARCH_OMAP3) char clk_name[11]; @@ -1423,7 +1470,6 @@ static int __init _omap_gpio_init(void) int j, gpio_count = 16; bank = &gpio_bank[i]; - bank->reserved_map = 0; bank->base = IO_ADDRESS(bank->base); spin_lock_init(&bank->lock); if (bank_is_mpuio(bank)) @@ -1461,6 +1507,26 @@ static int __init _omap_gpio_init(void) gpio_count = 32; } #endif + + /* REVISIT eventually switch from OMAP-specific gpio structs + * over to the generic ones + */ + bank->chip.direction_input = gpio_input; + bank->chip.get = gpio_get; + bank->chip.direction_output = gpio_output; + bank->chip.set = gpio_set; + if (bank_is_mpuio(bank)) { + bank->chip.label = "mpuio"; + bank->chip.base = OMAP_MPUIO(0); + } else { + bank->chip.label = "gpio"; + bank->chip.base = gpio; + gpio += gpio_count; + } + bank->chip.ngpio = gpio_count; + + gpiochip_add(&bank->chip); + for (j = bank->virtual_irq_start; j < bank->virtual_irq_start + gpio_count; j++) { lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class); @@ -1757,8 +1823,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { unsigned irq, value, is_in, irqstat; + const char *label; - if (!(bank->reserved_map & mask)) + label = gpiochip_is_requested(&bank->chip, j); + if (!label) continue; irq = bank->virtual_irq_start + j; @@ -1766,13 +1834,16 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) is_in = gpio_is_input(bank, mask); if (bank_is_mpuio(bank)) - seq_printf(s, "MPUIO %2d: ", j); + seq_printf(s, "MPUIO %2d ", j); else - seq_printf(s, "GPIO %3d: ", gpio); - seq_printf(s, "%s %s", + seq_printf(s, "GPIO %3d ", gpio); + seq_printf(s, "(%10s): %s %s", + label, is_in ? "in " : "out", value ? "hi" : "lo"); +/* FIXME for at least omap2, show pullup/pulldown state */ + irqstat = irq_desc[irq].status; if (is_in && ((bank->suspend_wakeup & mask) || irqstat & IRQ_TYPE_SENSE_MASK)) { @@ -1795,10 +1866,10 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) trigger = "high"; break; case IRQ_TYPE_NONE: - trigger = "(unspecified)"; + trigger = "(?)"; break; } - seq_printf(s, ", irq-%d %s%s", + seq_printf(s, ", irq-%d %-8s%s", irq, trigger, (bank->suspend_wakeup & mask) ? " wakeup" : ""); -- cgit v1.2.3 From b144ff6f3068602e5bbcefab888b97bcedb9b4a5 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 16 Jan 2008 21:56:15 -0800 Subject: ARM: OMAP: Clear level-triggered GPIO interrupts in unmask hook The clearing was moved to the unmask hook because it is known to run after the interrupt handler has actually run. Before this patch, if interrupts are threaded, the clearing/unmasking of level triggered interrupts would be done before the threaded handler actually ran. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'arch/arm/plat-omap/gpio.c') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 56889fdb074..4f104e4f6c0 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -148,6 +148,7 @@ struct gpio_bank { u32 saved_fallingdetect; u32 saved_risingdetect; #endif + u32 level_mask; spinlock_t lock; struct gpio_chip chip; }; @@ -538,6 +539,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, bank->enabled_non_wakeup_gpios &= ~gpio_bit; } + bank->level_mask = + __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | + __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); /* * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only * level triggering requested. @@ -1021,12 +1025,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) isr &= 0x0000ffff; if (cpu_class_is_omap2()) { - level_mask = - __raw_readl(bank->base + - OMAP24XX_GPIO_LEVELDETECT0) | - __raw_readl(bank->base + - OMAP24XX_GPIO_LEVELDETECT1); - level_mask &= enabled; + level_mask = bank->level_mask & enabled; } /* clear edge sensitive interrupts before handler(s) are @@ -1088,14 +1087,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) retrigger |= irq_mask; } } - - if (cpu_class_is_omap2()) { - /* clear level sensitive interrupts after handler(s) */ - _enable_gpio_irqbank(bank, isr_saved & level_mask, 0); - _clear_gpio_irqbank(bank, isr_saved & level_mask); - _enable_gpio_irqbank(bank, isr_saved & level_mask, 1); - } - } /* if bank has any level sensitive GPIO pin interrupt configured, we must unmask the bank interrupt only after @@ -1134,6 +1125,14 @@ static void gpio_unmask_irq(unsigned int irq) { unsigned int gpio = irq - IH_GPIO_BASE; struct gpio_bank *bank = get_irq_chip_data(irq); + unsigned int irq_mask = 1 << get_gpio_index(gpio); + + /* For level-triggered GPIOs, the clearing must be done after + * the HW source is cleared, thus after the handler has run */ + if (bank->level_mask & irq_mask) { + _set_gpio_irqenable(bank, gpio, 0); + _clear_gpio_irqstatus(bank, gpio); + } _set_gpio_irqenable(bank, gpio, 1); } -- cgit v1.2.3 From 672e302e3c04e40e7c236cb09159f593f24f5def Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 16 Jan 2008 21:56:16 -0800 Subject: ARM: OMAP: use edge/level handlers from generic IRQ framework Currently, the GPIO interrupt handling is duplicating some of the work done by the generic IRQ handlers (handle_edge_irq, handle_level_irq) such as detecting nesting, handling re-triggers etc. Remove this duplication and use generic hooks based on IRQ type. Using generic IRQ handlers ensures correct behavior when using threaded interrupts introduced by the -rt patch. Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 42 +++++++----------------------------------- 1 file changed, 7 insertions(+), 35 deletions(-) (limited to 'arch/arm/plat-omap/gpio.c') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 4f104e4f6c0..1903a3491ee 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -542,10 +542,6 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, bank->level_mask = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); - /* - * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only - * level triggering requested. - */ } #endif @@ -656,6 +652,12 @@ static int gpio_irq_type(unsigned irq, unsigned type) irq_desc[irq].status |= type; } spin_unlock_irqrestore(&bank->lock, flags); + + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) + __set_irq_handler_unlocked(irq, handle_level_irq); + else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + __set_irq_handler_unlocked(irq, handle_edge_irq); + return retval; } @@ -1050,42 +1052,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) gpio_irq = bank->virtual_irq_start; for (; isr != 0; isr >>= 1, gpio_irq++) { struct irq_desc *d; - int irq_mask; + if (!(isr & 1)) continue; d = irq_desc + gpio_irq; - /* Don't run the handler if it's already running - * or was disabled lazely. - */ - if (unlikely((d->depth || - (d->status & IRQ_INPROGRESS)))) { - irq_mask = 1 << - (gpio_irq - bank->virtual_irq_start); - /* The unmasking will be done by - * enable_irq in case it is disabled or - * after returning from the handler if - * it's already running. - */ - _enable_gpio_irqbank(bank, irq_mask, 0); - if (!d->depth) { - /* Level triggered interrupts - * won't ever be reentered - */ - BUG_ON(level_mask & irq_mask); - d->status |= IRQ_PENDING; - } - continue; - } desc_handle_irq(gpio_irq, d); - - if (unlikely((d->status & IRQ_PENDING) && !d->depth)) { - irq_mask = 1 << - (gpio_irq - bank->virtual_irq_start); - d->status &= ~IRQ_PENDING; - _enable_gpio_irqbank(bank, irq_mask, 1); - retrigger |= irq_mask; - } } } /* if bank has any level sensitive GPIO pin interrupt -- cgit v1.2.3