diff options
| author | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-06-06 11:42:13 +0200 |
| commit | c440bfe6d6d92d66478a7e84402b31f48413617b (patch) | |
| tree | 7919ffbc5fdf5a1bb7dddf066ae904aad1058135 /board/amcc/acadia/memory.c | |
| parent | e3cbe1f93c5722f8ebbad468e30c069a2b511097 (diff) | |
ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'board/amcc/acadia/memory.c')
| -rw-r--r-- | board/amcc/acadia/memory.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 5375d36c9..25904d3b9 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,6 +39,7 @@ void sdram_init(void) return; } +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val) return; } +#endif long int initdram(int board_type) { +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ @@ -92,7 +96,12 @@ long int initdram(int board_type) /* Config EBC to use RDY */ mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | 0x04000000); + mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + + /* Wait a short while, since for NAND booting this is too fast */ + for (i=0; i<200000; i++) + ; +#endif return (CFG_MBYTES_RAM << 20); } |