diff options
author | Mathieu J. Poirier <mathieu.poirier@linaro.org> | 2011-02-14 14:35:53 -0700 |
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committer | Mathieu J. Poirier <mathieu.poirier@linaro.org> | 2011-02-14 14:35:53 -0700 |
commit | 3240a1ab310fac143eef856a98bece96fa1a47ff (patch) | |
tree | 08408399a33a1f808cc1527d1cf2a4c2a3abbe4d /board/st | |
parent | 4035e3996f903064c91e6e1ce9b1328018c6a9d3 (diff) |
Adding base support for snowball.
- Initial pin configuration.
- Introduction of u8500_is_snowball.
- Introduction of new machine type.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Diffstat (limited to 'board/st')
-rw-r--r-- | board/st/u8500/u8500.c | 29 |
1 files changed, 23 insertions, 6 deletions
diff --git a/board/st/u8500/u8500.c b/board/st/u8500/u8500.c index 019d3fef4..43f21eed0 100644 --- a/board/st/u8500/u8500.c +++ b/board/st/u8500/u8500.c @@ -136,9 +136,20 @@ pin_cfg_t gpio_cfg_hrefv60[] = { GPIO66_GPIO | PIN_OUTPUT_LOW, /* DISP2 RST */ }; +pin_cfg_t gpio_cfg_snowball[] = { + /* MMC0 (MicroSD card) */ + GPIO217_GPIO | PIN_OUTPUT_HIGH, /* MMC_EN */ + GPIO218_GPIO | PIN_INPUT_NOPULL, /* MMC_CD */ + GPIO228_GPIO | PIN_OUTPUT_HIGH, /* SD_SEL */ + + /* eMMC */ + GPIO167_GPIO | PIN_OUTPUT_HIGH, /* RSTn_MLC */ +}; + #define BOARD_ID_MOP500 0 #define BOARD_ID_HREF 1 #define BOARD_ID_HREFV60 2 +#define BOARD_ID_SNOWBALL 3 int board_id; /* set in probe_href() */ int errno; @@ -338,17 +349,23 @@ static void probe_href(void) board_id = BOARD_ID_MOP500; else board_id = BOARD_ID_HREF; - } else + } else if(u8500_is_snowball()) { + gd->bd->bi_arch_number = MACH_TYPE_SNOWBALL; + + db8500_gpio_config_pins(gpio_cfg_snowball, + ARRAY_SIZE(gpio_cfg_snowball)); + + board_id = BOARD_ID_SNOWBALL; + } else{ /* No GPIOE => HREF+ 2.0 V60 or later */ gd->bd->bi_arch_number = MACH_TYPE_HREFV60; - } - if (gd->bd->bi_arch_number == MACH_TYPE_HREFV60) { - db8500_gpio_config_pins(gpio_cfg_hrefv60, + db8500_gpio_config_pins(gpio_cfg_hrefv60, + ARRAY_SIZE(gpio_cfg_hrefv60)); - board_id = BOARD_ID_HREFV60; + board_id = BOARD_ID_HREFV60; + } } - } #define BATT_OK_SEL1_TH_F_MASK 0xF0 |