diff options
| author | Andy Fleming <afleming@freescale.com> | 2008-10-30 16:50:14 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2009-02-16 18:07:43 -0600 |
| commit | e1ac387f4645499746856adc1aeaa9787da2eca6 (patch) | |
| tree | 2bb85a452ef20194a01d8954be714e6cc46d4e16 /board | |
| parent | 80522dc8369a89938369fbcee572e662373bc9a3 (diff) | |
83xx: Add eSDHC support on 8379 EMDS board
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'board')
| -rw-r--r-- | board/freescale/mpc837xemds/mpc837xemds.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c index 156d8089a..062d762d2 100644 --- a/board/freescale/mpc837xemds/mpc837xemds.c +++ b/board/freescale/mpc837xemds/mpc837xemds.c @@ -23,6 +23,7 @@ int board_early_init_f(void) { + struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR; u8 *bcsr = (u8 *)CONFIG_SYS_BCSR; /* Enable flash write */ @@ -30,6 +31,18 @@ int board_early_init_f(void) /* Clear all of the interrupt of BCSR */ bcsr[0xe] = 0xff; +#ifdef CONFIG_MMC + /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */ + bcsr[0xc] |= 0x4c; + + /* Set proper bits in SICR to allow SD signals through */ + clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD); + + clrsetbits_be32(&im->sysconf.sicrh, (SICRH_GPIO2_E | SICRH_SPI), + (SICRH_GPIO2_E_SD | SICRH_SPI_SD)); + +#endif + #ifdef CONFIG_FSL_SERDES immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; u32 spridr = in_be32(&immr->sysconf.spridr); @@ -38,21 +51,21 @@ int board_early_init_f(void) switch (PARTID_NO_E(spridr)) { case SPR_8377: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; case SPR_8378: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII, - FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V); break; case SPR_8379: fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA, - FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); break; default: printf("serdes not configured: unknown CPU part number: " - "%04x\n", spridr >> 16); + "%04x\n", spridr >> 16); break; } #endif /* CONFIG_FSL_SERDES */ |