diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-03-19 09:16:10 -0500 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-03-30 13:33:50 -0500 |
| commit | 1b3e4044a28a3d95b0aad41bdc52482bb2cc9b2b (patch) | |
| tree | e81d608df798c58a5d2a35204ef6891fb2bc0bd8 /cpu/mpc85xx/cpu_init.c | |
| parent | c360ceac0286159f94d9d1a9496fc9858c8d9bec (diff) | |
85xx: Add support for additional e500mc features
* Enable backside L2
* e500mc no longer has timebase enable in HID (moved to CCSR register)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'cpu/mpc85xx/cpu_init.c')
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 0b7c60971..c98dd8da5 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -345,6 +345,19 @@ int cpu_init_r(void) asm("msync;isync"); puts("enabled\n"); } +#elif defined(CONFIG_BACKSIDE_L2_CACHE) + u32 l2cfg0 = mfspr(SPRN_L2CFG0); + + /* invalidate the L2 cache */ + mtspr(SPRN_L2CSR0, L2CSR0_L2FI); + while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + ; + + /* enable the cache */ + mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0); + + if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) + printf("%d KB enabled\n", (l2cfg0 & 0x3fff) * 64); #else puts("disabled\n"); #endif |