diff options
author | Jon Loeliger <jdl@freescale.com> | 2005-08-02 13:53:07 -0500 |
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committer | Jon Loeliger <jdl@freescale.com> | 2005-08-02 13:53:07 -0500 |
commit | 4b1d95d96a39a71eddd088bb5e0e9e699035c9bf (patch) | |
tree | 57e2d52b0636c7299992e869fa0b0ee4da7ca4d2 /cpu/ppc4xx/405gp_pci.c | |
parent | de1d0a69956a63cea6a62043ae5d5afb584efe93 (diff) | |
parent | 095b8a3798f1c6cd618092899e783dc2ee0d23f5 (diff) |
Merge with rsync://git-user@source.denx.net/git/u-boot.git
Diffstat (limited to 'cpu/ppc4xx/405gp_pci.c')
-rw-r--r-- | cpu/ppc4xx/405gp_pci.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 4f1754ade..ebbcfd573 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -437,7 +437,7 @@ void pci_440_init (struct pci_controller *hose) * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR) mfsdr(sdr_sdstp1,strap); if ( (strap & 0x00010000) == 0 ){ printf("PCI: SDR0_STRP1[PISE] not set.\n"); @@ -498,7 +498,7 @@ void pci_440_init (struct pci_controller *hose) #if defined(CONFIG_440_GX) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ -#else +#elif defined(PCIX0_BRDGOPT1) out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ #endif @@ -531,7 +531,9 @@ void pci_440_init (struct pci_controller *hose) #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif +#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR) out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); +#endif hose->last_busno = pci_hose_scan(hose); } } |