diff options
| author | Stefan Roese <sr@denx.de> | 2008-01-09 10:43:47 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-01-09 10:43:47 +0100 |
| commit | 1466ef8db57a2b52efd8c900dd37e7b3840dc263 (patch) | |
| tree | a81e87f5d4968652555d64d122bcfef01f6ce7c7 /cpu | |
| parent | 1f84021a85abeb837d2ce0dc84297b4f1d45d516 (diff) | |
| parent | b2e2142c500c48a57f18f9dd30e66c13caea0971 (diff) | |
Merge branch 'lwmon5-no-ocm'
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ppc4xx/commproc.c | 14 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 52 |
2 files changed, 65 insertions, 1 deletions
diff --git a/cpu/ppc4xx/commproc.c b/cpu/ppc4xx/commproc.c index 68aab5b7e..22156dd9d 100644 --- a/cpu/ppc4xx/commproc.c +++ b/cpu/ppc4xx/commproc.c @@ -26,10 +26,21 @@ #include <common.h> #include <commproc.h> - +#include <asm/io.h> #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +#if defined(CFG_POST_ALT_WORD_ADDR) +void post_word_store (ulong a) +{ + out_be32((void *)CFG_POST_ALT_WORD_ADDR, a); +} + +ulong post_word_load (void) +{ + return in_be32((void *)CFG_POST_ALT_WORD_ADDR); +} +#else /* CFG_POST_ALT_WORD_ADDR */ void post_word_store (ulong a) { volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); @@ -41,6 +52,7 @@ ulong post_word_load (void) volatile void *save_addr = (volatile void *)(CFG_OCM_DATA_ADDR + CFG_POST_WORD_ADDR); return *(volatile ulong *) save_addr; } +#endif /* CFG_POST_ALT_WORD_ADDR */ #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 52601ed70..a73060436 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -636,6 +636,33 @@ _start: dcbz r0,r3 addi r3,r3,32 bdnz ..d_ag + + /* + * Lock the init-ram/stack in d-cache, so that other regions + * may use d-cache as well + * Note, that this current implementation locks exactly 4k + * of d-cache, so please make sure that you don't define a + * bigger init-ram area. Take a look at the lwmon5 440EPx + * implementation as a reference. + */ + msync + isync + /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ + lis r1,0x0201 + ori r1,r1,0xf808 + mtspr dvlim,r1 + lis r1,0x0808 + ori r1,r1,0x0808 + mtspr dnv0,r1 + mtspr dnv1,r1 + mtspr dnv2,r1 + mtspr dnv3,r1 + mtspr dtv0,r1 + mtspr dtv1,r1 + mtspr dtv2,r1 + mtspr dtv3,r1 + msync + isync #endif /* CFG_INIT_RAM_DCACHE */ /* 440EP & 440GR are only 440er PPC's without internal SRAM */ @@ -1345,6 +1372,31 @@ relocate_code: mr r4,r10 mr r5,r11 #endif + +#ifdef CFG_INIT_RAM_DCACHE + /* + * Unlock the previously locked d-cache + */ + msync + isync + /* set TFLOOR/NFLOOR to 0 again */ + lis r6,0x0001 + ori r6,r6,0xf800 + mtspr dvlim,r6 + lis r6,0x0000 + ori r6,r6,0x0000 + mtspr dnv0,r6 + mtspr dnv1,r6 + mtspr dnv2,r6 + mtspr dnv3,r6 + mtspr dtv0,r6 + mtspr dtv1,r6 + mtspr dtv2,r6 + mtspr dtv3,r6 + msync + isync +#endif /* CFG_INIT_RAM_DCACHE */ + #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) |