diff options
| author | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2003-06-27 21:31:46 +0000 |
| commit | 8bde7f776c77b343aca29b8c7b58464d915ac245 (patch) | |
| tree | 20f1fd99975215e7c658454a15cdb4ed4694e2d4 /drivers | |
| parent | 993cad9364c6b87ae429d1ed1130d8153f6f027e (diff) | |
* Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
Diffstat (limited to 'drivers')
38 files changed, 5065 insertions, 5237 deletions
diff --git a/drivers/3c589.c b/drivers/3c589.c index 541f93b71..080b686e2 100644 --- a/drivers/3c589.c +++ b/drivers/3c589.c @@ -101,8 +101,8 @@ typedef unsigned long int dword; #define insw(args...) mmio_insw(args) #define mmio_insw(r,b,l) ({ int __i ; \ word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = mmio_inw(r); \ mmio_inw(0); \ }; \ @@ -204,40 +204,39 @@ static void el_get_mac_addr( unsigned char *mac_addr ) #if EL_DEBUG > 1 static void print_packet( byte * buf, int length ) { - int i; - int remainder; - int lines; - - PRINTK2("Packet of length %d \n", length ); - - lines = length / 16; - remainder = length % 16; - - for ( i = 0; i < lines ; i ++ ) { - int cur; - - for ( cur = 0; cur < 8; cur ++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - PRINTK2("%02x%02x ", a, b ); - } - PRINTK2("\n"); - } - for ( i = 0; i < remainder/2 ; i++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - PRINTK2("%02x%02x ", a, b ); - } - PRINTK2("\n"); + int i; + int remainder; + int lines; + + PRINTK2("Packet of length %d \n", length ); + + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + PRINTK2("%02x%02x ", a, b ); + } + PRINTK2("\n"); } #endif /* EL_DEBUG > 1 */ - /************************************************************************** ETH_RESET - Reset adapter ***************************************************************************/ @@ -436,7 +435,6 @@ int eth_rx() } - /************************************************************************** ETH_TRANSMIT - Transmit a frame ***************************************************************************/ @@ -506,9 +504,9 @@ int eth_send(volatile void *packet, int length) { PRINTK("\n\n"); } - /* wait for Tx complete */ + /* wait for Tx complete */ PRINTK("Waiting for Tx to complete...\n"); - while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0) + while(((status = inw(EL_BASE_ADDR + VX_STATUS)) & S_COMMAND_IN_PROGRESS) != 0) { udelay(10); } @@ -518,5 +516,4 @@ int eth_send(volatile void *packet, int length) { } - #endif /* CONFIG_DRIVER_3C589 */ diff --git a/drivers/3c589.h b/drivers/3c589.h index 00e7f7c30..6735bf9f6 100644 --- a/drivers/3c589.h +++ b/drivers/3c589.h @@ -129,7 +129,7 @@ #define VX_W0_RESOURCE_CFG 0x08 #define VX_W0_ADDRESS_CFG 0x06 #define VX_W0_CONFIG_CTRL 0x04 - /* Read */ + /* Read */ #define VX_W0_PRODUCT_ID 0x02 #define VX_W0_MFG_ID 0x00 diff --git a/drivers/5701rls.c b/drivers/5701rls.c index c4409e486..86950d0f8 100644 --- a/drivers/5701rls.c +++ b/drivers/5701rls.c @@ -33,9 +33,9 @@ LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice) FwImgInfo.Data.Length = t3FwDataLen; if (LM_LoadFirmware(pDevice, - &FwImgInfo, - T3_RX_CPU_ID | T3_TX_CPU_ID, - T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + &FwImgInfo, + T3_RX_CPU_ID | T3_TX_CPU_ID, + T3_RX_CPU_ID) != LM_STATUS_SUCCESS) { return LM_STATUS_FAILURE; } diff --git a/drivers/ali512x.c b/drivers/ali512x.c index e52edd003..7b7edc09a 100644 --- a/drivers/ali512x.c +++ b/drivers/ali512x.c @@ -58,7 +58,7 @@ */ static void ali_write(u8 index, u8 value) -{ +{ /* write an arbirary register */ outb(index, ALI_INDEX); outb(value, ALI_DATA); @@ -74,7 +74,7 @@ static int ali_read(u8 index) #define ALI_OPEN() \ outb(0x51, ALI_INDEX); \ - outb(0x23, ALI_INDEX) + outb(0x23, ALI_INDEX) #define ALI_CLOSE() \ @@ -82,7 +82,7 @@ static int ali_read(u8 index) /* Select a logical device */ #define ALI_SELDEV(dev) \ - ali_write(0x07, dev) + ali_write(0x07, dev) void ali512x_init(void) @@ -102,14 +102,14 @@ void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel) { ALI_OPEN(); ALI_SELDEV(0); - + ali_write(0x30, enabled?1:0); if (enabled) { ali_write(0x60, io >> 8); ali_write(0x61, io & 0xff); ali_write(0x70, irq); ali_write(0x74, dma_channel); - + /* AT mode, no drive swap */ ali_write(0xf0, 0x08); ali_write(0xf1, 0x00); @@ -124,14 +124,14 @@ void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel) { ALI_OPEN(); ALI_SELDEV(3); - + ali_write(0x30, enabled?1:0); if (enabled) { ali_write(0x60, io >> 8); ali_write(0x61, io & 0xff); ali_write(0x70, irq); ali_write(0x74, dma_channel); - + /* mode: EPP 1.9, ECP FIFO threshold = 7, IRQ active low */ ali_write(0xf0, 0xbc); /* 12 MHz, Burst DMA in ECP */ @@ -145,18 +145,18 @@ void ali512x_set_uart(int enabled, int index, u16 io, u8 irq) { ALI_OPEN(); ALI_SELDEV(index?5:4); - + ali_write(0x30, enabled?1:0); if (enabled) { ali_write(0x60, io >> 8); ali_write(0x61, io & 0xff); ali_write(0x70, irq); - + ali_write(0xf0, 0x00); ali_write(0xf1, 0x00); - + /* huh? write 0xf2 twice - a typo in rolo - * or some secret ali errata? Who knows? + * or some secret ali errata? Who knows? */ if (index) { ali_write(0xf2, 0x00); @@ -171,7 +171,7 @@ void ali512x_set_uart2_irda(int enabled) { ALI_OPEN(); ALI_SELDEV(5); - + ali_write(0xf1, enabled?0x48:0x00); /* fullduplex IrDa */ ALI_CLOSE(); @@ -181,7 +181,7 @@ void ali512x_set_rtc(int enabled, u16 io, u8 irq) { ALI_OPEN(); ALI_SELDEV(6); - + ali_write(0x30, enabled?1:0); if (enabled) { ali_write(0x60, io >> 8); @@ -197,12 +197,12 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) { ALI_OPEN(); ALI_SELDEV(7); - + ali_write(0x30, enabled?1:0); if (enabled) { ali_write(0x70, kbc_irq); - ali_write(0x72, mouse_irq); - + ali_write(0x72, mouse_irq); + ali_write(0xf0, 0x00); } ALI_CLOSE(); @@ -210,21 +210,21 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) /* Common I/O - * + * * (This descripotsion is base on several incompete sources * since I have not been able to obtain any datasheet for the device - * there may be some mis-understandings burried in here. + * there may be some mis-understandings burried in here. * -- Daniel daniel@omicron.se) - * + * * There are 22 CIO pins numbered * 10-17 * 20-25 * 30-37 - * + * * 20-24 are dedicated CIO pins, the other 17 are muliplexed with * other functions. - * - * Secondary + * + * Secondary * CIO Pin Function Decription * ======================================================= * CIO10 IRQIN1 Interrupt input 1? @@ -235,14 +235,14 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) * CIO15 P20 KBC P21 fucntion * CIO16 I2C_CLK I2C Clock * CIO17 I2C_DAT I2C Data - * + * * CIO20 - * CIO21 - * CIO22 - * CIO23 - * CIO24 - * CIO25 LOCK Keylock - * + * * CIO30 KBC_CLK Keybaord Clock * CIO31 CS0J General Chip Select decoder CS0J * CIO32 CS1J General Chip Select decoder CS1J @@ -252,13 +252,13 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) * CIO36 ALT_MDAT Alternative Mouse Data * CIO37 ALT_KBC Alternative KBC select * - * The CIO use an indirect address scheme. - * + * The CIO use an indirect address scheme. + * * Reigster 3 in the SIO is used to select the index and data * port addresses where the CIO I/O registers show up. - * The function selection registers are accessible under - * function SIO 8. - * + * The function selection registers are accessible under + * function SIO 8. + * * SIO reigster 3 (CIO Address Selection) bit definitions: * bit 7 CIO index and data registers enabled * bit 1-0 CIO indirect registers port address select @@ -266,23 +266,23 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) * 1 index = 0xE2 data = 0xE3 * 2 index = 0xE4 data = 0xE5 * 3 index = 0xEA data = 0xEB - * + * * There are three CIO I/O register accessed via CIO index port and CIO data port * 0x01 CIO 10-17 data * 0x02 CIO 20-25 data (bits 7-6 unused) * 0x03 CIO 30-37 data - * - * - * The pin function is accessed through normal + * + * + * The pin function is accessed through normal * SIO registers, each register have the same format: - * + * * Bit Function Value - * 0 Input/output 1=input + * 0 Input/output 1=input * 1 Polarity of signal 1=inverted * 2 Unused ?? * 3 Function (normal or special) 1=special * 7-4 Unused - * + * * SIO REG * 0xe0 CIO 10 Config * 0xe1 CIO 11 Config @@ -308,7 +308,7 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) * 0xfa CIO 35 Config * 0xfb CIO 36 Config * 0xfc CIO 37 Config - * + * */ #define ALI_CIO_PORT_SEL 0x83 @@ -318,28 +318,28 @@ void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq) void ali512x_set_cio(int enabled) { int i; - + ALI_OPEN(); - + if (enabled) { ali_write(0x3, ALI_CIO_PORT_SEL); /* Enable CIO data register */ } else { ali_write(0x3, ALI_CIO_PORT_SEL & ~0x80); } - + ALI_SELDEV(8); - + ali_write(0x30, enabled?1:0); - + /* set all pins to input to start with */ for (i=0xe0;i<0xee;i++) { ali_write(i, 1); } - + for (i=0xf5;i<0xfe;i++) { ali_write(i, 1); } - + ALI_CLOSE(); } @@ -348,23 +348,23 @@ void ali512x_cio_function(int pin, int special, int inv, int input) { u8 data; u8 addr; - + /* valid pins are 10-17, 20-25 and 30-37 */ - if (pin >= 10 && pin <= 17) { + if (pin >= 10 && pin <= 17) { addr = 0xe0+(pin&7); } else if (pin >= 20 && pin <= 25) { addr = 0xe8+(pin&7); - } else if (pin >= 30 && pin <= 37) { + } else if (pin >= 30 && pin <= 37) { addr = 0xf5+(pin&7); } else { return; } - + ALI_OPEN(); ALI_SELDEV(8); - - + + data=0xf4; if (special) { data |= 0x08; @@ -376,22 +376,22 @@ void ali512x_cio_function(int pin, int special, int inv, int input) data |= 0x01; } } - + ali_write(addr, data); - + ALI_CLOSE(); } -void ali512x_cio_out(int pin, int value) +void ali512x_cio_out(int pin, int value) { u8 reg; u8 data; u8 bit; - + reg = pin/10; bit = 1 << (pin%10); - - + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ data = inb(ALI_CIO_DATA); if (value) { @@ -407,17 +407,17 @@ int ali512x_cio_in(int pin) u8 reg; u8 data; u8 bit; - + /* valid pins are 10-17, 20-25 and 30-37 */ reg = pin/10; bit = 1 << (pin%10); - - + + outb(reg, ALI_CIO_INDEX); /* select I/O register */ data = inb(ALI_CIO_DATA); - - return data & bit; + + return data & bit; } - + #endif diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c index a88880ad3..5f632a646 100644 --- a/drivers/bcm570x.c +++ b/drivers/bcm570x.c @@ -19,7 +19,6 @@ #include <malloc.h> - /* * PCI Registers and definitions. */ @@ -33,7 +32,6 @@ #define BCM570X_ILINE 1 - #define SECOND_USEC 1000000 #define MAX_PACKET_SIZE 1600 #define MAX_UNITS 4 @@ -98,7 +96,6 @@ static unsigned int stats_coalesce_ticks[MAX_UNITS] = {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK}; - /* * Legitimate values for BCM570x device types */ @@ -274,7 +271,6 @@ struct pci_device_table { #define n570xDevices (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0])) - /* * Allocate a packet buffer from the bcm570x packet pool. */ @@ -522,7 +518,7 @@ int eth_init(bd_t *bis) else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID) printf("Broadcom BCM5701 Integrated Copper "); else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID) - printf("Broadcom BCM5703 Integrated Copper "); + printf("Broadcom BCM5703 Integrated Copper "); else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID) printf("Broadcom BCM8002 SerDes "); else if (pDevice->EnableTbi) @@ -556,21 +552,21 @@ eth_isr(void) if (pDevice->UseTaggedStatus) { if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) || pUmDevice->adapter_just_inited) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); - oldtag = pDevice->pStatusBlkVirt->StatusTag; - - for (i = 0; ; i++) { - pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; - LM_ServiceInterrupts(pDevice); - newtag = pDevice->pStatusBlkVirt->StatusTag; - if ((newtag == oldtag) || (i > 50)) { - MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); - if (pDevice->UndiFix) { - REG_WR(pDevice, Grc.LocalCtrl, + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); + oldtag = pDevice->pStatusBlkVirt->StatusTag; + + for (i = 0; ; i++) { + pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED; + LM_ServiceInterrupts(pDevice); + newtag = pDevice->pStatusBlkVirt->StatusTag; + if ((newtag == oldtag) || (i > 50)) { + MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24); + if (pDevice->UndiFix) { + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | 0x2); - } - break; - } + } + break; + } oldtag = newtag; } } @@ -625,8 +621,8 @@ eth_send(volatile void *packet, int length) /* Link down, return */ while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) { #if 0 - printf("eth%d: link down - check cable or link partner.\n", - pUmDevice->index); + printf("eth%d: link down - check cable or link partner.\n", + pUmDevice->index); #endif eth_isr(); @@ -672,7 +668,7 @@ eth_send(volatile void *packet, int length) * used to send the packet. */ if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) { - if (pUmPacket->skbuff == NULL){ + if (pUmPacket->skbuff == NULL){ /* Packet was discarded */ printf("TX: failed (1)\n"); status = 1; @@ -680,8 +676,8 @@ eth_send(volatile void *packet, int length) printf("TX: failed (2)\n"); status = 2; } - QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); - return status; + QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket); + return status; } /* Copy packet to DMA buffer */ @@ -694,11 +690,11 @@ eth_send(volatile void *packet, int length) pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM; if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){ - /* - * A lower level send failure will push the packet descriptor back - * in the free queue, so just deal with the VxWorks clusters. - */ - if (pUmPacket->skbuff == NULL){ + /* + * A lower level send failure will push the packet descriptor back + * in the free queue, so just deal with the VxWorks clusters. + */ + if (pUmPacket->skbuff == NULL){ printf("TX failed (1)!\n"); /* Packet was discarded */ status = 3; @@ -804,7 +800,6 @@ eth_rx(void) } - /* Shut down device */ void eth_halt(void) @@ -814,19 +809,19 @@ eth_halt(void) if (pDevice && pUmDevice && pUmDevice->opened){ printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name); printf("HALT,"); - /* stop device */ - LM_Halt(pDevice); + /* stop device */ + LM_Halt(pDevice); printf("POWER DOWN,"); - LM_SetPowerState(pDevice, LM_POWER_STATE_D3); + LM_SetPowerState(pDevice, LM_POWER_STATE_D3); - /* Free the memory allocated by the device in tigon3 */ - for (i = 0; i < pUmDevice->mem_list_num; i++) { - if (pUmDevice->mem_list[i]) { + /* Free the memory allocated by the device in tigon3 */ + for (i = 0; i < pUmDevice->mem_list_num; i++) { + if (pUmDevice->mem_list[i]) { /* sanity check */ - if (pUmDevice->dma_list[i]) { /* cache-safe memory */ - free(pUmDevice->mem_list[i]); + if (pUmDevice->dma_list[i]) { /* cache-safe memory */ + free(pUmDevice->mem_list[i]); } else { - free(pUmDevice->mem_list[i]); /* normal memory */ + free(pUmDevice->mem_list[i]); /* normal memory */ } } } @@ -840,8 +835,6 @@ eth_halt(void) } - - /* * * Middle Module: Interface between the HW driver (tigon3 modules) and @@ -931,7 +924,6 @@ MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, } - LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize, PLM_VOID *pMemoryBlockVirt) @@ -1183,26 +1175,26 @@ MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) if (Status == LM_STATUS_LINK_DOWN) { sprintf(buf,"eth%d: %s: NIC Link is down\n", pUmDevice->index,pUmDevice->name); - lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; + lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?'; } else if (Status == LM_STATUS_LINK_ACTIVE) { sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name); if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){ strcat(buf,"1000 Mbps "); - lcd[0] = '1';lcd[1]='G';lcd[2]='B'; + lcd[0] = '1';lcd[1]='G';lcd[2]='B'; } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){ strcat(buf,"100 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]='0'; + lcd[0] = '1';lcd[1]='0';lcd[2]='0'; } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){ strcat(buf,"10 Mbps "); - lcd[0] = '1';lcd[1]='0';lcd[2]=' '; + lcd[0] = '1';lcd[1]='0';lcd[2]=' '; } if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){ strcat(buf, "full duplex"); - lcd[3] = 'F'; + lcd[3] = 'F'; } else { strcat(buf, "half duplex"); - lcd[3] = 'H'; + lcd[3] = 'H'; } strcat(buf, " link up"); @@ -1223,7 +1215,7 @@ MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status) } else { strcat(buf, ", flow control OFF"); } - strcat(buf,"\n"); + strcat(buf,"\n"); printf("%s",buf); } #if 0 @@ -1275,20 +1267,20 @@ MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) int len = 0; if (len == 0) - return (LM_STATUS_SUCCESS); + return (LM_STATUS_SUCCESS); if (len > MAX_PACKET_SIZE){ - printf ("eth%d: xmit frame discarded, too big!, size = %d\n", + printf ("eth%d: xmit frame discarded, too big!, size = %d\n", pUmDevice->index, len); - return (LM_STATUS_FAILURE); + return (LM_STATUS_FAILURE); } skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE); if (skbnew == NULL) { - pUmDevice->tx_full = 1; - printf ("eth%d: out of transmit buffers", pUmDevice->index); - return (LM_STATUS_FAILURE); + pUmDevice->tx_full = 1; + printf ("eth%d: out of transmit buffers", pUmDevice->index); + return (LM_STATUS_FAILURE); } /* New packet values */ @@ -1325,13 +1317,13 @@ MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice) pUmPacket = (PUM_PACKET) pPacket; skb = (void*)pUmPacket->skbuff; - /* - * Free MBLK if we transmitted a fragmented packet or a - * non-fragmented packet straight from the VxWorks - * buffer pool. If packet was copied to a local transmit - * buffer, then there's no MBUF to free, just free - * the transmit buffer back to the cluster pool. - */ + /* + * Free MBLK if we transmitted a fragmented packet or a + * non-fragmented packet straight from the VxWorks + * buffer pool. If packet was copied to a local transmit + * buffer, then there's no MBUF to free, just free + * the transmit buffer back to the cluster pool. + */ if (skb) bcm570xPktFree (pUmDevice->index, skb); @@ -1383,22 +1375,22 @@ void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr) { #if (BITS_PER_LONG == 64) - paddr->High = ((unsigned long) addr) >> 32; - paddr->Low = ((unsigned long) addr) & 0xffffffff; + paddr->High = ((unsigned long) addr) >> 32; + paddr->Low = ((unsigned long) addr) & 0xffffffff; #else - paddr->High = 0; - paddr->Low = (unsigned long) addr; + paddr->High = 0; + paddr->Low = (unsigned long) addr; #endif } void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr) { - unsigned long baddr = (unsigned long) addr; + unsigned long baddr = (unsigned long) addr; #if (BITS_PER_LONG == 64) - set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); + set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32); #else - set_64bit_addr(paddr, baddr, 0); + set_64bit_addr(paddr, baddr, 0); #endif } @@ -1465,7 +1457,6 @@ unsigned int QueueSize) { } /* QQ_InitQueue */ - /******************************************************************************/ /* Description: */ /* */ @@ -1482,7 +1473,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_Full */ - /******************************************************************************/ /* Description: */ /* */ @@ -1495,7 +1485,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_Empty */ - /******************************************************************************/ /* Description: */ /* */ @@ -1508,7 +1497,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_GetSize */ - /******************************************************************************/ /* Description: */ /* */ @@ -1521,7 +1509,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_GetEntryCnt */ - /******************************************************************************/ /* Description: */ /* */ @@ -1539,7 +1526,7 @@ PQQ_ENTRY pEntry) { #if !defined(QQ_NO_OVERFLOW_CHECK) if(Head == pQueue->Tail) { - return 0; + return 0; } /* if */ #endif /* QQ_NO_OVERFLOW_CHECK */ @@ -1552,7 +1539,6 @@ PQQ_ENTRY pEntry) { } /* QQ_PushHead */ - /******************************************************************************/ /* Description: */ /* */ @@ -1568,13 +1554,13 @@ PQQ_ENTRY pEntry) { Tail = pQueue->Tail; if(Tail == 0) { - Tail = pQueue->Size; + Tail = pQueue->Size; } /* if */ Tail--; #if !defined(QQ_NO_OVERFLOW_CHECK) if(Tail == pQueue->Head) { - return 0; + return 0; } /* if */ #endif /* QQ_NO_OVERFLOW_CHECK */ @@ -1587,7 +1573,6 @@ PQQ_ENTRY pEntry) { } /* QQ_PushTail */ - /******************************************************************************/ /* Description: */ /* */ @@ -1603,12 +1588,12 @@ PQQ_CONTAINER pQueue) { #if !defined(QQ_NO_UNDERFLOW_CHECK) if(Head == pQueue->Tail) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } /* if */ #endif /* QQ_NO_UNDERFLOW_CHECK */ if(Head == 0) { - Head = pQueue->Size; + Head = pQueue->Size; } /* if */ Head--; @@ -1622,7 +1607,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_PopHead */ - /******************************************************************************/ /* Description: */ /* */ @@ -1638,7 +1622,7 @@ PQQ_CONTAINER pQueue) { #if !defined(QQ_NO_UNDERFLOW_CHECK) if(Tail == pQueue->Head) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } /* if */ #endif /* QQ_NO_UNDERFLOW_CHECK */ @@ -1651,7 +1635,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_PopTail */ - /******************************************************************************/ /* Description: */ /* */ @@ -1664,16 +1647,16 @@ QQ_GetHead( { if(Idx >= atomic_read(&pQueue->EntryCnt)) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } if(pQueue->Head > Idx) { - Idx = pQueue->Head - Idx; + Idx = pQueue->Head - Idx; } else { - Idx = pQueue->Size - (Idx - pQueue->Head); + Idx = pQueue->Size - (Idx - pQueue->Head); } Idx--; @@ -1681,7 +1664,6 @@ QQ_GetHead( } - /******************************************************************************/ /* Description: */ /* */ @@ -1694,13 +1676,13 @@ QQ_GetTail( { if(Idx >= atomic_read(&pQueue->EntryCnt)) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } Idx += pQueue->Tail; if(Idx >= pQueue->Size) { - Idx = Idx - pQueue->Size; + Idx = Idx - pQueue->Size; } return pQueue->Array[Idx]; diff --git a/drivers/bcm570x_autoneg.c b/drivers/bcm570x_autoneg.c index 1818c6a27..9023796aa 100644 --- a/drivers/bcm570x_autoneg.c +++ b/drivers/bcm570x_autoneg.c @@ -16,7 +16,6 @@ #include "bcm570x_mm.h" - /******************************************************************************/ /* Description: */ /* */ @@ -37,7 +36,6 @@ MM_AnTxConfig( } - /******************************************************************************/ /* Description: */ /* */ @@ -56,7 +54,6 @@ MM_AnTxIdle( } - /******************************************************************************/ /* Description: */ /* */ @@ -78,17 +75,16 @@ MM_AnRxConfig( Value32 = REG_RD(pDevice, MacCtrl.Status); if(Value32 & MAC_STATUS_RECEIVING_CFG) { - Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg); - *pRxConfig = (unsigned short) Value32; + Value32 = REG_RD(pDevice, MacCtrl.RxAutoNeg); + *pRxConfig = (unsigned short) Value32; - Retcode = AN_TRUE; + Retcode = AN_TRUE; } return Retcode; } - /******************************************************************************/ /* Description: */ /* */ @@ -102,7 +98,7 @@ AutonegInit( for(j = 0; j < sizeof(AN_STATE_INFO); j++) { - ((unsigned char *) pAnInfo)[j] = 0; + ((unsigned char *) pAnInfo)[j] = 0; } /* Initialize the default advertisement register. */ @@ -113,7 +109,6 @@ AutonegInit( } - /******************************************************************************/ /* Description: */ /* */ @@ -130,14 +125,14 @@ Autoneg8023z( /* Get the current time. */ if(pAnInfo->State == AN_STATE_UNKNOWN) { - pAnInfo->RxConfig.AsUSHORT = 0; - pAnInfo->CurrentTime_us = 0; - pAnInfo->LinkTime_us = 0; - pAnInfo->AbilityMatchCfg = 0; - pAnInfo->AbilityMatchCnt = 0; - pAnInfo->AbilityMatch = AN_FALSE; - pAnInfo->IdleMatch = AN_FALSE; - pAnInfo->AckMatch = AN_FALSE; + pAnInfo->RxConfig.AsUSHORT = 0; + pAnInfo->CurrentTime_us = 0; + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; } /* Increment the timer tick. This function is called every microsecon. */ @@ -147,43 +142,43 @@ Autoneg8023z( /* corresponding conditions are satisfied. */ if(MM_AnRxConfig(pAnInfo, &RxConfig)) { - if(RxConfig != pAnInfo->AbilityMatchCfg) - { - pAnInfo->AbilityMatchCfg = RxConfig; - pAnInfo->AbilityMatch = AN_FALSE; - pAnInfo->AbilityMatchCnt = 0; - } - else - { - pAnInfo->AbilityMatchCnt++; - if(pAnInfo->AbilityMatchCnt > 1) - { - pAnInfo->AbilityMatch = AN_TRUE; - pAnInfo->AbilityMatchCfg = RxConfig; - } - } - - if(RxConfig & AN_CONFIG_ACK) - { - pAnInfo->AckMatch = AN_TRUE; - } - else - { - pAnInfo->AckMatch = AN_FALSE; - } - - pAnInfo->IdleMatch = AN_FALSE; + if(RxConfig != pAnInfo->AbilityMatchCfg) + { + pAnInfo->AbilityMatchCfg = RxConfig; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AbilityMatchCnt = 0; + } + else + { + pAnInfo->AbilityMatchCnt++; + if(pAnInfo->AbilityMatchCnt > 1) + { + pAnInfo->AbilityMatch = AN_TRUE; + pAnInfo->AbilityMatchCfg = RxConfig; + } + } + + if(RxConfig & AN_CONFIG_ACK) + { + pAnInfo->AckMatch = AN_TRUE; + } + else + { + pAnInfo->AckMatch = AN_FALSE; + } + + pAnInfo->IdleMatch = AN_FALSE; } else { - pAnInfo->IdleMatch = AN_TRUE; + pAnInfo->IdleMatch = AN_TRUE; - pAnInfo->AbilityMatchCfg = 0; - pAnInfo->AbilityMatchCnt = 0; - pAnInfo->AbilityMatch = AN_FALSE; - pAnInfo->AckMatch = AN_FALSE; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; - RxConfig = 0; + RxConfig = 0; } /* Save the last Config. */ @@ -195,218 +190,218 @@ Autoneg8023z( /* Autoneg state machine as defined in 802.3z section 37.3.1.5. */ switch(pAnInfo->State) { - case AN_STATE_UNKNOWN: - if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an) - { - pAnInfo->CurrentTime_us = 0; - pAnInfo->State = AN_STATE_AN_ENABLE; - } - - /* Fall through.*/ - - case AN_STATE_AN_ENABLE: - pAnInfo->mr_an_complete = AN_FALSE; - pAnInfo->mr_page_rx = AN_FALSE; - - if(pAnInfo->mr_an_enable) - { - pAnInfo->LinkTime_us = 0; - pAnInfo->AbilityMatchCfg = 0; - pAnInfo->AbilityMatchCnt = 0; - pAnInfo->AbilityMatch = AN_FALSE; - pAnInfo->IdleMatch = AN_FALSE; - pAnInfo->AckMatch = AN_FALSE; - - pAnInfo->State = AN_STATE_AN_RESTART_INIT; - } - else - { - pAnInfo->State = AN_STATE_DISABLE_LINK_OK; - } - break; - - case AN_STATE_AN_RESTART_INIT: - pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; - pAnInfo->mr_np_loaded = AN_FALSE; - - pAnInfo->TxConfig.AsUSHORT = 0; - MM_AnTxConfig(pAnInfo); - - AnRet = AUTONEG_STATUS_TIMER_ENABLED; - - pAnInfo->State = AN_STATE_AN_RESTART; - - /* Fall through.*/ - - case AN_STATE_AN_RESTART: - /* Get the current time and compute the delta with the saved */ - /* link timer. */ - Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; - if(Delta_us > AN_LINK_TIMER_INTERVAL_US) - { - pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT; - } - else - { - AnRet = AUTONEG_STATUS_TIMER_ENABLED; - } - break; - - case AN_STATE_DISABLE_LINK_OK: - AnRet = AUTONEG_STATUS_DONE; - break; - - case AN_STATE_ABILITY_DETECT_INIT: - /* Note: in the state diagram, this variable is set to */ - /* mr_adv_ability<12>. Is this right?. */ - pAnInfo->mr_toggle_tx = AN_FALSE; - - /* Send the config as advertised in the advertisement register. */ - pAnInfo->TxConfig.AsUSHORT = 0; - pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex; - pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex; - pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause; - pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause; - pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1; - pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2; - pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page; - - MM_AnTxConfig(pAnInfo); - - pAnInfo->State = AN_STATE_ABILITY_DETECT; - - break; - - case AN_STATE_ABILITY_DETECT: - if(pAnInfo->AbilityMatch == AN_TRUE && - pAnInfo->RxConfig.AsUSHORT != 0) - { - pAnInfo->State = AN_STATE_ACK_DETECT_INIT; - } - - break; - - case AN_STATE_ACK_DETECT_INIT: - pAnInfo->TxConfig.D14_ACK = 1; - MM_AnTxConfig(pAnInfo); - - pAnInfo->State = AN_STATE_ACK_DETECT; - - /* Fall through. */ - - case AN_STATE_ACK_DETECT: - if(pAnInfo->AckMatch == AN_TRUE) - { - if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) == - (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK)) - { - pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT; - } - else - { - pAnInfo->State = AN_STATE_AN_ENABLE; - } - } - else if(pAnInfo->AbilityMatch == AN_TRUE && - pAnInfo->RxConfig.AsUSHORT == 0) - { - pAnInfo->State = AN_STATE_AN_ENABLE; - } - - break; - - case AN_STATE_COMPLETE_ACK_INIT: - /* Make sure invalid bits are not set. */ - if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 || - pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 || - pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 || - pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11) - { - AnRet = AUTONEG_STATUS_FAILED; - break; - } - - /* Set up the link partner advertisement register. */ - pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD; - pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD; - pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1; - pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2; - pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1; - pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2; - pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP; - - pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; - - pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx; - pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11; - pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP; - pAnInfo->mr_page_rx = AN_TRUE; - - pAnInfo->State = AN_STATE_COMPLETE_ACK; - AnRet = AUTONEG_STATUS_TIMER_ENABLED; - - break; - - case AN_STATE_COMPLETE_ACK: - if(pAnInfo->AbilityMatch == AN_TRUE && - pAnInfo->RxConfig.AsUSHORT == 0) - { - pAnInfo->State = AN_STATE_AN_ENABLE; - break; - } - - Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; - - if(Delta_us > AN_LINK_TIMER_INTERVAL_US) - { - if(pAnInfo->mr_adv_next_page == 0 || - pAnInfo->mr_lp_adv_next_page == 0) - { - pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; - } - else - { - if(pAnInfo->TxConfig.bits.D15 == 0 && - pAnInfo->mr_np_rx == 0) - { - pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; - } - else - { - AnRet = AUTONEG_STATUS_FAILED; - } - } - } - - break; - - case AN_STATE_IDLE_DETECT_INIT: - pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; - - MM_AnTxIdle(pAnInfo); - - pAnInfo->State = AN_STATE_IDLE_DETECT; - - AnRet = AUTONEG_STATUS_TIMER_ENABLED; - - break; - - case AN_STATE_IDLE_DETECT: - if(pAnInfo->AbilityMatch == AN_TRUE && - pAnInfo->RxConfig.AsUSHORT == 0) - { - pAnInfo->State = AN_STATE_AN_ENABLE; - break; - } - - Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; - if(Delta_us > AN_LINK_TIMER_INTERVAL_US) - { + case AN_STATE_UNKNOWN: + if(pAnInfo->mr_an_enable || pAnInfo->mr_restart_an) + { + pAnInfo->CurrentTime_us = 0; + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + /* Fall through.*/ + + case AN_STATE_AN_ENABLE: + pAnInfo->mr_an_complete = AN_FALSE; + pAnInfo->mr_page_rx = AN_FALSE; + + if(pAnInfo->mr_an_enable) + { + pAnInfo->LinkTime_us = 0; + pAnInfo->AbilityMatchCfg = 0; + pAnInfo->AbilityMatchCnt = 0; + pAnInfo->AbilityMatch = AN_FALSE; + pAnInfo->IdleMatch = AN_FALSE; + pAnInfo->AckMatch = AN_FALSE; + + pAnInfo->State = AN_STATE_AN_RESTART_INIT; + } + else + { + pAnInfo->State = AN_STATE_DISABLE_LINK_OK; + } + break; + + case AN_STATE_AN_RESTART_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + pAnInfo->mr_np_loaded = AN_FALSE; + + pAnInfo->TxConfig.AsUSHORT = 0; + MM_AnTxConfig(pAnInfo); + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + pAnInfo->State = AN_STATE_AN_RESTART; + + /* Fall through.*/ + + case AN_STATE_AN_RESTART: + /* Get the current time and compute the delta with the saved */ + /* link timer. */ + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + pAnInfo->State = AN_STATE_ABILITY_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + } + break; + + case AN_STATE_DISABLE_LINK_OK: + AnRet = AUTONEG_STATUS_DONE; + break; + + case AN_STATE_ABILITY_DETECT_INIT: + /* Note: in the state diagram, this variable is set to */ + /* mr_adv_ability<12>. Is this right?. */ + pAnInfo->mr_toggle_tx = AN_FALSE; + + /* Send the config as advertised in the advertisement register. */ + pAnInfo->TxConfig.AsUSHORT = 0; + pAnInfo->TxConfig.D5_FD = pAnInfo->mr_adv_full_duplex; + pAnInfo->TxConfig.D6_HD = pAnInfo->mr_adv_half_duplex; + pAnInfo->TxConfig.D7_PS1 = pAnInfo->mr_adv_sym_pause; + pAnInfo->TxConfig.D8_PS2 = pAnInfo->mr_adv_asym_pause; + pAnInfo->TxConfig.D12_RF1 = pAnInfo->mr_adv_remote_fault1; + pAnInfo->TxConfig.D13_RF2 = pAnInfo->mr_adv_remote_fault2; + pAnInfo->TxConfig.D15_NP = pAnInfo->mr_adv_next_page; + + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ABILITY_DETECT; + + break; + + case AN_STATE_ABILITY_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT != 0) + { + pAnInfo->State = AN_STATE_ACK_DETECT_INIT; + } + + break; + + case AN_STATE_ACK_DETECT_INIT: + pAnInfo->TxConfig.D14_ACK = 1; + MM_AnTxConfig(pAnInfo); + + pAnInfo->State = AN_STATE_ACK_DETECT; + + /* Fall through. */ + + case AN_STATE_ACK_DETECT: + if(pAnInfo->AckMatch == AN_TRUE) + { + if((pAnInfo->RxConfig.AsUSHORT & ~AN_CONFIG_ACK) == + (pAnInfo->AbilityMatchCfg & ~AN_CONFIG_ACK)) + { + pAnInfo->State = AN_STATE_COMPLETE_ACK_INIT; + } + else + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + } + else if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + } + + break; + + case AN_STATE_COMPLETE_ACK_INIT: + /* Make sure invalid bits are not set. */ + if(pAnInfo->RxConfig.bits.D0 || pAnInfo->RxConfig.bits.D1 || + pAnInfo->RxConfig.bits.D2 || pAnInfo->RxConfig.bits.D3 || + pAnInfo->RxConfig.bits.D4 || pAnInfo->RxConfig.bits.D9 || + pAnInfo->RxConfig.bits.D10 || pAnInfo->RxConfig.bits.D11) + { + AnRet = AUTONEG_STATUS_FAILED; + break; + } + + /* Set up the link partner advertisement register. */ + pAnInfo->mr_lp_adv_full_duplex = pAnInfo->RxConfig.D5_FD; + pAnInfo->mr_lp_adv_half_duplex = pAnInfo->RxConfig.D6_HD; + pAnInfo->mr_lp_adv_sym_pause = pAnInfo->RxConfig.D7_PS1; + pAnInfo->mr_lp_adv_asym_pause = pAnInfo->RxConfig.D8_PS2; + pAnInfo->mr_lp_adv_remote_fault1 = pAnInfo->RxConfig.D12_RF1; + pAnInfo->mr_lp_adv_remote_fault2 = pAnInfo->RxConfig.D13_RF2; + pAnInfo->mr_lp_adv_next_page = pAnInfo->RxConfig.D15_NP; + + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + pAnInfo->mr_toggle_tx = !pAnInfo->mr_toggle_tx; + pAnInfo->mr_toggle_rx = pAnInfo->RxConfig.bits.D11; + pAnInfo->mr_np_rx = pAnInfo->RxConfig.D15_NP; + pAnInfo->mr_page_rx = AN_TRUE; + + pAnInfo->State = AN_STATE_COMPLETE_ACK; + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_COMPLETE_ACK: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { + if(pAnInfo->mr_adv_next_page == 0 || + pAnInfo->mr_lp_adv_next_page == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + if(pAnInfo->TxConfig.bits.D15 == 0 && + pAnInfo->mr_np_rx == 0) + { + pAnInfo->State = AN_STATE_IDLE_DETECT_INIT; + } + else + { + AnRet = AUTONEG_STATUS_FAILED; + } + } + } + + break; + + case AN_STATE_IDLE_DETECT_INIT: + pAnInfo->LinkTime_us = pAnInfo->CurrentTime_us; + + MM_AnTxIdle(pAnInfo); + + pAnInfo->State = AN_STATE_IDLE_DETECT; + + AnRet = AUTONEG_STATUS_TIMER_ENABLED; + + break; + + case AN_STATE_IDLE_DETECT: + if(pAnInfo->AbilityMatch == AN_TRUE && + pAnInfo->RxConfig.AsUSHORT == 0) + { + pAnInfo->State = AN_STATE_AN_ENABLE; + break; + } + + Delta_us = pAnInfo->CurrentTime_us - pAnInfo->LinkTime_us; + if(Delta_us > AN_LINK_TIMER_INTERVAL_US) + { #if 0 /* if(pAnInfo->IdleMatch == AN_TRUE) */ /* { */ #endif - pAnInfo->State = AN_STATE_LINK_OK; + pAnInfo->State = AN_STATE_LINK_OK; #if 0 /* } */ /* else */ @@ -415,26 +410,26 @@ Autoneg8023z( /* break; */ /* } */ #endif - } + } - break; + break; - case AN_STATE_LINK_OK: - pAnInfo->mr_an_complete = AN_TRUE; - pAnInfo->mr_link_ok = AN_TRUE; - AnRet = AUTONEG_STATUS_DONE; + case AN_STATE_LINK_OK: + pAnInfo->mr_an_complete = AN_TRUE; + pAnInfo->mr_link_ok = AN_TRUE; + AnRet = AUTONEG_STATUS_DONE; - break; + break; - case AN_STATE_NEXT_PAGE_WAIT_INIT: - break; + case AN_STATE_NEXT_PAGE_WAIT_INIT: + break; - case AN_STATE_NEXT_PAGE_WAIT: - break; + case AN_STATE_NEXT_PAGE_WAIT: + break; - default: - AnRet = AUTONEG_STATUS_FAILED; - break; + default: + AnRet = AUTONEG_STATUS_FAILED; + break; } return AnRet; diff --git a/drivers/bcm570x_autoneg.h b/drivers/bcm570x_autoneg.h index 95fcc0736..7830944b8 100644 --- a/drivers/bcm570x_autoneg.h +++ b/drivers/bcm570x_autoneg.h @@ -16,7 +16,6 @@ #define AUTONEG_H - /******************************************************************************/ /* Constants. */ /******************************************************************************/ @@ -28,7 +27,6 @@ #define AN_FALSE 0 - /******************************************************************************/ /* Main data structure for keeping track of 802.3z auto-negotation state */ /* variables as shown in Figure 37-6 of the IEEE 802.3z specification. */ @@ -73,112 +71,112 @@ typedef struct /* Tx config data */ union { - /* The TxConfig register is arranged as follows: */ - /* */ - /* MSB LSB */ - /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ - /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ - /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ - struct - { + /* The TxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { #ifdef BIG_ENDIAN_HOST - unsigned int D7:1; /* PS1 */ - unsigned int D6:1; /* HD */ - unsigned int D5:1; /* FD */ - unsigned int D4:1; - unsigned int D3:1; - unsigned int D2:1; - unsigned int D1:1; - unsigned int D0:1; - unsigned int D15:1; /* NP */ - unsigned int D14:1; /* ACK */ - unsigned int D13:1; /* RF2 */ - unsigned int D12:1; /* RF1 */ - unsigned int D11:1; - unsigned int D10:1; - unsigned int D9:1; - unsigned int D8:1; /* PS2 */ + unsigned int D7:1; /* PS1 */ + unsigned int D6:1; /* HD */ + unsigned int D5:1; /* FD */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ #else /* BIG_ENDIAN_HOST */ - unsigned int D8:1; /* PS2 */ - unsigned int D9:1; - unsigned int D10:1; - unsigned int D11:1; - unsigned int D12:1; /* RF1 */ - unsigned int D13:1; /* RF2 */ - unsigned int D14:1; /* ACK */ - unsigned int D15:1; /* NP */ - unsigned int D0:1; - unsigned int D1:1; - unsigned int D2:1; - unsigned int D3:1; - unsigned int D4:1; - unsigned int D5:1; /* FD */ - unsigned int D6:1; /* HD */ - unsigned int D7:1; /* PS1 */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ #endif - } bits; - - unsigned short AsUSHORT; - - #define D8_PS2 bits.D8 - #define D12_RF1 bits.D12 - #define D13_RF2 bits.D13 - #define D14_ACK bits.D14 - #define D15_NP bits.D15 - #define D5_FD bits.D5 - #define D6_HD bits.D6 - #define D7_PS1 bits.D7 + } bits; + + unsigned short AsUSHORT; + + #define D8_PS2 bits.D8 + #define D12_RF1 bits.D12 + #define D13_RF2 bits.D13 + #define D14_ACK bits.D14 + #define D15_NP bits.D15 + #define D5_FD bits.D5 + #define D6_HD bits.D6 + #define D7_PS1 bits.D7 } TxConfig; /* Rx config data */ union { - /* The RxConfig register is arranged as follows: */ - /* */ - /* MSB LSB */ - /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ - /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ - /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ - struct - { + /* The RxConfig register is arranged as follows: */ + /* */ + /* MSB LSB */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + /* | D7| D6| D5| D4| D3| D2| D1| D0|D15|D14|D13|D12|D11|D10| D9| D8| */ + /* +---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+---+ */ + struct + { #ifdef BIG_ENDIAN_HOST unsigned int D7:1; /* PS1 */ - unsigned int D6:1; /* HD */ + unsigned int D6:1; /* HD */ unsigned int D5:1; /* FD */ - unsigned int D4:1; - unsigned int D3:1; - unsigned int D2:1; - unsigned int D1:1; - unsigned int D0:1; - unsigned int D15:1; /* NP */ - unsigned int D14:1; /* ACK */ - unsigned int D13:1; /* RF2 */ - unsigned int D12:1; /* RF1 */ - unsigned int D11:1; - unsigned int D10:1; - unsigned int D9:1; - unsigned int D8:1; /* PS2 */ + unsigned int D4:1; + unsigned int D3:1; + unsigned int D2:1; + unsigned int D1:1; + unsigned int D0:1; + unsigned int D15:1; /* NP */ + unsigned int D14:1; /* ACK */ + unsigned int D13:1; /* RF2 */ + unsigned int D12:1; /* RF1 */ + unsigned int D11:1; + unsigned int D10:1; + unsigned int D9:1; + unsigned int D8:1; /* PS2 */ #else /* BIG_ENDIAN_HOST */ - unsigned int D8:1; /* PS2 */ - unsigned int D9:1; - unsigned int D10:1; - unsigned int D11:1; - unsigned int D12:1; /* RF1 */ - unsigned int D13:1; /* RF2 */ - unsigned int D14:1; /* ACK */ - unsigned int D15:1; /* NP */ - unsigned int D0:1; - unsigned int D1:1; - unsigned int D2:1; - unsigned int D3:1; - unsigned int D4:1; - unsigned int D5:1; /* FD */ - unsigned int D6:1; /* HD */ - unsigned int D7:1; /* PS1 */ + unsigned int D8:1; /* PS2 */ + unsigned int D9:1; + unsigned int D10:1; + unsigned int D11:1; + unsigned int D12:1; /* RF1 */ + unsigned int D13:1; /* RF2 */ + unsigned int D14:1; /* ACK */ + unsigned int D15:1; /* NP */ + unsigned int D0:1; + unsigned int D1:1; + unsigned int D2:1; + unsigned int D3:1; + unsigned int D4:1; + unsigned int D5:1; /* FD */ + unsigned int D6:1; /* HD */ + unsigned int D7:1; /* PS1 */ #endif - } bits; + } bits; - unsigned short AsUSHORT; + unsigned short AsUSHORT; } RxConfig; #define AN_CONFIG_NP 0x0080 @@ -196,177 +194,177 @@ typedef struct /* Control register. */ union { - struct - { - unsigned int an_enable:1; - unsigned int loopback:1; - unsigned int reset:1; - unsigned int restart_an:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_an_enable Mr0.bits.an_enable - #define mr_loopback Mr0.bits.loopback - #define mr_main_reset Mr0.bits.reset - #define mr_restart_an Mr0.bits.restart_an + struct + { + unsigned int an_enable:1; + unsigned int loopback:1; + unsigned int reset:1; + unsigned int restart_an:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_an_enable Mr0.bits.an_enable + #define mr_loopback Mr0.bits.loopback + #define mr_main_reset Mr0.bits.reset + #define mr_restart_an Mr0.bits.restart_an } Mr0; /* Status register. */ union { - struct - { - unsigned int an_complete:1; - unsigned int link_ok:1; - } bits; + struct + { + unsigned int an_complete:1; + unsigned int link_ok:1; + } bits; - unsigned short AsUSHORT; + unsigned short AsUSHORT; - #define mr_an_complete Mr1.bits.an_complete - #define mr_link_ok Mr1.bits.link_ok + #define mr_an_complete Mr1.bits.an_complete + #define mr_link_ok Mr1.bits.link_ok } Mr1; /* Advertisement register. */ union { - struct - { - unsigned int reserved_4:5; - unsigned int full_duplex:1; - unsigned int half_duplex:1; - unsigned int sym_pause:1; - unsigned int asym_pause:1; - unsigned int reserved_11:3; - unsigned int remote_fault1:1; - unsigned int remote_fault2:1; - unsigned int reserved_14:1; - unsigned int next_page:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_adv_full_duplex Mr4.bits.full_duplex - #define mr_adv_half_duplex Mr4.bits.half_duplex - #define mr_adv_sym_pause Mr4.bits.sym_pause - #define mr_adv_asym_pause Mr4.bits.asym_pause - #define mr_adv_remote_fault1 Mr4.bits.remote_fault1 - #define mr_adv_remote_fault2 Mr4.bits.remote_fault2 - #define mr_adv_next_page Mr4.bits.next_page + struct + { + unsigned int reserved_4:5; + unsigned int full_duplex:1; + unsigned int half_duplex:1; + unsigned int sym_pause:1; + unsigned int asym_pause:1; + unsigned int reserved_11:3; + unsigned int remote_fault1:1; + unsigned int remote_fault2:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_adv_full_duplex Mr4.bits.full_duplex + #define mr_adv_half_duplex Mr4.bits.half_duplex + #define mr_adv_sym_pause Mr4.bits.sym_pause + #define mr_adv_asym_pause Mr4.bits.asym_pause + #define mr_adv_remote_fault1 Mr4.bits.remote_fault1 + #define mr_adv_remote_fault2 Mr4.bits.remote_fault2 + #define mr_adv_next_page Mr4.bits.next_page } Mr4; /* Link partner advertisement register. */ union { - struct - { - unsigned int reserved_4:5; - unsigned int lp_full_duplex:1; - unsigned int lp_half_duplex:1; - unsigned int lp_sym_pause:1; - unsigned int lp_asym_pause:1; - unsigned int reserved_11:3; - unsigned int lp_remote_fault1:1; - unsigned int lp_remote_fault2:1; - unsigned int lp_ack:1; - unsigned int lp_next_page:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex - #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex - #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause - #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause - #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1 - #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2 - #define mr_lp_adv_next_page Mr5.bits.lp_next_page + struct + { + unsigned int reserved_4:5; + unsigned int lp_full_duplex:1; + unsigned int lp_half_duplex:1; + unsigned int lp_sym_pause:1; + unsigned int lp_asym_pause:1; + unsigned int reserved_11:3; + unsigned int lp_remote_fault1:1; + unsigned int lp_remote_fault2:1; + unsigned int lp_ack:1; + unsigned int lp_next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_adv_full_duplex Mr5.bits.lp_full_duplex + #define mr_lp_adv_half_duplex Mr5.bits.lp_half_duplex + #define mr_lp_adv_sym_pause Mr5.bits.lp_sym_pause + #define mr_lp_adv_asym_pause Mr5.bits.lp_asym_pause + #define mr_lp_adv_remote_fault1 Mr5.bits.lp_remote_fault1 + #define mr_lp_adv_remote_fault2 Mr5.bits.lp_remote_fault2 + #define mr_lp_adv_next_page Mr5.bits.lp_next_page } Mr5; /* Auto-negotiation expansion register. */ union { - struct - { - unsigned int reserved_0:1; - unsigned int page_received:1; - unsigned int next_pageable:1; - unsigned int reserved_15:13; - } bits; - - unsigned short AsUSHORT; + struct + { + unsigned int reserved_0:1; + unsigned int page_received:1; + unsigned int next_pageable:1; + unsigned int reserved_15:13; + } bits; + + unsigned short AsUSHORT; } Mr6; /* Auto-negotiation next page transmit register. */ union { - struct - { - unsigned int code_field:11; - unsigned int toggle:1; - unsigned int ack2:1; - unsigned int message_page:1; - unsigned int reserved_14:1; - unsigned int next_page:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_np_tx Mr7.AsUSHORT + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int reserved_14:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_np_tx Mr7.AsUSHORT } Mr7; /* Auto-negotiation link partner ability register. */ union { - struct - { - unsigned int code_field:11; - unsigned int toggle:1; - unsigned int ack2:1; - unsigned int message_page:1; - unsigned int ack:1; - unsigned int next_page:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_lp_np_rx Mr8.AsUSHORT + struct + { + unsigned int code_field:11; + unsigned int toggle:1; + unsigned int ack2:1; + unsigned int message_page:1; + unsigned int ack:1; + unsigned int next_page:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_lp_np_rx Mr8.AsUSHORT } Mr8; /* Extended status register. */ union { - struct - { - unsigned int reserved_11:12; - unsigned int base1000_t_hd:1; - unsigned int base1000_t_fd:1; - unsigned int base1000_x_hd:1; - unsigned int base1000_x_fd:1; - } bits; - - unsigned short AsUSHORT; + struct + { + unsigned int reserved_11:12; + unsigned int base1000_t_hd:1; + unsigned int base1000_t_fd:1; + unsigned int base1000_x_hd:1; + unsigned int base1000_x_fd:1; + } bits; + + unsigned short AsUSHORT; } Mr15; /* Miscellaneous state variables. */ union { - struct - { - unsigned int toggle_tx:1; - unsigned int toggle_rx:1; - unsigned int np_rx:1; - unsigned int page_rx:1; - unsigned int np_loaded:1; - } bits; - - unsigned short AsUSHORT; - - #define mr_toggle_tx MrMisc.bits.toggle_tx - #define mr_toggle_rx MrMisc.bits.toggle_rx - #define mr_np_rx MrMisc.bits.np_rx - #define mr_page_rx MrMisc.bits.page_rx - #define mr_np_loaded MrMisc.bits.np_loaded + struct + { + unsigned int toggle_tx:1; + unsigned int toggle_rx:1; + unsigned int np_rx:1; + unsigned int page_rx:1; + unsigned int np_loaded:1; + } bits; + + unsigned short AsUSHORT; + + #define mr_toggle_tx MrMisc.bits.toggle_tx + #define mr_toggle_rx MrMisc.bits.toggle_rx + #define mr_np_rx MrMisc.bits.np_rx + #define mr_page_rx MrMisc.bits.page_rx + #define mr_np_loaded MrMisc.bits.np_loaded } MrMisc; @@ -377,7 +375,6 @@ typedef struct } AN_STATE_INFO, *PAN_STATE_INFO; - /******************************************************************************/ /* Return code of Autoneg8023z. */ /******************************************************************************/ @@ -391,7 +388,6 @@ typedef enum } AUTONEG_STATUS, *PAUTONEG_STATUS; - /******************************************************************************/ /* Function prototypes. */ /******************************************************************************/ @@ -400,7 +396,6 @@ AUTONEG_STATUS Autoneg8023z(PAN_STATE_INFO pAnInfo); void AutonegInit(PAN_STATE_INFO pAnInfo); - /******************************************************************************/ /* The following functions are defined in the os-dependent module. */ /******************************************************************************/ @@ -410,6 +405,4 @@ void MM_AnTxIdle(PAN_STATE_INFO pAnInfo); char MM_AnRxConfig(PAN_STATE_INFO pAnInfo, unsigned short *pRxConfig); - #endif /* AUTONEG_H */ - diff --git a/drivers/bcm570x_bits.h b/drivers/bcm570x_bits.h index 79b1052de..615d61e98 100644 --- a/drivers/bcm570x_bits.h +++ b/drivers/bcm570x_bits.h @@ -17,7 +17,6 @@ #define BITS_H - /******************************************************************************/ /* Bit Mask definitions */ /******************************************************************************/ @@ -56,4 +55,3 @@ #define BIT_31 0x80000000 #endif /* BITS_H */ - diff --git a/drivers/bcm570x_debug.h b/drivers/bcm570x_debug.h index 0a688cfcd..88e209b0f 100644 --- a/drivers/bcm570x_debug.h +++ b/drivers/bcm570x_debug.h @@ -34,7 +34,7 @@ #define CP_RESET 0x200000 #define CP_ALL (CP_INIT | CP_SEND | CP_RCV | CP_INT | \ - CP_RESET | CP_UINIT) + CP_RESET | CP_UINIT) #define CP_MASK 0xffff0000 @@ -94,7 +94,7 @@ #if DBG #define DbgMessage(CNTRL, MESSAGE) \ if((CNTRL & DBG_MSG_CP) && ((CNTRL & LV_MASK) <= DBG_MSG_LV)) \ - printf MESSAGE + printf MESSAGE #define DbgBreak() DbgBreakPoint() #undef STATIC #define STATIC @@ -106,6 +106,4 @@ #endif /* DBG */ - #endif /* DEBUG_H */ - diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h index 79073a8e4..607f3fd06 100644 --- a/drivers/bcm570x_lm.h +++ b/drivers/bcm570x_lm.h @@ -20,7 +20,6 @@ #include "bcm570x_bits.h" - /******************************************************************************/ /* Basic types. */ /******************************************************************************/ @@ -50,13 +49,13 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; /* void LM_INC_PHYSICAL_ADDRESS(PLM_PHYSICAL_ADDRESS pAddr,LM_UINT32 IncSize) */ #define LM_INC_PHYSICAL_ADDRESS(pAddr, IncSize) \ { \ - LM_UINT32 OrgLow; \ - \ - OrgLow = (pAddr)->Low; \ - (pAddr)->Low += IncSize; \ - if((pAddr)->Low < OrgLow) { \ - (pAddr)->High++; /* Wrap around. */ \ - } \ + LM_UINT32 OrgLow; \ + \ + OrgLow = (pAddr)->Low; \ + (pAddr)->Low += IncSize; \ + if((pAddr)->Low < OrgLow) { \ + (pAddr)->High++; /* Wrap around. */ \ + } \ } @@ -69,7 +68,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; #endif /* OFFSETOF */ - /******************************************************************************/ /* Simple macros. */ /******************************************************************************/ @@ -103,7 +101,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5]; - /******************************************************************************/ /* Constants. */ /******************************************************************************/ @@ -133,7 +130,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS; #define LM_PROMISCUOUS_MODE 0x10000 - /******************************************************************************/ /* PCI registers. */ /******************************************************************************/ @@ -191,12 +187,11 @@ typedef struct { #define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \ typedef struct { \ - LM_FRAG_LIST FragList; \ - LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ + LM_FRAG_LIST FragList; \ + LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1]; \ } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME - /******************************************************************************/ /* Status codes. */ /******************************************************************************/ @@ -223,7 +218,6 @@ typedef struct { typedef LM_UINT LM_STATUS, *PLM_STATUS; - /******************************************************************************/ /* Requested media type. */ /******************************************************************************/ @@ -247,7 +241,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS; typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; - /******************************************************************************/ /* Media type. */ /******************************************************************************/ @@ -262,7 +255,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE; typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; - /******************************************************************************/ /* Line speed. */ /******************************************************************************/ @@ -275,7 +267,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE; typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; - /******************************************************************************/ /* Duplex mode. */ /******************************************************************************/ @@ -287,7 +278,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED; typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; - /******************************************************************************/ /* Power state. */ /******************************************************************************/ @@ -300,7 +290,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE; typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; - /******************************************************************************/ /* Task offloading. */ /******************************************************************************/ @@ -317,7 +306,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE; typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; - /******************************************************************************/ /* Flow control. */ /******************************************************************************/ @@ -337,7 +325,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD; typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; - /******************************************************************************/ /* Wake up mode. */ /******************************************************************************/ @@ -350,7 +337,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL; typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; - /******************************************************************************/ /* Counters. */ /******************************************************************************/ @@ -377,7 +363,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE; typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE; - /******************************************************************************/ /* Forward definition. */ /******************************************************************************/ @@ -386,7 +371,6 @@ typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK; typedef struct _LM_PACKET *PLM_PACKET; - /******************************************************************************/ /* Function prototypes. */ /******************************************************************************/ @@ -427,7 +411,6 @@ LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice); int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration); - /******************************************************************************/ /* These are the OS specific functions called by LMAC. */ /******************************************************************************/ @@ -466,4 +449,3 @@ LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice); #endif /* LM_H */ - diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h index badd0d299..b7cbf8abd 100644 --- a/drivers/bcm570x_mm.h +++ b/drivers/bcm570x_mm.h @@ -56,14 +56,14 @@ typedef int spinlock_t; /* Embedded device control */ typedef struct _UM_DEVICE_BLOCK { LM_DEVICE_BLOCK lm_dev; - pci_dev_t pdev; + pci_dev_t pdev; char *name; void *mem_list[MAX_MEM]; dma_addr_t dma_list[MAX_MEM]; int mem_size_list[MAX_MEM]; int mem_list_num; - int mtu; - int index; + int mtu; + int index; int opened; int delayed_link_ind; /* Delay link status during initial load */ int adapter_just_inited; /* the first few seconds after init. */ @@ -72,7 +72,7 @@ typedef struct _UM_DEVICE_BLOCK { int adaptive_expiry; int crc_counter_expiry; /* new -- unsupported */ int poll_tib_expiry; /* new -- unsupported */ - int tx_full; + int tx_full; int tx_queued; int line_speed; /* in Mbps, 0 if link is down */ UM_RX_PACKET_Q rx_out_of_buf_q; @@ -81,14 +81,14 @@ typedef struct _UM_DEVICE_BLOCK { int rx_buf_repl_panic_thresh; int rx_buf_align; /* new -- unsupported */ int do_global_lock; - mutex_t global_lock; - mutex_t undi_lock; + mutex_t global_lock; + mutex_t undi_lock; long undi_flags; volatile int interrupt; int tasklet_pending; int tasklet_busy; /* new -- unsupported */ - int rx_pkt; - int tx_pkt; + int rx_pkt; + int tx_pkt; #ifdef NICE_SUPPORT /* unsupported, this is a linux ioctl */ void (*nice_rx)(void*, void* ); void* nice_ctx; @@ -100,19 +100,19 @@ typedef struct _UM_DEVICE_BLOCK { unsigned int rx_curr_coalesce_ticks; unsigned int tx_curr_coalesce_frames; /* new -- unsupported */ #if TIGON3_DEBUG /* new -- unsupported */ - uint tx_zc_count; - uint tx_chksum_count; - uint tx_himem_count; - uint rx_good_chksum_count; + uint tx_zc_count; + uint tx_chksum_count; + uint tx_himem_count; + uint rx_good_chksum_count; #endif - unsigned int rx_bad_chksum_count; /* new -- unsupported */ - unsigned int rx_misc_errors; /* new -- unsupported */ + unsigned int rx_bad_chksum_count; /* new -- unsupported */ + unsigned int rx_misc_errors; /* new -- unsupported */ } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK; /* Physical/PCI DMA address */ typedef union { - dma_addr_t dma_map; + dma_addr_t dma_map; } dma_map_t; /* Packet */ @@ -130,8 +130,8 @@ _UM_PACKET { /* Macro for setting 64bit address struct */ #define set_64bit_addr(paddr, low, high) \ - (paddr)->Low = low; \ - (paddr)->High = high; + (paddr)->Low = low; \ + (paddr)->High = high; /* Assume that PCI controller's view of host memory is same as host */ diff --git a/drivers/bcm570x_queue.h b/drivers/bcm570x_queue.h index bc32ad70f..336b3caa4 100644 --- a/drivers/bcm570x_queue.h +++ b/drivers/bcm570x_queue.h @@ -103,14 +103,13 @@ typedef struct { /* Declare queue type macro. */ #define DECLARE_QUEUE_TYPE(_QUEUE_TYPE, _QUEUE_SIZE) \ - \ + \ typedef struct { \ - QQ_CONTAINER Container; \ - PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \ + QQ_CONTAINER Container; \ + PQQ_ENTRY EntryBuffer[_QUEUE_SIZE]; \ } _QUEUE_TYPE, *P##_QUEUE_TYPE - /******************************************************************************/ /* Compilation switches. */ /******************************************************************************/ @@ -144,7 +143,6 @@ unsigned int QueueSize) { } /* QQ_InitQueue */ - /******************************************************************************/ /* Description: */ /* */ @@ -161,7 +159,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_Full */ - /******************************************************************************/ /* Description: */ /* */ @@ -174,7 +171,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_Empty */ - /******************************************************************************/ /* Description: */ /* */ @@ -187,7 +183,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_GetSize */ - /******************************************************************************/ /* Description: */ /* */ @@ -200,7 +195,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_GetEntryCnt */ - /******************************************************************************/ /* Description: */ /* */ @@ -218,7 +212,7 @@ PQQ_ENTRY pEntry) { #if !defined(QQ_NO_OVERFLOW_CHECK) if(Head == pQueue->Tail) { - return 0; + return 0; } /* if */ #endif /* QQ_NO_OVERFLOW_CHECK */ @@ -231,7 +225,6 @@ PQQ_ENTRY pEntry) { } /* QQ_PushHead */ - /******************************************************************************/ /* Description: */ /* */ @@ -247,13 +240,13 @@ PQQ_ENTRY pEntry) { Tail = pQueue->Tail; if(Tail == 0) { - Tail = pQueue->Size; + Tail = pQueue->Size; } /* if */ Tail--; #if !defined(QQ_NO_OVERFLOW_CHECK) if(Tail == pQueue->Head) { - return 0; + return 0; } /* if */ #endif /* QQ_NO_OVERFLOW_CHECK */ @@ -266,7 +259,6 @@ PQQ_ENTRY pEntry) { } /* QQ_PushTail */ - /******************************************************************************/ /* Description: */ /* */ @@ -282,12 +274,12 @@ PQQ_CONTAINER pQueue) { #if !defined(QQ_NO_UNDERFLOW_CHECK) if(Head == pQueue->Tail) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } /* if */ #endif /* QQ_NO_UNDERFLOW_CHECK */ if(Head == 0) { - Head = pQueue->Size; + Head = pQueue->Size; } /* if */ Head--; @@ -304,7 +296,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_PopHead */ - /******************************************************************************/ /* Description: */ /* */ @@ -320,7 +311,7 @@ PQQ_CONTAINER pQueue) { #if !defined(QQ_NO_UNDERFLOW_CHECK) if(Tail == pQueue->Head) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } /* if */ #endif /* QQ_NO_UNDERFLOW_CHECK */ @@ -337,7 +328,6 @@ PQQ_CONTAINER pQueue) { } /* QQ_PopTail */ - /******************************************************************************/ /* Description: */ /* */ @@ -350,16 +340,16 @@ QQ_GetHead( { if(Idx >= atomic_read(&pQueue->EntryCnt)) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } if(pQueue->Head > Idx) { - Idx = pQueue->Head - Idx; + Idx = pQueue->Head - Idx; } else { - Idx = pQueue->Size - (Idx - pQueue->Head); + Idx = pQueue->Size - (Idx - pQueue->Head); } Idx--; @@ -367,7 +357,6 @@ QQ_GetHead( } - /******************************************************************************/ /* Description: */ /* */ @@ -380,13 +369,13 @@ QQ_GetTail( { if(Idx >= atomic_read(&pQueue->EntryCnt)) { - return (PQQ_ENTRY) 0; + return (PQQ_ENTRY) 0; } Idx += pQueue->Tail; if(Idx >= pQueue->Size) { - Idx = Idx - pQueue->Size; + Idx = Idx - pQueue->Size; } return pQueue->Array[Idx]; @@ -395,5 +384,4 @@ QQ_GetTail( #endif /* QQ_USE_MACROS */ - #endif /* QUEUE_H */ diff --git a/drivers/cfb_console.c b/drivers/cfb_console.c index d428b174e..22382afdc 100644 --- a/drivers/cfb_console.c +++ b/drivers/cfb_console.c @@ -60,34 +60,34 @@ VIDEO_GETC_FCT - keyboard_getc function CONFIG_CONSOLE_CURSOR - on/off drawing cursor is done with delay - loop in VIDEO_TSTC_FCT (i8042) + loop in VIDEO_TSTC_FCT (i8042) CFG_CONSOLE_BLINK_COUNT - value for delay loop - blink rate CONFIG_CONSOLE_TIME - display time/date in upper right corner, - needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR + needs CFG_CMD_DATE and CONFIG_CONSOLE_CURSOR CONFIG_VIDEO_LOGO - display Linux Logo in upper left corner CONFIG_VIDEO_BMP_LOGO - use bmp_logo instead of linux_logo CONFIG_CONSOLE_EXTRA_INFO - display additional board information strings - that normaly goes to serial port. This define - requires a board specific function: - video_drawstring (VIDEO_INFO_X, - VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, - info); - that fills a info buffer at i=row. - s.a: board/eltec/bab7xx. + that normaly goes to serial port. This define + requires a board specific function: + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, + info); + that fills a info buffer at i=row. + s.a: board/eltec/bab7xx. CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be initialised - as an output only device. The Keyboard driver - will not be set-up. This may be used, if you - have none or more than one Keyboard devices - (USB Keyboard, AT Keyboard). + as an output only device. The Keyboard driver + will not be set-up. This may be used, if you + have none or more than one Keyboard devices + (USB Keyboard, AT Keyboard). CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last character. No - blinking is provided. Uses the macros CURSOR_SET - and CURSOR_OFF. + blinking is provided. Uses the macros CURSOR_SET + and CURSOR_OFF. CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the - graphic chip. Uses the macro CURSOR_SET. - ATTENTION: If booting an OS, the display driver - must disable the hardware register of the graphic - chip. Otherwise a blinking field is displayed + graphic chip. Uses the macro CURSOR_SET. + ATTENTION: If booting an OS, the display driver + must disable the hardware register of the graphic + chip. Otherwise a blinking field is displayed */ #include <common.h> @@ -214,7 +214,7 @@ void console_cursor (int state); #endif #define CURSOR_ON #define CURSOR_OFF video_putchar(console_col * VIDEO_FONT_WIDTH,\ - console_row * VIDEO_FONT_HEIGHT, ' '); + console_row * VIDEO_FONT_HEIGHT, ' '); #define CURSOR_SET video_set_cursor(); #endif /* CONFIG_VIDEO_SW_CURSOR */ @@ -226,7 +226,7 @@ void console_cursor (int state); #define CURSOR_ON #define CURSOR_OFF #define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ - (console_row * VIDEO_FONT_HEIGHT) + VIDEO_LOGO_HEIGHT); + (console_row * VIDEO_FONT_HEIGHT) + VIDEO_LOGO_HEIGHT); #endif /* CONFIG_VIDEO_HW_CURSOR */ #ifdef CONFIG_VIDEO_LOGO @@ -281,9 +281,9 @@ void console_cursor (int state); #ifdef VIDEO_FB_LITTLE_ENDIAN #define SWAP16(x) ((((x) & 0x00ff) << 8) | ( (x) >> 8)) #define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\ - (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) + (((x) & 0x00ff0000) >> 8) | (((x) & 0xff000000) >> 24) ) #define SHORTSWAP32(x) ((((x) & 0x000000ff) << 8) | (((x) & 0x0000ff00) >> 8)|\ - (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) ) + (((x) & 0x00ff0000) << 8) | (((x) & 0xff000000) >> 8) ) #else #define SWAP16(x) (x) #define SWAP32(x) (x) @@ -317,52 +317,52 @@ static int console_row = 0; /* cursor row */ static u32 eorx, fgx, bgx; /* color pats */ static const int video_font_draw_table8[] = { - 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, - 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, - 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, - 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff }; + 0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, + 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff, + 0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, + 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff }; static const int video_font_draw_table15[] = { - 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff }; + 0x00000000, 0x00007fff, 0x7fff0000, 0x7fff7fff }; static const int video_font_draw_table16[] = { - 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; + 0x00000000, 0x0000ffff, 0xffff0000, 0xffffffff }; static const int video_font_draw_table24[16][3] = { - { 0x00000000, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x0000ffff, 0xff000000 }, - { 0x00000000, 0x0000ffff, 0xffffffff }, - { 0x000000ff, 0xffff0000, 0x00000000 }, - { 0x000000ff, 0xffff0000, 0x00ffffff }, - { 0x000000ff, 0xffffffff, 0xff000000 }, - { 0x000000ff, 0xffffffff, 0xffffffff }, - { 0xffffff00, 0x00000000, 0x00000000 }, - { 0xffffff00, 0x00000000, 0x00ffffff }, - { 0xffffff00, 0x0000ffff, 0xff000000 }, - { 0xffffff00, 0x0000ffff, 0xffffffff }, - { 0xffffffff, 0xffff0000, 0x00000000 }, - { 0xffffffff, 0xffff0000, 0x00ffffff }, - { 0xffffffff, 0xffffffff, 0xff000000 }, - { 0xffffffff, 0xffffffff, 0xffffffff } }; + { 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x0000ffff, 0xff000000 }, + { 0x00000000, 0x0000ffff, 0xffffffff }, + { 0x000000ff, 0xffff0000, 0x00000000 }, + { 0x000000ff, 0xffff0000, 0x00ffffff }, + { 0x000000ff, 0xffffffff, 0xff000000 }, + { 0x000000ff, 0xffffffff, 0xffffffff }, + { 0xffffff00, 0x00000000, 0x00000000 }, + { 0xffffff00, 0x00000000, 0x00ffffff }, + { 0xffffff00, 0x0000ffff, 0xff000000 }, + { 0xffffff00, 0x0000ffff, 0xffffffff }, + { 0xffffffff, 0xffff0000, 0x00000000 }, + { 0xffffffff, 0xffff0000, 0x00ffffff }, + { 0xffffffff, 0xffffffff, 0xff000000 }, + { 0xffffffff, 0xffffffff, 0xffffffff } }; static const int video_font_draw_table32[16][4] = { - { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 }, - { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff }, - { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 }, - { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff }, - { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 }, - { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff }, - { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 }, - { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff }, - { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 }, - { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff }, - { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 }, - { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff }, - { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 }, - { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; + { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00000000, 0x00ffffff, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00000000, 0x00ffffff, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00000000, 0x00ffffff }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00000000 }, + { 0x00ffffff, 0x00ffffff, 0x00ffffff, 0x00ffffff } }; /******************************************************************************/ @@ -380,98 +380,98 @@ static void video_drawchars (int xx, int yy, unsigned char *s, int count) { case GDF__8BIT_INDEX: case GDF__8BIT_332RGB: - while (count--) - { - c = *s ; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) - { - u8 bits = *cdat++; - ((u32 *)dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; - ((u32 *)dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++; - } - break; + while (count--) + { + c = *s ; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) + { + u8 bits = *cdat++; + ((u32 *)dest)[0] = (video_font_draw_table8[bits >> 4] & eorx) ^ bgx; + ((u32 *)dest)[1] = (video_font_draw_table8[bits & 15] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++; + } + break; case GDF_15BIT_555RGB: - while (count--) - { - c = *s ; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) - { - u8 bits = *cdat++; - ((u32 *)dest)[0] = SHORTSWAP32((video_font_draw_table15[bits >> 6] & eorx) ^ bgx); - ((u32 *)dest)[1] = SHORTSWAP32((video_font_draw_table15[bits >> 4 & 3] & eorx) ^ bgx); - ((u32 *)dest)[2] = SHORTSWAP32((video_font_draw_table15[bits >> 2 & 3] & eorx) ^ bgx); - ((u32 *)dest)[3] = SHORTSWAP32((video_font_draw_table15[bits & 3] & eorx) ^ bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++ ; - } - break; + while (count--) + { + c = *s ; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) + { + u8 bits = *cdat++; + ((u32 *)dest)[0] = SHORTSWAP32((video_font_draw_table15[bits >> 6] & eorx) ^ bgx); + ((u32 *)dest)[1] = SHORTSWAP32((video_font_draw_table15[bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *)dest)[2] = SHORTSWAP32((video_font_draw_table15[bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *)dest)[3] = SHORTSWAP32((video_font_draw_table15[bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++ ; + } + break; case GDF_16BIT_565RGB: - while (count--) - { - c = *s ; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) - { - u8 bits = *cdat++; - ((u32 *)dest)[0] = SHORTSWAP32((video_font_draw_table16[bits >> 6] & eorx) ^ bgx); - ((u32 *)dest)[1] = SHORTSWAP32((video_font_draw_table16[bits >> 4 & 3] & eorx) ^ bgx); - ((u32 *)dest)[2] = SHORTSWAP32((video_font_draw_table16[bits >> 2 & 3] & eorx) ^ bgx); - ((u32 *)dest)[3] = SHORTSWAP32((video_font_draw_table16[bits & 3] & eorx) ^ bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++ ; - } - break; + while (count--) + { + c = *s ; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) + { + u8 bits = *cdat++; + ((u32 *)dest)[0] = SHORTSWAP32((video_font_draw_table16[bits >> 6] & eorx) ^ bgx); + ((u32 *)dest)[1] = SHORTSWAP32((video_font_draw_table16[bits >> 4 & 3] & eorx) ^ bgx); + ((u32 *)dest)[2] = SHORTSWAP32((video_font_draw_table16[bits >> 2 & 3] & eorx) ^ bgx); + ((u32 *)dest)[3] = SHORTSWAP32((video_font_draw_table16[bits & 3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++ ; + } + break; case GDF_32BIT_X888RGB: - while (count--) - { - c = *s ; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) - { - u8 bits = *cdat++; - ((u32 *)dest)[0] = SWAP32((video_font_draw_table32[bits >> 4][0] & eorx) ^ bgx); - ((u32 *)dest)[1] = SWAP32((video_font_draw_table32[bits >> 4][1] & eorx) ^ bgx); - ((u32 *)dest)[2] = SWAP32((video_font_draw_table32[bits >> 4][2] & eorx) ^ bgx); - ((u32 *)dest)[3] = SWAP32((video_font_draw_table32[bits >> 4][3] & eorx) ^ bgx); - ((u32 *)dest)[4] = SWAP32((video_font_draw_table32[bits & 15][0] & eorx) ^ bgx); - ((u32 *)dest)[5] = SWAP32((video_font_draw_table32[bits & 15][1] & eorx) ^ bgx); - ((u32 *)dest)[6] = SWAP32((video_font_draw_table32[bits & 15][2] & eorx) ^ bgx); - ((u32 *)dest)[7] = SWAP32((video_font_draw_table32[bits & 15][3] & eorx) ^ bgx); - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++ ; - } - break; + while (count--) + { + c = *s ; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) + { + u8 bits = *cdat++; + ((u32 *)dest)[0] = SWAP32((video_font_draw_table32[bits >> 4][0] & eorx) ^ bgx); + ((u32 *)dest)[1] = SWAP32((video_font_draw_table32[bits >> 4][1] & eorx) ^ bgx); + ((u32 *)dest)[2] = SWAP32((video_font_draw_table32[bits >> 4][2] & eorx) ^ bgx); + ((u32 *)dest)[3] = SWAP32((video_font_draw_table32[bits >> 4][3] & eorx) ^ bgx); + ((u32 *)dest)[4] = SWAP32((video_font_draw_table32[bits & 15][0] & eorx) ^ bgx); + ((u32 *)dest)[5] = SWAP32((video_font_draw_table32[bits & 15][1] & eorx) ^ bgx); + ((u32 *)dest)[6] = SWAP32((video_font_draw_table32[bits & 15][2] & eorx) ^ bgx); + ((u32 *)dest)[7] = SWAP32((video_font_draw_table32[bits & 15][3] & eorx) ^ bgx); + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++ ; + } + break; case GDF_24BIT_888RGB: - while (count--) - { - c = *s ; - cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; - for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) - { - u8 bits = *cdat++; - ((u32 *)dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx; - ((u32 *)dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx; - ((u32 *)dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; - ((u32 *)dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; - ((u32 *)dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx; - ((u32 *)dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx; - } - dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; - s++ ; - } - break; + while (count--) + { + c = *s ; + cdat = video_fontdata + c * VIDEO_FONT_HEIGHT; + for (rows = VIDEO_FONT_HEIGHT, dest = dest0; rows--; dest += VIDEO_LINE_LEN) + { + u8 bits = *cdat++; + ((u32 *)dest)[0] = (video_font_draw_table24[bits >> 4][0] & eorx) ^ bgx; + ((u32 *)dest)[1] = (video_font_draw_table24[bits >> 4][1] & eorx) ^ bgx; + ((u32 *)dest)[2] = (video_font_draw_table24[bits >> 4][2] & eorx) ^ bgx; + ((u32 *)dest)[3] = (video_font_draw_table24[bits & 15][0] & eorx) ^ bgx; + ((u32 *)dest)[4] = (video_font_draw_table24[bits & 15][1] & eorx) ^ bgx; + ((u32 *)dest)[5] = (video_font_draw_table24[bits & 15][2] & eorx) ^ bgx; + } + dest0 += VIDEO_FONT_WIDTH * VIDEO_PIXEL_SIZE; + s++ ; + } + break; } } @@ -500,7 +500,7 @@ static void video_set_cursor(void) eorx = fgx ^ bgx; /* draw cursor */ video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); + console_row * VIDEO_FONT_HEIGHT, ' '); /* restore drawing colors */ eorx = fgx; fgx = bgx; @@ -524,24 +524,24 @@ void console_cursor (int state) sprintf(info, " %02d:%02d:%02d ", tm.tm_hour, tm.tm_min, tm.tm_sec); video_drawstring(VIDEO_VISIBLE_COLS-10*VIDEO_FONT_WIDTH, - VIDEO_INFO_Y, info); + VIDEO_INFO_Y, info); sprintf(info, "%02d.%02d.%04d", tm.tm_mday, tm.tm_mon, tm.tm_year); video_drawstring(VIDEO_VISIBLE_COLS-10*VIDEO_FONT_WIDTH, - VIDEO_INFO_Y+1*VIDEO_FONT_HEIGHT, info); + VIDEO_INFO_Y+1*VIDEO_FONT_HEIGHT, info); } #endif if (state && (last_state != state)) { - video_set_cursor(); + video_set_cursor(); } if (!state && (last_state != state)) { - /* clear cursor */ - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); + /* clear cursor */ + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, ' '); } last_state = state; @@ -554,7 +554,7 @@ void console_cursor (int state) static void memsetl (int *p, int c, int v) { while (c--) - *(p++) = v; + *(p++) = v; } #endif @@ -564,7 +564,7 @@ static void memsetl (int *p, int c, int v) static void memcpyl (int *d, int *s, int c) { while (c--) - *(d++) = *(s++); + *(d++) = *(s++); } #endif @@ -612,13 +612,13 @@ static void console_back (void) if (console_col < 0) { - console_col = CONSOLE_COLS - 1; - console_row--; - if (console_row < 0) - console_row = 0; + console_col = CONSOLE_COLS - 1; + console_row--; + if (console_row < 0) + console_row = 0; } video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, ' '); + console_row * VIDEO_FONT_HEIGHT, ' '); } /*****************************************************************************/ @@ -647,39 +647,38 @@ void video_putc (const char c) switch (c) { case 13: /* ignore */ - break; + break; case '\n': /* next line */ - console_newline(); - break; + console_newline(); + break; case 9: /* tab 8 */ - CURSOR_OFF - console_col |= 0x0008; - console_col &= ~0x0007; + CURSOR_OFF + console_col |= 0x0008; + console_col &= ~0x0007; - if (console_col >= CONSOLE_COLS) - console_newline(); - break; + if (console_col >= CONSOLE_COLS) + console_newline(); + break; case 8: /* backspace */ - console_back(); - break; + console_back(); + break; default: /* draw the char */ - video_putchar (console_col * VIDEO_FONT_WIDTH, - console_row * VIDEO_FONT_HEIGHT, c); - console_col++ ; + video_putchar (console_col * VIDEO_FONT_WIDTH, + console_row * VIDEO_FONT_HEIGHT, c); + console_col++ ; - /* check for newline */ - if (console_col >= CONSOLE_COLS) - console_newline(); + /* check for newline */ + if (console_col >= CONSOLE_COLS) + console_newline(); } CURSOR_SET } - /*****************************************************************************/ void video_puts (const char *s) @@ -687,7 +686,7 @@ void video_puts (const char *s) int count = strlen(s); while(count--) - video_putc(*s++); + video_putc(*s++); } /*****************************************************************************/ @@ -697,25 +696,25 @@ void logo_plot (void *screen, int width, int x, int y) { int skip = (width - VIDEO_LOGO_WIDTH) * VIDEO_PIXEL_SIZE, - xcount, i, - ycount = VIDEO_LOGO_HEIGHT; + xcount, i, + ycount = VIDEO_LOGO_HEIGHT; unsigned char - *source, - *dest = (unsigned char *) screen + ((y * width * VIDEO_PIXEL_SIZE) + x), - r, g, b, *logo_red, *logo_blue, *logo_green; + *source, + *dest = (unsigned char *) screen + ((y * width * VIDEO_PIXEL_SIZE) + x), + r, g, b, *logo_red, *logo_blue, *logo_green; #ifdef CONFIG_VIDEO_BMP_LOGO source = bmp_logo_bitmap; - + /* Allocate temporary space for computing colormap */ logo_red = malloc (BMP_LOGO_COLORS); logo_green = malloc (BMP_LOGO_COLORS); logo_blue = malloc (BMP_LOGO_COLORS); /* Compute color map */ for (i = 0; i < VIDEO_LOGO_COLORS; i++) { - logo_red [i] = (bmp_logo_palette [i] & 0x0f00) >> 4; - logo_green [i] = (bmp_logo_palette [i] & 0x00f0); - logo_blue [i] = (bmp_logo_palette [i] & 0x000f) << 4; + logo_red [i] = (bmp_logo_palette [i] & 0x0f00) >> 4; + logo_green [i] = (bmp_logo_palette [i] & 0x00f0); + logo_blue [i] = (bmp_logo_palette [i] & 0x000f) << 4; } #else source = linux_logo; @@ -723,61 +722,61 @@ void logo_plot (void *screen, int width, int x, int y) logo_green = linux_logo_green; logo_blue = linux_logo_blue; #endif - + if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { - for (i = 0; i < VIDEO_LOGO_COLORS; i++) - { - video_set_lut (i + VIDEO_LOGO_LUT_OFFSET, - logo_red [i], logo_green [i], logo_blue [i]); - } + for (i = 0; i < VIDEO_LOGO_COLORS; i++) + { + video_set_lut (i + VIDEO_LOGO_LUT_OFFSET, + logo_red [i], logo_green [i], logo_blue [i]); + } } while (ycount--) { - xcount = VIDEO_LOGO_WIDTH; - while (xcount--) - { - r = logo_red [*source - VIDEO_LOGO_LUT_OFFSET]; - g = logo_green [*source - VIDEO_LOGO_LUT_OFFSET]; - b = logo_blue [*source - VIDEO_LOGO_LUT_OFFSET]; - - switch (VIDEO_DATA_FORMAT) - { - case GDF__8BIT_INDEX: - *dest = *source; - break; - case GDF__8BIT_332RGB: - *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); - break; - case GDF_15BIT_555RGB: - *(unsigned short *)dest = - SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); - break; - case GDF_16BIT_565RGB: - *(unsigned short *)dest = - SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3))); - break; - case GDF_32BIT_X888RGB: - *(unsigned long *)dest = - SWAP32((unsigned long)((r<<16) | (g<<8) | b)); - break; - case GDF_24BIT_888RGB: + xcount = VIDEO_LOGO_WIDTH; + while (xcount--) + { + r = logo_red [*source - VIDEO_LOGO_LUT_OFFSET]; + g = logo_green [*source - VIDEO_LOGO_LUT_OFFSET]; + b = logo_blue [*source - VIDEO_LOGO_LUT_OFFSET]; + + switch (VIDEO_DATA_FORMAT) + { + case GDF__8BIT_INDEX: + *dest = *source; + break; + case GDF__8BIT_332RGB: + *dest = ((r>>5)<<5) | ((g>>5)<<2) | (b>>6); + break; + case GDF_15BIT_555RGB: + *(unsigned short *)dest = + SWAP16((unsigned short)(((r>>3)<<10) | ((g>>3)<<5) | (b>>3))); + break; + case GDF_16BIT_565RGB: + *(unsigned short *)dest = + SWAP16((unsigned short)(((r>>3)<<11) | ((g>>2)<<5) | (b>>3))); + break; + case GDF_32BIT_X888RGB: + *(unsigned long *)dest = + SWAP32((unsigned long)((r<<16) | (g<<8) | b)); + break; + case GDF_24BIT_888RGB: #ifdef VIDEO_FB_LITTLE_ENDIAN - dest[0] = b; - dest[1] = g; - dest[2] = r; + dest[0] = b; + dest[1] = g; + dest[2] = r; #else - dest[0] = r; - dest[1] = g; - dest[2] = b; + dest[0] = r; + dest[1] = g; + dest[2] = b; #endif - break; - } - source++; - dest += VIDEO_PIXEL_SIZE; - } - dest += skip; + break; + } + source++; + dest += VIDEO_PIXEL_SIZE; + } + dest += skip; } #ifdef CONFIG_VIDEO_BMP_LOGO free (logo_red); @@ -804,10 +803,10 @@ static void *video_logo (void) for (i = 1; i < n; i++) { - video_get_info_str (i, info); - if (*info) - video_drawstring (VIDEO_INFO_X, - VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, info); + video_get_info_str (i, info); + if (*info) + video_drawstring (VIDEO_INFO_X, + VIDEO_INFO_Y + i*VIDEO_FONT_HEIGHT, info); } } #endif @@ -824,7 +823,7 @@ static int video_init(void) unsigned char color8; if ((pGD=video_hw_init()) == NULL) - return -1; + return -1; video_fb_address = (void*)VIDEO_FB_ADRS; #ifdef CONFIG_VIDEO_HW_CURSOR @@ -835,37 +834,37 @@ static int video_init(void) switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: - video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); - video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL); - fgx = 0x01010101; - bgx = 0x00000000; - break; + video_set_lut (0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); + video_set_lut (0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, CONSOLE_BG_COL); + fgx = 0x01010101; + bgx = 0x00000000; + break; case GDF__8BIT_332RGB: - color8 = ((CONSOLE_FG_COL & 0xe0) | ((CONSOLE_FG_COL>>3) & 0x1c) | CONSOLE_FG_COL>>6); - fgx = (color8<<24) | (color8<<16) | (color8<<8) | color8; - color8 = ((CONSOLE_BG_COL & 0xe0) | ((CONSOLE_BG_COL>>3) & 0x1c) | CONSOLE_BG_COL>>6); - bgx = (color8<<24) | (color8<<16) | (color8<<8) | color8; - break; + color8 = ((CONSOLE_FG_COL & 0xe0) | ((CONSOLE_FG_COL>>3) & 0x1c) | CONSOLE_FG_COL>>6); + fgx = (color8<<24) | (color8<<16) | (color8<<8) | color8; + color8 = ((CONSOLE_BG_COL & 0xe0) | ((CONSOLE_BG_COL>>3) & 0x1c) | CONSOLE_BG_COL>>6); + bgx = (color8<<24) | (color8<<16) | (color8<<8) | color8; + break; case GDF_15BIT_555RGB: - fgx = (((CONSOLE_FG_COL>>3)<<26) | ((CONSOLE_FG_COL>>3)<<21) | ((CONSOLE_FG_COL>>3)<<16) | - ((CONSOLE_FG_COL>>3)<<10) | ((CONSOLE_FG_COL>>3)<<5) | (CONSOLE_FG_COL>>3)); - bgx = (((CONSOLE_BG_COL>>3)<<26) | ((CONSOLE_BG_COL>>3)<<21) | ((CONSOLE_BG_COL>>3)<<16) | - ((CONSOLE_BG_COL>>3)<<10) | ((CONSOLE_BG_COL>>3)<<5) | (CONSOLE_BG_COL>>3)); - break; + fgx = (((CONSOLE_FG_COL>>3)<<26) | ((CONSOLE_FG_COL>>3)<<21) | ((CONSOLE_FG_COL>>3)<<16) | + ((CONSOLE_FG_COL>>3)<<10) | ((CONSOLE_FG_COL>>3)<<5) | (CONSOLE_FG_COL>>3)); + bgx = (((CONSOLE_BG_COL>>3)<<26) | ((CONSOLE_BG_COL>>3)<<21) | ((CONSOLE_BG_COL>>3)<<16) | + ((CONSOLE_BG_COL>>3)<<10) | ((CONSOLE_BG_COL>>3)<<5) | (CONSOLE_BG_COL>>3)); + break; case GDF_16BIT_565RGB: - fgx = (((CONSOLE_FG_COL>>3)<<27) | ((CONSOLE_FG_COL>>2)<<21) | ((CONSOLE_FG_COL>>3)<<16) | - ((CONSOLE_FG_COL>>3)<<11) | ((CONSOLE_FG_COL>>2)<<5) | (CONSOLE_FG_COL>>3)); - bgx = (((CONSOLE_BG_COL>>3)<<27) | ((CONSOLE_BG_COL>>2)<<21) | ((CONSOLE_BG_COL>>3)<<16) | - ((CONSOLE_BG_COL>>3)<<11) | ((CONSOLE_BG_COL>>2)<<5) | (CONSOLE_BG_COL>>3)); - break; + fgx = (((CONSOLE_FG_COL>>3)<<27) | ((CONSOLE_FG_COL>>2)<<21) | ((CONSOLE_FG_COL>>3)<<16) | + ((CONSOLE_FG_COL>>3)<<11) | ((CONSOLE_FG_COL>>2)<<5) | (CONSOLE_FG_COL>>3)); + bgx = (((CONSOLE_BG_COL>>3)<<27) | ((CONSOLE_BG_COL>>2)<<21) | ((CONSOLE_BG_COL>>3)<<16) | + ((CONSOLE_BG_COL>>3)<<11) | ((CONSOLE_BG_COL>>2)<<5) | (CONSOLE_BG_COL>>3)); + break; case GDF_32BIT_X888RGB: - fgx = (CONSOLE_FG_COL<<16) | (CONSOLE_FG_COL<<8) | CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL<<16) | (CONSOLE_BG_COL<<8) | CONSOLE_BG_COL; - break; + fgx = (CONSOLE_FG_COL<<16) | (CONSOLE_FG_COL<<8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL<<16) | (CONSOLE_BG_COL<<8) | CONSOLE_BG_COL; + break; case GDF_24BIT_888RGB: - fgx = (CONSOLE_FG_COL<<24) | (CONSOLE_FG_COL<<16) | (CONSOLE_FG_COL<<8) | CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL<<24) | (CONSOLE_BG_COL<<16) | (CONSOLE_BG_COL<<8) | CONSOLE_BG_COL; - break; + fgx = (CONSOLE_FG_COL<<24) | (CONSOLE_FG_COL<<16) | (CONSOLE_FG_COL<<8) | CONSOLE_FG_COL; + bgx = (CONSOLE_BG_COL<<24) | (CONSOLE_BG_COL<<16) | (CONSOLE_BG_COL<<8) | CONSOLE_BG_COL; + break; } eorx = fgx ^ bgx; @@ -897,48 +896,48 @@ int drv_video_init (void) /* Force console i/o to serial ? */ if ((penv = getenv ("console")) != NULL) - if (strcmp (penv, "serial") == 0) - return 0; + if (strcmp (penv, "serial") == 0) + return 0; /* Init video chip - returns with framebuffer cleared */ if (video_init() == -1) - skip_dev_init = 1; + skip_dev_init = 1; #ifdef CONFIG_VGA_AS_SINGLE_DEVICE /* Devices VGA and Keyboard will be assigned seperately */ /* Init vga device */ if (!skip_dev_init) { - memset (&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "vga"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; - console_dev.putc = video_putc; /* 'putc' function */ - console_dev.puts = video_puts; /* 'puts' function */ - console_dev.tstc = NULL; /* 'tstc' function */ - console_dev.getc = NULL; /* 'getc' function */ - - if (device_register (&console_dev) == 0) - return 1; + memset (&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "vga"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = NULL; /* 'tstc' function */ + console_dev.getc = NULL; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; } #else PRINTD("KBD: Keyboard init ...\n"); if (VIDEO_KBD_INIT_FCT == -1) - skip_dev_init = 1; + skip_dev_init = 1; /* Init console device */ if (!skip_dev_init) { - memset (&console_dev, 0, sizeof(console_dev)); - strcpy(console_dev.name, "console"); - console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ - console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; - console_dev.putc = video_putc; /* 'putc' function */ - console_dev.puts = video_puts; /* 'puts' function */ - console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ - console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ - - if (device_register (&console_dev) == 0) - return 1; + memset (&console_dev, 0, sizeof(console_dev)); + strcpy(console_dev.name, "console"); + console_dev.ext = DEV_EXT_VIDEO; /* Video extensions */ + console_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; + console_dev.putc = video_putc; /* 'putc' function */ + console_dev.puts = video_puts; /* 'puts' function */ + console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ + console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ + + if (device_register (&console_dev) == 0) + return 1; } #endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ /* No console dev available */ @@ -946,10 +945,3 @@ int drv_video_init (void) } #endif /* CONFIG_CFB_CONSOLE */ - - - - - - - diff --git a/drivers/ct69000.c b/drivers/ct69000.c index 563556285..ba6966387 100644 --- a/drivers/ct69000.c +++ b/drivers/ct69000.c @@ -31,46 +31,46 @@ Parameters can be set via the variable "videomode" in the environment. 2 diferent ways are possible: "videomode=301" - 301 is a hexadecimal number describing the VESA - mode. Following modes are implemented: - - Colors 640x480 800x600 1024x768 1152x864 - --------+----------------------------------- - 8 bits | 0x301 0x303 0x305 0x161 - 15 bits | 0x310 0x313 0x316 0x162 - 16 bits | 0x311 0x314 0x317 0x163 - 24 bits | 0x312 0x315 0x318 ? - --------+----------------------------------- + mode. Following modes are implemented: + + Colors 640x480 800x600 1024x768 1152x864 + --------+----------------------------------- + 8 bits | 0x301 0x303 0x305 0x161 + 15 bits | 0x310 0x313 0x316 0x162 + 16 bits | 0x311 0x314 0x317 0x163 + 24 bits | 0x312 0x315 0x318 ? + --------+----------------------------------- "videomode=bootargs" - - the parameters are parsed from the bootargs. - The format is "NAME:VALUE,NAME:VALUE" etc. - Ex.: - "bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000" - Parameters not included in the list will be taken from - the default mode, which is one of the following: - mode:0 640x480x24 - mode:1 800x600x16 - mode:2 1024x768x8 - mode:3 960x720x24 - mode:4 1152x864x16 - if "mode" is not provided within the parameter list, - mode:0 is assumed. - Following parameters are supported: - x xres = visible resolution horizontal - y yres = visible resolution vertical - pclk pixelclocks in pico sec - le left_marging time from sync to picture in pixelclocks - ri right_marging time from picture to sync in pixelclocks - up upper_margin time from sync to picture - lo lower_margin - hs hsync_len length of horizontal sync - vs vsync_len length of vertical sync - sync see FB_SYNC_* - vmode see FB_VMODE_* - depth Color depth in bits per pixel - All other parameters in the variable bootargs are ignored. - It is also possible to set the parameters direct in the - variable "videomode", or in another variable i.e. - "myvideo" and setting the variable "videomode=myvideo".. + - the parameters are parsed from the bootargs. + The format is "NAME:VALUE,NAME:VALUE" etc. + Ex.: + "bootargs=video=ctfb:x:800,y:600,depth:16,pclk:25000" + Parameters not included in the list will be taken from + the default mode, which is one of the following: + mode:0 640x480x24 + mode:1 800x600x16 + mode:2 1024x768x8 + mode:3 960x720x24 + mode:4 1152x864x16 + if "mode" is not provided within the parameter list, + mode:0 is assumed. + Following parameters are supported: + x xres = visible resolution horizontal + y yres = visible resolution vertical + pclk pixelclocks in pico sec + le left_marging time from sync to picture in pixelclocks + ri right_marging time from picture to sync in pixelclocks + up upper_margin time from sync to picture + lo lower_margin + hs hsync_len length of horizontal sync + vs vsync_len length of vertical sync + sync see FB_SYNC_* + vmode see FB_VMODE_* + depth Color depth in bits per pixel + All other parameters in the variable bootargs are ignored. + It is also possible to set the parameters direct in the + variable "videomode", or in another variable i.e. + "myvideo" and setting the variable "videomode=myvideo".. ****************************************************************************/ #include <common.h> diff --git a/drivers/dataflash.c b/drivers/dataflash.c index a0a4b62a4..26a6f84e4 100644 --- a/drivers/dataflash.c +++ b/drivers/dataflash.c @@ -97,7 +97,6 @@ int AT91F_DataflashInit (void) } - void dataflash_print_info (void) { int i; diff --git a/drivers/ds1722.c b/drivers/ds1722.c index 34eb80ca2..227d8169a 100644 --- a/drivers/ds1722.c +++ b/drivers/ds1722.c @@ -18,24 +18,24 @@ static void ds1722_select(int dev) u8 ds1722_read(int dev, int addr) { u8 res; - + ds1722_select(dev); - - ssi_tx_byte(addr); - res = ssi_rx_byte(); - + + ssi_tx_byte(addr); + res = ssi_rx_byte(); + ssi_chip_select(0); - + return res; } void ds1722_write(int dev, int addr, u8 data) { ds1722_select(dev); - - ssi_tx_byte(0x80|addr); - ssi_tx_byte(data); - + + ssi_tx_byte(0x80|addr); + ssi_tx_byte(data); + ssi_chip_select(0); } @@ -43,26 +43,26 @@ void ds1722_write(int dev, int addr, u8 data) u16 ds1722_temp(int dev, int resolution) { static int useconds[] = { - 75000, 150000, 300000, 600000, 1200000 + 75000, 150000, 300000, 600000, 1200000 }; char temp; u16 res; - - + + /* set up the desired resulotion ... */ ds1722_write(dev, 0, 0xe0 | (resolution << 1)); - + /* wait while the chip measures the tremperature */ - udelay(useconds[resolution]); - + udelay(useconds[resolution]); + res = (temp = ds1722_read(dev, 2)) << 8; - - if (temp < 0) { + + if (temp < 0) { temp = (16 - (ds1722_read(dev, 1) >> 4)) & 0x0f; } else { temp = (ds1722_read(dev, 1) >> 4); } - + switch (temp) { case 0: /* .0000 */ @@ -129,7 +129,7 @@ u16 ds1722_temp(int dev, int resolution) break; } return res; - + } int ds1722_probe(int dev) diff --git a/drivers/e1000.c b/drivers/e1000.c index b4d50b803..cc50c2687 100644 --- a/drivers/e1000.c +++ b/drivers/e1000.c @@ -6,26 +6,26 @@ tested on both gig copper and gig fiber boards ***************************************************************************/ /******************************************************************************* - + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. - - This program is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the Free - Software Foundation; either version 2 of the License, or (at your option) + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with - this program; if not, write to the Free Software Foundation, Inc., 59 + this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - + The full GNU General Public License is included in this distribution in the file called LICENSE. - + Contact Information: Linux NICS <linux.nics@intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 @@ -109,7 +109,7 @@ static int e1000_detect_gig_phy(struct e1000_hw *hw); #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) (\ writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2)))) #define E1000_READ_REG_ARRAY(a, reg, offset) ( \ - readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) + readl((a)->hw_addr + E1000_##reg + ((offset) << 2))) #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);} /****************************************************************************** @@ -133,14 +133,14 @@ e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd) /****************************************************************************** * Lowers the EEPROM's clock input. * - * hw - Struct containing variables accessed by shared code + * hw - Struct containing variables accessed by shared code * eecd - EECD's current value *****************************************************************************/ static void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd) { - /* Lower the clock input to the EEPROM (by clearing the SK bit), and then - * wait 50 microseconds. + /* Lower the clock input to the EEPROM (by clearing the SK bit), and then + * wait 50 microseconds. */ *eecd = *eecd & ~E1000_EECD_SK; E1000_WRITE_REG(hw, EECD, *eecd); @@ -163,7 +163,7 @@ e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count) /* We need to shift "count" bits out to the EEPROM. So, value in the * "data" parameter will be shifted out to the EEPROM one bit at a time. - * In order to do this, "data" must be broken down into bits. + * In order to do this, "data" must be broken down into bits. */ mask = 0x01 << (count - 1); eecd = E1000_READ_REG(hw, EECD); @@ -208,10 +208,10 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw) uint32_t i; uint16_t data; - /* In order to read a register from the EEPROM, we need to shift 16 bits + /* In order to read a register from the EEPROM, we need to shift 16 bits * in from the EEPROM. Bits are "shifted in" by raising the clock input to * the EEPROM (setting the SK bit), and then reading the value of the "DO" - * bit. During this "shifting in" process the "DI" bit should always be + * bit. During this "shifting in" process the "DI" bit should always be * clear.. */ @@ -241,7 +241,7 @@ e1000_shift_in_ee_bits(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code * - * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This + * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This * function should be called before issuing a command to the EEPROM. *****************************************************************************/ static void @@ -262,7 +262,7 @@ e1000_setup_eeprom(struct e1000_hw *hw) /****************************************************************************** * Returns EEPROM to a "standby" state - * + * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static void @@ -302,7 +302,7 @@ e1000_standby_eeprom(struct e1000_hw *hw) * * hw - Struct containing variables accessed by shared code * offset - offset of word in the EEPROM to read - * data - word read from the EEPROM + * data - word read from the EEPROM *****************************************************************************/ static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t * data) @@ -447,7 +447,7 @@ e1000_write_eeprom(struct e1000_hw *hw, uint16_t Reg, uint16_t Data) /****************************************************************************** * Verifies that the EEPROM has a valid checksum - * + * * hw - Struct containing variables accessed by shared code * * Reads the first 64 16 bit words of the EEPROM and sums the values read. @@ -470,7 +470,7 @@ e1000_validate_eeprom_checksum(struct eth_device *nic) } checksum += eeprom_data; } - + if (checksum == (uint16_t) EEPROM_SUM) { return 0; } else { @@ -515,7 +515,7 @@ e1000_read_mac_addr(struct eth_device *nic) /****************************************************************************** * Initializes receive address filters. * - * hw - Struct containing variables accessed by shared code + * hw - Struct containing variables accessed by shared code * * Places the MAC address in receive address register 0 and clears the rest * of the receive addresss registers. Clears the multicast table. Assumes @@ -566,7 +566,7 @@ e1000_clear_vfta(struct e1000_hw *hw) /****************************************************************************** * Set the mac type member in the hw struct. - * + * * hw - Struct containing variables accessed by shared code *****************************************************************************/ static int @@ -711,8 +711,8 @@ e1000_reset_hw(struct e1000_hw *hw) * Performs basic configuration of the adapter. * * hw - Struct containing variables accessed by shared code - * - * Assumes that the controller has previously been reset and is in a + * + * Assumes that the controller has previously been reset and is in a * post-reset uninitialized state. Initializes the receive address registers, * multicast table, and VLAN filter table. Calls routines to setup link * configuration and flow control settings. Clears all on-chip counters. Leaves @@ -857,13 +857,13 @@ e1000_init_hw(struct eth_device *nic) /****************************************************************************** * Configures flow control and link settings. - * + * * hw - Struct containing variables accessed by shared code - * + * * Determines which flow control settings to use. Calls the apropriate media- * specific link configuration function. Configures the flow control settings. * Assuming the adapter has a valid link partner, a valid link should be - * established. Assumes the hardware has previously been reset and the + * established. Assumes the hardware has previously been reset and the * transmitter and receiver are not enabled. *****************************************************************************/ static int @@ -950,7 +950,7 @@ e1000_setup_link(struct eth_device *nic) * these registers will be set to a default threshold that may be * adjusted later by the driver's runtime code. However, if the * ability to transmit pause frames in not enabled, then these - * registers will be set to 0. + * registers will be set to 0. */ if (!(hw->fc & e1000_fc_tx_pause)) { E1000_WRITE_REG(hw, FCRTL, 0); @@ -992,8 +992,8 @@ e1000_setup_fiber_link(struct eth_device *nic) int32_t ret_val; DEBUGFUNC(); - /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be - * set when the optics detect a signal. On older adapters, it will be + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be * cleared when there is a signal */ ctrl = E1000_READ_REG(hw, CTRL); @@ -1013,12 +1013,12 @@ e1000_setup_fiber_link(struct eth_device *nic) * the device accordingly. If auto-negotiation is enabled, then software * will have to set the "PAUSE" bits to the correct value in the Tranmsit * Config Word Register (TXCW) and re-start auto-negotiation. However, if - * auto-negotiation is disabled, then software will have to manually + * auto-negotiation is disabled, then software will have to manually * configure the two flow control enable bits in the CTRL register. * * The possible values of the "fc" parameter are: * 0: Flow control is completely disabled - * 1: Rx flow control is enabled (we can receive pause frames, but + * 1: Rx flow control is enabled (we can receive pause frames, but * not send pause frames). * 2: Tx flow control is enabled (we can send pause frames but we do * not support receiving pause frames). @@ -1030,8 +1030,8 @@ e1000_setup_fiber_link(struct eth_device *nic) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); break; case e1000_fc_rx_pause: - /* RX Flow control is enabled and TX Flow control is disabled by a - * software over-ride. Since there really isn't a way to advertise + /* RX Flow control is enabled and TX Flow control is disabled by a + * software over-ride. Since there really isn't a way to advertise * that we are capable of RX Pause ONLY, we will advertise that we * support both symmetric and asymmetric RX PAUSE. Later, we will * disable the adapter's ability to send PAUSE frames. @@ -1039,7 +1039,7 @@ e1000_setup_fiber_link(struct eth_device *nic) txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); break; case e1000_fc_tx_pause: - /* TX Flow control is enabled, and RX Flow control is disabled, by a + /* TX Flow control is enabled, and RX Flow control is disabled, by a * software over-ride. */ txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); @@ -1070,8 +1070,8 @@ e1000_setup_fiber_link(struct eth_device *nic) mdelay(1); /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" - * indication in the Device Status Register. Time-out if a link isn't - * seen in 500 milliseconds seconds (Auto-negotiation should complete in + * indication in the Device Status Register. Time-out if a link isn't + * seen in 500 milliseconds seconds (Auto-negotiation should complete in * less than 500 milliseconds even if the other end is doing it in SW). */ if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { @@ -1083,7 +1083,7 @@ e1000_setup_fiber_link(struct eth_device *nic) break; } if (i == (LINK_UP_TIMEOUT / 10)) { - /* AutoNeg failed to achieve a link, so we'll call + /* AutoNeg failed to achieve a link, so we'll call * e1000_check_for_link. This routine will force the link up if we * detect a signal. This will allow us to communicate with * non-autonegotiating link partners. @@ -1284,7 +1284,7 @@ e1000_setup_copper_link(struct eth_device *nic) } } #else - /* If we do not wait for autonegtation to complete I + /* If we do not wait for autonegtation to complete I * do not see a valid link status. */ ret_val = e1000_wait_autoneg(hw); @@ -1558,7 +1558,7 @@ e1000_config_mac_to_phy(struct e1000_hw *hw) /****************************************************************************** * Forces the MAC's flow control settings. - * + * * hw - Struct containing variables accessed by shared code * * Sets the TFCE and RFCE bits in the device control register to reflect @@ -1625,7 +1625,7 @@ e1000_force_mac_fc(struct e1000_hw *hw) /****************************************************************************** * Configures flow control settings after link is established - * + * * hw - Struct containing variables accessed by shared code * * Should be called immediately after a valid link has been established. @@ -1859,8 +1859,8 @@ e1000_check_for_link(struct eth_device *nic) DEBUGFUNC(); - /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be - * set when the optics detect a signal. On older adapters, it will be + /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be + * set when the optics detect a signal. On older adapters, it will be * cleared when there is a signal */ ctrl = E1000_READ_REG(hw, CTRL); @@ -1920,7 +1920,7 @@ e1000_check_for_link(struct eth_device *nic) } } - /* Configure Flow Control now that Auto-Neg has completed. First, we + /* Configure Flow Control now that Auto-Neg has completed. First, we * need to restore the desired flow control settings because we may * have had to re-autoneg with a different link partner. */ @@ -1950,7 +1950,7 @@ e1000_check_for_link(struct eth_device *nic) NWAY_LPAR_100TX_HD_CAPS | NWAY_LPAR_100TX_FD_CAPS | NWAY_LPAR_100T4_CAPS)) { - /* If our link partner advertises anything in addition to + /* If our link partner advertises anything in addition to * gigabit, we do not need to enable TBI compatibility. */ if (hw->tbi_compatibility_on) { @@ -2151,7 +2151,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) uint32_t mask; /* We need to shift "count" number of bits out to the PHY. So, the value - * in the "data" parameter will be shifted out to the PHY one bit at a + * in the "data" parameter will be shifted out to the PHY one bit at a * time. In order to do this, "data" must be broken down into bits. */ mask = 0x01; @@ -2190,7 +2190,7 @@ e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count) * * hw - Struct containing variables accessed by shared code * -* Bits are shifted in in MSB to LSB order. +* Bits are shifted in in MSB to LSB order. ******************************************************************************/ static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw) @@ -2360,12 +2360,12 @@ e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data) } else { /* We'll need to use the SW defined pins to shift the write command * out to the PHY. We first send a preamble to the PHY to signal the - * beginning of the MII instruction. This is done by sending 32 + * beginning of the MII instruction. This is done by sending 32 * consecutive "1" bits. */ e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE); - /* Now combine the remaining required fields that will indicate a + /* Now combine the remaining required fields that will indicate a * write operation. We use this method instead of calling the * e1000_shift_out_mdi_bits routine for each field in the command. The * format of a MII write instruction is as follows: diff --git a/drivers/e1000.h b/drivers/e1000.h index ba05ac075..0fbdc90b1 100644 --- a/drivers/e1000.h +++ b/drivers/e1000.h @@ -1,25 +1,25 @@ /******************************************************************************* - + Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved. - - This program is free software; you can redistribute it and/or modify it - under the terms of the GNU General Public License as published by the Free - Software Foundation; either version 2 of the License, or (at your option) + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but WITHOUT - ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with - this program; if not, write to the Free Software Foundation, Inc., 59 + this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. - + The full GNU General Public License is included in this distribution in the file called LICENSE. - + Contact Information: Linux NICS <linux.nics@intel.com> Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 @@ -251,7 +251,7 @@ struct e1000_phy_stats { /* This defines the bits that are set in the Interrupt Mask * Set/Read Register. Each bit is documented below: * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) - * o RXSEQ = Receive Sequence Error + * o RXSEQ = Receive Sequence Error */ #define POLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ @@ -275,7 +275,7 @@ struct e1000_phy_stats { /* The number of high/low register pairs in the RAR. The RAR (Receive Address * Registers) holds the directed and multicast addresses that we monitor. We * reserve one of these spots for our directed address, allowing us room for - * E1000_RAR_ENTRIES - 1 multicast addresses. + * E1000_RAR_ENTRIES - 1 multicast addresses. */ #define E1000_RAR_ENTRIES 16 @@ -475,7 +475,7 @@ struct e1000_ffvt_entry { /* Register Set. (82543, 82544) * * Registers are defined to be 32 bits and should be accessed as 32 bit values. - * These registers are physically located on the NIC, but are mapped into the + * These registers are physically located on the NIC, but are mapped into the * host memory address space. * * RW - register is both readable and writable @@ -1248,7 +1248,7 @@ struct e1000_hw { #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ -#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery +#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery * Filtering */ #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ @@ -1287,9 +1287,9 @@ struct e1000_hw { #define ID_LED_RESERVED_0000 0x0000 #define ID_LED_RESERVED_FFFF 0xFFFF #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ - (ID_LED_OFF1_OFF2 << 8) | \ - (ID_LED_DEF1_DEF2 << 4) | \ - (ID_LED_DEF1_DEF2)) + (ID_LED_OFF1_OFF2 << 8) | \ + (ID_LED_DEF1_DEF2 << 4) | \ + (ID_LED_DEF1_DEF2)) #define ID_LED_DEF1_DEF2 0x1 #define ID_LED_DEF1_ON2 0x2 #define ID_LED_DEF1_OFF2 0x3 @@ -1410,26 +1410,26 @@ struct e1000_hw { /* The number of bits that we need to shift right to move the "pause" * bits from the EEPROM (bits 13:12) to the "pause" (bits 8:7) field - * in the TXCW register + * in the TXCW register */ #define PAUSE_SHIFT 5 /* The number of bits that we need to shift left to move the "SWDPIO" * bits from the EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field - * in the CTRL register + * in the CTRL register */ #define SWDPIO_SHIFT 17 /* The number of bits that we need to shift left to move the "SWDPIO_EXT" * bits from the EEPROM word F (bits 7:4) to the bits 11:8 of The * Extended CTRL register. - * in the CTRL register + * in the CTRL register */ #define SWDPIO__EXT_SHIFT 4 /* The number of bits that we need to shift left to move the "ILOS" * bit from the EEPROM (bit 4) to the "ILOS" (bit 7) field - * in the CTRL register + * in the CTRL register */ #define ILOS_SHIFT 3 @@ -1446,7 +1446,7 @@ struct e1000_hw { /* TBI_ACCEPT macro definition: * * This macro requires: - * adapter = a pointer to struct e1000_hw + * adapter = a pointer to struct e1000_hw * status = the 8 bit status field of the RX descriptor with EOP set * error = the 8 bit error field of the RX descriptor with EOP set * length = the sum of all the length fields of the RX descriptors that @@ -1455,7 +1455,7 @@ struct e1000_hw { * max_frame_length = the maximum frame length we want to accept. * min_frame_length = the minimum frame length we want to accept. * - * This macro is a conditional that should be used in the interrupt + * This macro is a conditional that should be used in the interrupt * handler's Rx processing routine when RxErrors have been detected. * * Typical use: @@ -1475,10 +1475,10 @@ struct e1000_hw { (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ ((last_byte) == CARRIER_EXTENSION) && \ (((status) & E1000_RXD_STAT_VP) ? \ - (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ - ((length) <= ((adapter)->max_frame_size + 1))) : \ - (((length) > (adapter)->min_frame_size) && \ - ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) + (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \ + ((length) <= ((adapter)->max_frame_size + 1))) : \ + (((length) > (adapter)->min_frame_size) && \ + ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1))))) /* Structures, enums, and macros for the PHY */ @@ -1589,7 +1589,7 @@ struct e1000_hw { * 0 = cannot comply with msg */ #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ -#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow +#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow * 0 = sending last NP */ @@ -1598,13 +1598,13 @@ struct e1000_hw { #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges * of different NP */ -#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg +#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg * 0 = cannot comply with msg */ #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow - * 0 = sending last NP + * 0 = sending last NP */ /* 1000BASE-T Control Register */ @@ -1651,18 +1651,18 @@ struct e1000_hw { #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ -#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, +#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, * 0=CLK125 toggling */ #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ /* Manual MDI configuration */ #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, - * 100BASE-TX/10BASE-T: + * 100BASE-TX/10BASE-T: * MDI Mode */ -#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled - * all speeds. +#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled + * all speeds. */ #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 10BASE-T distance @@ -1703,7 +1703,7 @@ struct e1000_hw { #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. * Will assert lost lock and bring * link down if idle not seen - * within 1ms in 1000BASE-T + * within 1ms in 1000BASE-T */ /* Number of times we will attempt to autonegotiate before downshifting if we * are the master */ diff --git a/drivers/eepro100.c b/drivers/eepro100.c index a0bb76da4..ab8f1d99e 100644 --- a/drivers/eepro100.c +++ b/drivers/eepro100.c @@ -679,11 +679,11 @@ int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, u /* Shift the enable command bits out. */ for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) { - dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - OUTW(dev, EE_ENB | dataval, SCBeeprom); - udelay(1); - OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); - udelay(1); + dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); } OUTW(dev, EE_ENB, SCBeeprom); @@ -696,11 +696,11 @@ int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, u /* Shift the write command bits out. */ for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--) { - dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; - OUTW(dev, EE_ENB | dataval, SCBeeprom); - udelay(1); - OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); - udelay(1); + dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0; + OUTW(dev, EE_ENB | dataval, SCBeeprom); + udelay(1); + OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom); + udelay(1); } /* Write the data */ @@ -730,17 +730,17 @@ int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, u tmplong = 10; do { - dataval = INW(dev, SCBeeprom); - if (dataval & EE_DATA_READ) - break; - udelay(10000); + dataval = INW(dev, SCBeeprom); + if (dataval & EE_DATA_READ) + break; + udelay(10000); } while (-- tmplong); if (tmplong == 0) { - printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); - return -1; + printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n"); + return -1; } /* Terminate the EEPROM access. */ diff --git a/drivers/i8042.c b/drivers/i8042.c index ce24fc930..e21978dc2 100644 --- a/drivers/i8042.c +++ b/drivers/i8042.c @@ -322,20 +322,20 @@ int i8042_kbd_init (void) keymap = KBD_US; if ((penv = getenv ("keymap")) != NULL) { - if (strncmp (penv, "de", 3) == 0) - keymap = KBD_GER; + if (strncmp (penv, "de", 3) == 0) + keymap = KBD_GER; } for (try = 0; try < KBD_RESET_TRIES; try++) { - if (kbd_reset() == 0) - { - kbd_mapping = keymap; - kbd_flags = NORMAL; - kbd_state = 0; - kbd_led_set(); - return 0; - } + if (kbd_reset() == 0) + { + kbd_mapping = keymap; + kbd_flags = NORMAL; + kbd_state = 0; + kbd_led_set(); + return 0; + } } return -1; } @@ -353,25 +353,25 @@ int i8042_tstc (void) #ifdef CONFIG_CONSOLE_CURSOR if (--blinkCount == 0) { - cursor_state ^= 1; - console_cursor (cursor_state); - blinkCount = CFG_CONSOLE_BLINK_COUNT; - udelay (10); + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + udelay (10); } #endif if ((in8 (I8042_STATUS_REG) & 0x01) == 0) - return 0; + return 0; else { - scan_code = in8 (I8042_DATA_REG); - if (scan_code == 0xfa) - return 0; + scan_code = in8 (I8042_DATA_REG); + if (scan_code == 0xfa) + return 0; - kbd_conv_char(scan_code); + kbd_conv_char(scan_code); - if (kbd_input != -1) - return 1; + if (kbd_input != -1) + return 1; } return 0; } @@ -389,23 +389,23 @@ int i8042_getc (void) while (kbd_input == -1) { - while ((in8 (I8042_STATUS_REG) & 0x01) == 0) - { + while ((in8 (I8042_STATUS_REG) & 0x01) == 0) + { #ifdef CONFIG_CONSOLE_CURSOR - if (--blinkCount==0) - { - cursor_state ^= 1; - console_cursor (cursor_state); - blinkCount = CFG_CONSOLE_BLINK_COUNT; - } - udelay (10); + if (--blinkCount==0) + { + cursor_state ^= 1; + console_cursor (cursor_state); + blinkCount = CFG_CONSOLE_BLINK_COUNT; + } + udelay (10); #endif - } + } - scan_code = in8 (I8042_DATA_REG); + scan_code = in8 (I8042_DATA_REG); - if (scan_code != 0xfa) - kbd_conv_char (scan_code); + if (scan_code != 0xfa) + kbd_conv_char (scan_code); } ret_chr = kbd_input; kbd_input = -1; @@ -419,62 +419,62 @@ static void kbd_conv_char (unsigned char scan_code) { if (scan_code == 0xe0) { - kbd_flags |= EXT; - return; + kbd_flags |= EXT; + return; } /* if high bit of scan_code, set break flag */ if (scan_code & 0x80) - kbd_flags |= BRK; + kbd_flags |= BRK; else - kbd_flags &= ~BRK; + kbd_flags &= ~BRK; if ((scan_code == 0xe1) || (kbd_flags & E1)) { - if (scan_code == 0xe1) - { - kbd_flags ^= BRK; /* reset the break flag */ - kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ - } - return; + if (scan_code == 0xe1) + { + kbd_flags ^= BRK; /* reset the break flag */ + kbd_flags ^= E1; /* bitwise EXOR with E1 flag */ + } + return; } scan_code &= 0x7f; if (kbd_flags & EXT) { - int i; - - kbd_flags ^= EXT; - for (i=0; ext_key_map[i]; i++) - { - if (ext_key_map[i] == scan_code) - { - scan_code = 0x80 + i; - break; - } - } - /* not found ? */ - if (!ext_key_map[i]) - return; + int i; + + kbd_flags ^= EXT; + for (i=0; ext_key_map[i]; i++) + { + if (ext_key_map[i] == scan_code) + { + scan_code = 0x80 + i; + break; + } + } + /* not found ? */ + if (!ext_key_map[i]) + return; } switch (kbd_fct_map [scan_code]) { case AS: kbd_normal (scan_code); - break; + break; case SH: kbd_shift (scan_code); - break; + break; case CN: kbd_ctrl (scan_code); - break; + break; case NM: kbd_num (scan_code); - break; + break; case CP: kbd_caps (scan_code); - break; + break; case ST: kbd_scroll (scan_code); - break; + break; case AK: kbd_alt (scan_code); - break; + break; } return; } @@ -490,14 +490,14 @@ static void kbd_normal (unsigned char scan_code) { chr = kbd_key_map [kbd_mapping][kbd_state][scan_code]; if ((chr == 0xff) || (chr == 0x00)) - { - return; - } + { + return; + } - /* if caps lock convert upper to lower */ - if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z')) + /* if caps lock convert upper to lower */ + if (((kbd_flags & CAPS) == CAPS) && (chr >= 'a' && chr <= 'z')) { - chr -= 'a' - 'A'; + chr -= 'a' - 'A'; } kbd_input = chr; } @@ -510,8 +510,8 @@ static void kbd_shift (unsigned char scan_code) { if ((kbd_flags & BRK) == BRK) { - kbd_state = AS; - kbd_flags &= (~SHIFT); + kbd_state = AS; + kbd_flags &= (~SHIFT); } else { @@ -569,12 +569,12 @@ static void kbd_scroll (unsigned char scan_code) { if ((kbd_flags & BRK) == NORMAL) { - kbd_flags ^= STP; - kbd_led_set (); /* update keyboard LED */ - if (kbd_flags & STP) - kbd_input = 0x13; - else - kbd_input = 0x11; + kbd_flags ^= STP; + kbd_led_set (); /* update keyboard LED */ + if (kbd_flags & STP) + kbd_input = 0x13; + else + kbd_input = 0x11; } } @@ -584,13 +584,13 @@ static void kbd_alt (unsigned char scan_code) { if ((kbd_flags & BRK) == BRK) { - kbd_state = AS; - kbd_flags &= (~ALT); + kbd_state = AS; + kbd_flags &= (~ALT); } else { - kbd_state = AK; - kbd_flags &= ALT; + kbd_state = AK; + kbd_flags &= ALT; } } @@ -614,7 +614,7 @@ static int kbd_input_empty (void) /* wait for input buf empty */ while ((in8 (I8042_STATUS_REG) & 0x02) && kbdTimeout--) - udelay(1000); + udelay(1000); return kbdTimeout; } @@ -624,30 +624,30 @@ static int kbd_input_empty (void) static int kbd_reset (void) { if (kbd_input_empty() == 0) - return -1; + return -1; out8 (I8042_DATA_REG, 0xff); udelay(250000); if (kbd_input_empty() == 0) - return -1; + return -1; out8 (I8042_DATA_REG, 0x60); if (kbd_input_empty() == 0) - return -1; + return -1; out8 (I8042_DATA_REG, 0x45); if (kbd_input_empty() == 0) - return -1; + return -1; out8 (I8042_COMMAND_REG, 0xae); if (kbd_input_empty() == 0) - return -1; + return -1; return 0; } diff --git a/drivers/i82365.c b/drivers/i82365.c index 81736b915..5f44eacdd 100644 --- a/drivers/i82365.c +++ b/drivers/i82365.c @@ -36,7 +36,6 @@ #include <command.h> #include <pci.h> #include <pcmcia.h> -#include <cmd_pcmcia.h> #include <asm/io.h> #include <pcmcia/ss.h> @@ -153,7 +152,7 @@ static void i365_set_pair (socket_info_t * s, u_short reg, u_short data) Code to save and restore global state information for TI 1130 and TI 1131 controllers, and to set and report global configuration options. - + ======================================================================*/ static void ti113x_get_state (socket_info_t * s) @@ -195,7 +194,7 @@ static u_int ti113x_set_opts (socket_info_t * s) /*====================================================================== Routines to handle common CardBus options - + ======================================================================*/ /* Default settings for PCI command configuration register */ @@ -239,7 +238,7 @@ static void cb_set_opts (socket_info_t * s) Power control for Cardbus controllers: used both for 16-bit and Cardbus cards. - + ======================================================================*/ static int cb_set_power (socket_info_t * s, socket_state_t * state) @@ -286,7 +285,7 @@ static int cb_set_power (socket_info_t * s, socket_state_t * state) /*====================================================================== Generic routines to get and set controller options - + ======================================================================*/ static void get_bridge_state (socket_info_t * s) @@ -560,7 +559,7 @@ void i82365_exit (void) /*====================================================================== Debug stuff - + ======================================================================*/ #ifdef DEBUG diff --git a/drivers/inca-ip_sw.c b/drivers/inca-ip_sw.c index 3a23f4db9..07e86fc5f 100644 --- a/drivers/inca-ip_sw.c +++ b/drivers/inca-ip_sw.c @@ -45,14 +45,14 @@ #define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value; #define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) #define SW_WRITE_REG(reg, value) \ - *((volatile u32*)reg) = (u32)value;\ - DELAY;\ - *((volatile u32*)reg) = (u32)value; + *((volatile u32*)reg) = (u32)value;\ + DELAY;\ + *((volatile u32*)reg) = (u32)value; #define SW_READ_REG(reg, value) \ - value = (u32)*((volatile u32*)reg);\ - DELAY;\ - value = (u32)*((volatile u32*)reg); + value = (u32)*((volatile u32*)reg);\ + DELAY;\ + value = (u32)*((volatile u32*)reg); #define INCA_DMA_TX_POLLING_TIME 0x07 #define INCA_DMA_RX_POLLING_TIME 0x07 @@ -151,7 +151,6 @@ static void inca_init_switch_chip(void); static void inca_dma_init(void); - int inca_switch_initialize(bd_t * bis) { struct eth_device *dev; @@ -293,7 +292,7 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) /* Writing to the COMMAND REG. */ DMA_WRITE_REG(INCA_IP_DMA_DMA_RXCCR0, - INCA_IP_DMA_DMA_RXCCR0_INIT); + INCA_IP_DMA_DMA_RXCCR0_INIT); /* Initialize TxDMA. */ @@ -316,9 +315,9 @@ static int inca_switch_init(struct eth_device *dev, bd_t * bis) #endif /* enable spanning tree forwarding, enable the CPU port */ /* ST_PT: - CPS (CPU port status) 0x3 (forwarding) - LPS (LAN port status) 0x3 (forwarding) - PPS (PC port status) 0x3 (forwarding) + CPS (CPU port status) 0x3 (forwarding) + LPS (LAN port status) 0x3 (forwarding) + PPS (PC port status) 0x3 (forwarding) */ SW_WRITE_REG(INCA_IP_Switch_ST_PT,0x3f); @@ -348,7 +347,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, printf ("%s: bad packet size: %d\n", dev->name, length); goto Done; } - + for(i = 0; tx_desc->C == 0; i++) { if (i >= TOUT_LOOP) @@ -365,7 +364,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, tx_old_hold = tx_hold; tx_desc->params.word = - (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); + (INCA_DMA_TX_SOP | INCA_DMA_TX_EOP | INCA_DMA_TX_HOLD); tx_desc->C = 0; tx_desc->TxDataPtr = (u32)packet; @@ -386,7 +385,7 @@ static int inca_switch_send(struct eth_device *dev, volatile void *packet, { command = INCA_IP_DMA_DMA_TXCCR0_HR; } - + DMA_READ_REG(INCA_IP_DMA_DMA_TXCCR0, regValue); regValue |= command; #if 0 @@ -443,7 +442,7 @@ static int inca_switch_recv(struct eth_device *dev) length = rx_desc->status.field.NBT; rx_desc->status.word &= - ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); + ~(INCA_DMA_RX_EOP | INCA_DMA_RX_SOP | INCA_DMA_RX_C); #if 0 { int i; @@ -461,7 +460,7 @@ static int inca_switch_recv(struct eth_device *dev) printf("Received %d bytes\n", length); #endif NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_new]), - length - 4); + length - 4); } else { @@ -527,62 +526,62 @@ static void inca_init_switch_chip(void) SW_WRITE_REG(INCA_IP_Switch_LAN_TX_CTL, 0x00000001); #if 1 - /* init MDIO configuration: - MDS (Poll speed): 0x01 (4ms) - PHY_LAN_ADDR: 0x06 - PHY_PC_ADDR: 0x05 - UEP (Use External PHY): 0x00 (Internal PHY is used) - PS (Port Select): 0x00 (PT/UMM for LAN) - PT (PHY Test): 0x00 (no test mode) - UMM (Use MDIO Mode): 0x00 (state machine is disabled) + /* init MDIO configuration: + MDS (Poll speed): 0x01 (4ms) + PHY_LAN_ADDR: 0x06 + PHY_PC_ADDR: 0x05 + UEP (Use External PHY): 0x00 (Internal PHY is used) + PS (Port Select): 0x00 (PT/UMM for LAN) + PT (PHY Test): 0x00 (no test mode) + UMM (Use MDIO Mode): 0x00 (state machine is disabled) */ SW_WRITE_REG(INCA_IP_Switch_MDIO_CFG, 0x4c50); - /* init PHY: - SL (Auto Neg. Speed for LAN) - SP (Auto Neg. Speed for PC) - LL (Link Status for LAN) - LP (Link Status for PC) - DL (Duplex Status for LAN) - DP (Duplex Status for PC) - PL (Auto Neg. Pause Status for LAN) - PP (Auto Neg. Pause Status for PC) + /* init PHY: + SL (Auto Neg. Speed for LAN) + SP (Auto Neg. Speed for PC) + LL (Link Status for LAN) + LP (Link Status for PC) + DL (Duplex Status for LAN) + DP (Duplex Status for PC) + PL (Auto Neg. Pause Status for LAN) + PP (Auto Neg. Pause Status for PC) */ SW_WRITE_REG (INCA_IP_Switch_EPHY, 0xff); /* MDIO_ACC: - RA (Request/Ack) 0x01 (Request) - RW (Read/Write) 0x01 (Write) - PHY_ADDR 0x05 (PC) - REG_ADDR 0x00 (PHY_BCR: basic control register) - PHY_DATA 0x8000 - Reset - software reset - LB (loop back) - normal - SS (speed select) - 10 Mbit/s - ANE (auto neg. enable) - disable - PD (power down) - normal - ISO (isolate) - normal - RAN (restart auto neg.) - normal - DM (duplex mode) - half duplex - CT (collision test) - enable + RA (Request/Ack) 0x01 (Request) + RW (Read/Write) 0x01 (Write) + PHY_ADDR 0x05 (PC) + REG_ADDR 0x00 (PHY_BCR: basic control register) + PHY_DATA 0x8000 + Reset - software reset + LB (loop back) - normal + SS (speed select) - 10 Mbit/s + ANE (auto neg. enable) - disable + PD (power down) - normal + ISO (isolate) - normal + RAN (restart auto neg.) - normal + DM (duplex mode) - half duplex + CT (collision test) - enable */ SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0a08000); /* MDIO_ACC: - RA (Request/Ack) 0x01 (Request) - RW (Read/Write) 0x01 (Write) - PHY_ADDR 0x06 (LAN) - REG_ADDR 0x00 (PHY_BCR: basic control register) - PHY_DATA 0x8000 - Reset - software reset - LB (loop back) - normal - SS (speed select) - 10 Mbit/s - ANE (auto neg. enable) - disable - PD (power down) - normal - ISO (isolate) - normal - RAN (restart auto neg.) - normal - DM (duplex mode) - half duplex - CT (collision test) - enable + RA (Request/Ack) 0x01 (Request) + RW (Read/Write) 0x01 (Write) + PHY_ADDR 0x06 (LAN) + REG_ADDR 0x00 (PHY_BCR: basic control register) + PHY_DATA 0x8000 + Reset - software reset + LB (loop back) - normal + SS (speed select) - 10 Mbit/s + ANE (auto neg. enable) - disable + PD (power down) - normal + ISO (isolate) - normal + RAN (restart auto neg.) - normal + DM (duplex mode) - half duplex + CT (collision test) - enable */ SW_WRITE_REG(INCA_IP_Switch_MDIO_ACC, 0xc0c08000); #endif @@ -640,7 +639,3 @@ static void inca_dma_init(void) } #endif - - /* End of file. - */ - diff --git a/drivers/lan91c96.c b/drivers/lan91c96.c index 76b0c53ae..189ca8762 100644 --- a/drivers/lan91c96.c +++ b/drivers/lan91c96.c @@ -179,7 +179,6 @@ static int smc_close (void); static int smc_rcv (void); - /* ------------------------------------------------------------ * Internal routines * ------------------------------------------------------------ @@ -252,7 +251,6 @@ static void print_packet (byte *, int); /* #define tx_done(dev) 1 */ - /* this does a soft reset on the device */ static void smc_reset (void); @@ -668,7 +666,6 @@ static int smc_rcv () packet_length -= 4; /*4; */ - /* set odd length for bug in LAN91C111, */ /* which never sets RS_ODDFRAME */ /* TODO ? */ diff --git a/drivers/lan91c96.h b/drivers/lan91c96.h index 3ac58bce2..4eb7d7f04 100644 --- a/drivers/lan91c96.h +++ b/drivers/lan91c96.h @@ -115,8 +115,8 @@ typedef unsigned long int dword; #define SMC_insl(r,b,l) ({ int __i ; \ dword *__b2; \ - __b2 = (dword *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (dword *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inl(r); \ SMC_inl(0); \ }; \ @@ -124,8 +124,8 @@ typedef unsigned long int dword; #define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inw(r); \ SMC_inw(0); \ }; \ @@ -133,8 +133,8 @@ typedef unsigned long int dword; #define SMC_insb(r,b,l) ({ int __i ; \ byte *__b2; \ - __b2 = (byte *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (byte *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inb(r); \ SMC_inb(0); \ }; \ @@ -173,8 +173,8 @@ typedef unsigned long int dword; #else #define SMC_insw(r,b,l) ({ int __i ; \ word *__b2; \ - __b2 = (word *) b; \ - for (__i = 0; __i < l; __i++) { \ + __b2 = (word *) b; \ + for (__i = 0; __i < l; __i++) { \ *(__b2 + __i) = SMC_inw(r); \ SMC_inw(0); \ }; \ @@ -188,7 +188,7 @@ typedef unsigned long int dword; * Bank Select Field **************************************************************************** */ -#define LAN91C96_BANK_SELECT 14 // Bank Select Register +#define LAN91C96_BANK_SELECT 14 /* Bank Select Register */ #define LAN91C96_BANKSELECT (0x3UC << 0) #define BANK0 0x00 #define BANK1 0x01 @@ -210,12 +210,12 @@ typedef unsigned long int dword; * Bank 0 Register Map in I/O Space **************************************************************************** */ -#define LAN91C96_TCR 0 // Transmit Control Register -#define LAN91C96_EPH_STATUS 2 // EPH Status Register -#define LAN91C96_RCR 4 // Receive Control Register -#define LAN91C96_COUNTER 6 // Counter Register -#define LAN91C96_MIR 8 // Memory Information Register -#define LAN91C96_MCR 10 // Memory Configuration Register +#define LAN91C96_TCR 0 /* Transmit Control Register */ +#define LAN91C96_EPH_STATUS 2 /* EPH Status Register */ +#define LAN91C96_RCR 4 /* Receive Control Register */ +#define LAN91C96_COUNTER 6 /* Counter Register */ +#define LAN91C96_MIR 8 /* Memory Information Register */ +#define LAN91C96_MCR 10 /* Memory Configuration Register */ /* **************************************************************************** @@ -258,15 +258,15 @@ typedef unsigned long int dword; #define LAN91C96_EPHSR_TX_UNRN (0x1U << 15) #define LAN91C96_EPHSR_ERRORS (LAN91C96_EPHSR_SNGL_COL | \ - LAN91C96_EPHSR_MUL_COL | \ - LAN91C96_EPHSR_16COL | \ - LAN91C96_EPHSR_SQET | \ - LAN91C96_EPHSR_TX_DEFR | \ - LAN91C96_EPHSR_LATCOL | \ - LAN91C96_EPHSR_LOST_CARR | \ - LAN91C96_EPHSR_EXC_DEF | \ - LAN91C96_EPHSR_LINK_OK | \ - LAN91C96_EPHSR_TX_UNRN) + LAN91C96_EPHSR_MUL_COL | \ + LAN91C96_EPHSR_16COL | \ + LAN91C96_EPHSR_SQET | \ + LAN91C96_EPHSR_TX_DEFR | \ + LAN91C96_EPHSR_LATCOL | \ + LAN91C96_EPHSR_LOST_CARR | \ + LAN91C96_EPHSR_EXC_DEF | \ + LAN91C96_EPHSR_LINK_OK | \ + LAN91C96_EPHSR_TX_UNRN) /* **************************************************************************** @@ -296,7 +296,7 @@ typedef unsigned long int dword; * Memory Information Register - Bank 0 - OFfset 8 **************************************************************************** */ -#define LAN91C96_MIR_SIZE (0x18 << 0) // 6144 bytes +#define LAN91C96_MIR_SIZE (0x18 << 0) /* 6144 bytes */ /* **************************************************************************** @@ -314,16 +314,16 @@ typedef unsigned long int dword; * Bank 1 Register Map in I/O Space **************************************************************************** */ -#define LAN91C96_CONFIG 0 // Configuration Register -#define LAN91C96_BASE 2 // Base Address Register -#define LAN91C96_IA0 4 // Individual Address Register - 0 -#define LAN91C96_IA1 5 // Individual Address Register - 1 -#define LAN91C96_IA2 6 // Individual Address Register - 2 -#define LAN91C96_IA3 7 // Individual Address Register - 3 -#define LAN91C96_IA4 8 // Individual Address Register - 4 -#define LAN91C96_IA5 9 // Individual Address Register - 5 -#define LAN91C96_GEN_PURPOSE 10 // General Address Registers -#define LAN91C96_CONTROL 12 // Control Register +#define LAN91C96_CONFIG 0 /* Configuration Register */ +#define LAN91C96_BASE 2 /* Base Address Register */ +#define LAN91C96_IA0 4 /* Individual Address Register - 0 */ +#define LAN91C96_IA1 5 /* Individual Address Register - 1 */ +#define LAN91C96_IA2 6 /* Individual Address Register - 2 */ +#define LAN91C96_IA3 7 /* Individual Address Register - 3 */ +#define LAN91C96_IA4 8 /* Individual Address Register - 4 */ +#define LAN91C96_IA5 9 /* Individual Address Register - 5 */ +#define LAN91C96_GEN_PURPOSE 10 /* General Address Registers */ +#define LAN91C96_CONTROL 12 /* Control Register */ /* **************************************************************************** @@ -371,17 +371,17 @@ typedef unsigned long int dword; * Bank 2 Register Map in I/O Space **************************************************************************** */ -#define LAN91C96_MMU 0 // MMU Command Register -#define LAN91C96_AUTO_TX_START 1 // Auto Tx Start Register -#define LAN91C96_PNR 2 // Packet Number Register -#define LAN91C96_ARR 3 // Allocation Result Register -#define LAN91C96_FIFO 4 // FIFO Ports Register -#define LAN91C96_POINTER 6 // Pointer Register -#define LAN91C96_DATA_HIGH 8 // Data High Register -#define LAN91C96_DATA_LOW 10 // Data Low Register -#define LAN91C96_INT_STATS 12 // Interrupt Status Register - RO -#define LAN91C96_INT_ACK 12 // Interrupt Acknowledge Register -WO -#define LAN91C96_INT_MASK 13 // Interrupt Mask Register +#define LAN91C96_MMU 0 /* MMU Command Register */ +#define LAN91C96_AUTO_TX_START 1 /* Auto Tx Start Register */ +#define LAN91C96_PNR 2 /* Packet Number Register */ +#define LAN91C96_ARR 3 /* Allocation Result Register */ +#define LAN91C96_FIFO 4 /* FIFO Ports Register */ +#define LAN91C96_POINTER 6 /* Pointer Register */ +#define LAN91C96_DATA_HIGH 8 /* Data High Register */ +#define LAN91C96_DATA_LOW 10 /* Data Low Register */ +#define LAN91C96_INT_STATS 12 /* Interrupt Status Register - RO */ +#define LAN91C96_INT_ACK 12 /* Interrupt Acknowledge Register -WO */ +#define LAN91C96_INT_MASK 13 /* Interrupt Mask Register */ /* **************************************************************************** @@ -392,14 +392,14 @@ typedef unsigned long int dword; #define LAN91C96_MMUCR_N1 (0x1U << 1) #define LAN91C96_MMUCR_N2 (0x1U << 2) #define LAN91C96_MMUCR_COMMAND (0xFU << 4) -#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) // WXYZ = 0010 -#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) // WXYZ = 0100 -#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) // WXYZ = 0110 -#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) // WXYZ = 0111 -#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) // WXYZ = 1000 -#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) // WXYZ = 1010 -#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) // WXYZ = 1100 -#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) // WXYZ = 1110 +#define LAN91C96_MMUCR_ALLOC_TX (0x2U << 4) /* WXYZ = 0010 */ +#define LAN91C96_MMUCR_RESET_MMU (0x4U << 4) /* WXYZ = 0100 */ +#define LAN91C96_MMUCR_REMOVE_RX (0x6U << 4) /* WXYZ = 0110 */ +#define LAN91C96_MMUCR_REMOVE_TX (0x7U << 4) /* WXYZ = 0111 */ +#define LAN91C96_MMUCR_RELEASE_RX (0x8U << 4) /* WXYZ = 1000 */ +#define LAN91C96_MMUCR_RELEASE_TX (0xAU << 4) /* WXYZ = 1010 */ +#define LAN91C96_MMUCR_ENQUEUE (0xCU << 4) /* WXYZ = 1100 */ +#define LAN91C96_MMUCR_RESET_TX (0xEU << 4) /* WXYZ = 1110 */ /* **************************************************************************** @@ -447,16 +447,16 @@ typedef unsigned long int dword; #define LAN91C96_PTR_RCV (0x1U << 15) #define LAN91C96_PTR_RX_FRAME (LAN91C96_PTR_RCV | \ - LAN91C96_PTR_AUTO_INCR | \ - LAN91C96_PTR_READ) + LAN91C96_PTR_AUTO_INCR | \ + LAN91C96_PTR_READ) /* **************************************************************************** * Data Register - Bank 2 - Offset 8 **************************************************************************** */ -#define LAN91C96_CONTROL_CRC (0x1U << 4) // CRC bit -#define LAN91C96_CONTROL_ODD (0x1U << 5) // ODD bit +#define LAN91C96_CONTROL_CRC (0x1U << 4) /* CRC bit */ +#define LAN91C96_CONTROL_ODD (0x1U << 5) /* ODD bit */ /* **************************************************************************** @@ -533,8 +533,8 @@ typedef unsigned long int dword; * PCMCIA Configuration Registers **************************************************************************** */ -#define LAN91C96_ECOR 0x8000 // Ethernet Configuration Register -#define LAN91C96_ECSR 0x8002 // Ethernet Configuration and Status +#define LAN91C96_ECOR 0x8000 /* Ethernet Configuration Register */ +#define LAN91C96_ECSR 0x8002 /* Ethernet Configuration and Status */ /* **************************************************************************** @@ -587,11 +587,10 @@ typedef unsigned long int dword; #define LAN91C96_HIGH_SIGNATURE (0x33U << 8) #define LAN91C96_SIGNATURE (LAN91C96_HIGH_SIGNATURE | LAN91C96_LOW_SIGNATURE) -#define LAN91C96_MAX_PAGES 6 // Maximum number of 256 pages. +#define LAN91C96_MAX_PAGES 6 /* Maximum number of 256 pages. */ #define ETHERNET_MAX_LENGTH 1514 - /*------------------------------------------------------------------------- * I define some macros to make it easier to do somewhat common * or slightly complicated, repeated tasks. diff --git a/drivers/mw_eeprom.c b/drivers/mw_eeprom.c index 30a51fa05..2a1f48984 100644 --- a/drivers/mw_eeprom.c +++ b/drivers/mw_eeprom.c @@ -33,10 +33,10 @@ static int mw_eeprom_size(int dev) { int x; u16 res; - + mw_eeprom_select(dev); ssi_tx_byte(EEP_OPC_READ); - + res = ssi_txrx_byte(0) << 8; res |= ssi_rx_byte(); for (x = 0; x < 16; x++) { @@ -46,7 +46,7 @@ static int mw_eeprom_size(int dev) res <<= 1; } ssi_chip_select(0); - + return x; } @@ -57,18 +57,18 @@ int mw_eeprom_erase_enable(int dev) ssi_tx_byte(0); udelay(1); ssi_chip_select(0); - + return 0; } int mw_eeprom_erase_disable(int dev) -{ +{ mw_eeprom_select(dev); ssi_tx_byte(EEP_OPC_ERASE_DIS); ssi_tx_byte(0); udelay(1); ssi_chip_select(0); - + return 0; } @@ -78,13 +78,13 @@ u32 mw_eeprom_read_word(int dev, int addr) u16 rcv; u16 res; int bits; - + mw_eeprom_select(dev); ssi_tx_byte((EEP_OPC_READ << 5) | ((addr >> (addrlen - 5)) & 0x1f)); rcv = ssi_txrx_byte(addr << (13 - addrlen)); res = rcv << (16 - addrlen); bits = 4 + addrlen; - + while (bits>0) { rcv = ssi_rx_byte(); if (bits > 7) { @@ -94,9 +94,9 @@ u32 mw_eeprom_read_word(int dev, int addr) } bits -= 8; } - + ssi_chip_select(0); - + return res; } @@ -104,10 +104,10 @@ int mw_eeprom_write_word(int dev, int addr, u16 data) { u8 byte1=0; u8 byte2=0; - + mw_eeprom_erase_enable(dev); mw_eeprom_select(dev); - + switch (addrlen) { case 6: byte1 = EEP_OPC_WRITE >> 2; @@ -136,14 +136,14 @@ int mw_eeprom_write_word(int dev, int addr, u16 data) default: printf("Unsupported number of address bits: %d\n", addrlen); return -1; - + } - + ssi_tx_byte(byte1); ssi_tx_byte(byte2); - ssi_tx_byte(data >> 8); + ssi_tx_byte(data >> 8); ssi_tx_byte(data & 0xff); - ssi_chip_select(0); + ssi_chip_select(0); udelay(10000); /* Worst case */ mw_eeprom_erase_disable(dev); @@ -154,20 +154,20 @@ int mw_eeprom_write_word(int dev, int addr, u16 data) int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) { int done; - + done = 0; if (addr & 1) { u16 temp = mw_eeprom_read_word(dev, addr >> 1); temp &= 0xff00; temp |= buffer[0]; - + mw_eeprom_write_word(dev, addr >> 1, temp); len--; addr++; buffer++; done++; } - + while (len <= 2) { mw_eeprom_write_word(dev, addr >> 1, *(u16*)buffer); len-=2; @@ -180,7 +180,7 @@ int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) u16 temp = mw_eeprom_read_word(dev, addr >> 1); temp &= 0x00ff; temp |= buffer[0] << 8; - + mw_eeprom_write_word(dev, addr >> 1, temp); len--; addr++; @@ -192,22 +192,21 @@ int mw_eeprom_write(int dev, int addr, u8 *buffer, int len) } - int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) { int done; - + done = 0; if (addr & 1) { u16 temp = mw_eeprom_read_word(dev, addr >> 1); buffer[0]= temp & 0xff; - + len--; addr++; buffer++; done++; } - + while (len <= 2) { *(u16*)buffer = mw_eeprom_read_word(dev, addr >> 1); len-=2; @@ -219,7 +218,7 @@ int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) if (len) { u16 temp = mw_eeprom_read_word(dev, addr >> 1); buffer[0] = temp >> 8; - + len--; addr++; buffer++; @@ -232,7 +231,7 @@ int mw_eeprom_read(int dev, int addr, u8 *buffer, int len) int mw_eeprom_probe(int dev) { addrlen = mw_eeprom_size(dev); - + if (addrlen < 6 || addrlen > 10) { return -1; } diff --git a/drivers/nicext.h b/drivers/nicext.h index 0879dc227..4074972c0 100644 --- a/drivers/nicext.h +++ b/drivers/nicext.h @@ -49,35 +49,35 @@ struct nice_req union { #ifdef __KERNEL__ - /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ - struct - { - void (*nrqus1_rx)( struct sk_buff*, void* ); - void* nrqus1_ctx; - } nrqu_nrqus1; + /* cmd = NICE_CMD_SET_RX or NICE_CMD_GET_RX */ + struct + { + void (*nrqus1_rx)( struct sk_buff*, void* ); + void* nrqus1_ctx; + } nrqu_nrqus1; - /* cmd = NICE_CMD_QUERY_SUPPORT */ - struct - { - __u32 nrqus2_magic; - __u32 nrqus2_support_rx:1; - __u32 nrqus2_support_vlan:1; - __u32 nrqus2_support_get_speed:1; - } nrqu_nrqus2; + /* cmd = NICE_CMD_QUERY_SUPPORT */ + struct + { + __u32 nrqus2_magic; + __u32 nrqus2_support_rx:1; + __u32 nrqus2_support_vlan:1; + __u32 nrqus2_support_get_speed:1; + } nrqu_nrqus2; #endif - /* cmd = NICE_CMD_GET_SPEED */ - struct - { - unsigned int nrqus3_speed; /* 0 if link is down, */ - /* otherwise speed in Mbps */ - } nrqu_nrqus3; + /* cmd = NICE_CMD_GET_SPEED */ + struct + { + unsigned int nrqus3_speed; /* 0 if link is down, */ + /* otherwise speed in Mbps */ + } nrqu_nrqus3; - /* cmd = NICE_CMD_BLINK_LED */ - struct - { - unsigned int nrqus4_blink_time; /* blink duration in seconds */ - } nrqu_nrqus4; + /* cmd = NICE_CMD_BLINK_LED */ + struct + { + unsigned int nrqus4_blink_time; /* blink duration in seconds */ + } nrqu_nrqus4; } nrq_nrqu; }; @@ -107,4 +107,3 @@ struct nice_req #define NICE_CMD_BLINK_LED 0x00000005 #endif /* _nicext_h_ */ - diff --git a/drivers/pci.c b/drivers/pci.c index 289db8fcf..b9a1b9a87 100644 --- a/drivers/pci.c +++ b/drivers/pci.c @@ -33,7 +33,6 @@ #ifdef CONFIG_PCI #include <command.h> -#include <cmd_boot.h> #include <asm/processor.h> #include <asm/io.h> #include <pci.h> diff --git a/drivers/pci_auto.c b/drivers/pci_auto.c index 38b59ecdb..8fe72a384 100644 --- a/drivers/pci_auto.c +++ b/drivers/pci_auto.c @@ -257,7 +257,6 @@ void pciauto_config_init(struct pci_controller *hose) } - if (hose->pci_mem) { pciauto_region_init(hose->pci_mem); @@ -296,7 +295,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev) DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev)); pciauto_prescan_setup_bridge(hose, dev, sub_bus); - + pci_hose_scan_bus(hose, hose->current_busno); pciauto_postscan_setup_bridge(hose, dev, sub_bus); diff --git a/drivers/plb2800_eth.c b/drivers/plb2800_eth.c index 7c7f9f8bf..4c683d7a5 100644 --- a/drivers/plb2800_eth.c +++ b/drivers/plb2800_eth.c @@ -57,7 +57,7 @@ #define MBOX_STAT_MB 0x00000001 #define EN_MA_LEARN 0x02000000 #define EN_DA_LKUP 0x01000000 -#define MA_DEST_SHF 11 +#define MA_DEST_SHF 11 #define DA_DEST_SHF 11 #define DA_STATE_SHF 19 #define TSTAMP_MS 0x00000000 @@ -121,23 +121,23 @@ int plb2800_eth_initialize(bd_t * bis) eth_register(dev); - /* bug fix */ - *(ulong *)0xb800e800 = 0x838; + /* bug fix */ + *(ulong *)0xb800e800 = 0x838; /* Set MBOX ownership */ temp = CMAC_CRIT << MBOX_STAT_ID_SHF; MBOX_REG(0)->stat = temp; MBOX_REG(1)->stat = temp; - temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; + temp = CMAC_NON_CRIT << MBOX_STAT_ID_SHF; MBOX_REG(2)->stat = temp; MBOX_REG(3)->stat = temp; - + plb2800_set_mac_addr(dev, plb2800_get_mac_addr()); /* Disable all Mbox interrupt */ temp = MIPS_H_MASK; - temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; + temp &= ~ (SW_H_MBOX1_MASK | SW_H_MBOX2_MASK | SW_H_MBOX3_MASK | SW_H_MBOX4_MASK) ; MIPS_H_MASK = temp; #ifdef DEBUG @@ -222,7 +222,7 @@ static int plb2800_eth_send(struct eth_device *dev, volatile void *packet, CMAC_CRX_CTRL = temp; mb->cmd = MBOX_STAT_CP; - + #ifdef DEBUG printf("2 mb->stat = 0x%x\n", mb->stat); #endif @@ -257,7 +257,7 @@ static int plb2800_eth_recv(struct eth_device *dev) { break; } - + length = ((*(hdr + 6) & 0x3f) << 8) + *(hdr + 7); memcpy((void *)NetRxPackets[rx_new], hdr + 12, length); @@ -323,13 +323,13 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) { return; } - + /* send one packet through CPU port * in order to learn system MAC address - */ + */ /* Set DA_LOOKUP register */ - temp = EN_MA_LEARN | (0 << DA_STATE_SHF) | (63 << DA_DEST_SHF); + temp = EN_MA_LEARN | (0 << DA_STATE_SHF) | (63 << DA_DEST_SHF); DA_LOOKUP = temp; /* Set MA_LEARN register */ @@ -339,7 +339,7 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) /* set destination address */ for (ix=0;ix<6;ix++) packet[ix] = 0xff; - + /* set source address = system MAC address */ for (ix=0;ix<6;ix++) packet[6+ix] = addr[ix]; @@ -351,7 +351,7 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) /* set data field */ for(ix=14;ix<60;ix++) packet[ix] = 0x00; - + #ifdef DEBUG for (ix=0;ix<6;ix++) printf("mac_addr[%d]=%02X\n", ix, (unsigned char)packet[6+ix]); @@ -364,10 +364,10 @@ static void plb2800_set_mac_addr(struct eth_device *dev, unsigned char * addr) for(ix=0;ix<65535;ix++) temp = ~temp; - /* Set CMAC_CTX_CTRL register */ + /* Set CMAC_CTX_CTRL register */ temp = TSTAMP_MS; /* no autocast */ CMAC_CTX_CTRL = temp; - + /* Set DA_LOOKUP register */ temp = EN_DA_LKUP; DA_LOOKUP = temp; @@ -380,10 +380,10 @@ static unsigned char * plb2800_get_mac_addr(void) static unsigned char addr[6]; char *tmp, *end; int i; - + tmp = getenv ("ethaddr"); if (NULL == tmp) return NULL; - + for (i=0; i<6; i++) { addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0; if (tmp) diff --git a/drivers/s3c24x0_i2c.c b/drivers/s3c24x0_i2c.c index eeb6cf6d1..76b9d954f 100644 --- a/drivers/s3c24x0_i2c.c +++ b/drivers/s3c24x0_i2c.c @@ -89,7 +89,7 @@ static int WaitForXfer(void) i = I2C_TIMEOUT * 1000; status = i2c->IICCON; while ((i > 0) && !(status & I2CCON_IRPND)) { - udelay(1000); + udelay(1000); status = i2c->IICCON; i--; } @@ -181,10 +181,10 @@ void i2c_init (int speed, int slaveadd) */ static int i2c_transfer(unsigned char cmd_type, - unsigned char chip, - unsigned char addr[], - unsigned char addr_len, - unsigned char data[], + unsigned char chip, + unsigned char addr[], + unsigned char addr_len, + unsigned char data[], unsigned short data_len) { S3C24X0_I2C * const i2c = S3C24X0_GetBase_I2C(); @@ -196,7 +196,7 @@ int i2c_transfer(unsigned char cmd_type, return I2C_NOK; } - //CheckDelay(); + /*CheckDelay(); */ /* Check I2C bus idle */ i = I2C_TIMEOUT * 1000; @@ -210,7 +210,7 @@ int i2c_transfer(unsigned char cmd_type, if (status & I2CSTAT_BSY) { result = I2C_NOK_TOUT; - return(result); + return(result); } i2c->IICCON |= 0x80; @@ -251,7 +251,7 @@ int i2c_transfer(unsigned char cmd_type, } if (result == I2C_OK) - result = WaitForXfer(); + result = WaitForXfer(); /* send STOP */ i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; @@ -306,7 +306,7 @@ int i2c_transfer(unsigned char cmd_type, /* disable ACK for final READ */ if (i == data_len - 1) i2c->IICCON &= ~0x80; - ReadWriteByte(); + ReadWriteByte(); result = WaitForXfer(); data[i] = i2c->IICDS; i++; @@ -323,7 +323,7 @@ int i2c_transfer(unsigned char cmd_type, default: printf( "i2c_transfer: bad call\n" ); - result = I2C_NOK; + result = I2C_NOK; break; } @@ -356,9 +356,9 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) if ( alen > 0 ) { xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; } @@ -378,8 +378,8 @@ int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); #endif if( (ret = i2c_transfer(I2C_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) { - printf( "I2c read: failed %d\n", ret); - return 1; + printf( "I2c read: failed %d\n", ret); + return 1; } return 0; } @@ -394,10 +394,10 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) } if ( alen > 0 ) { - xaddr[0] = (addr >> 24) & 0xFF; - xaddr[1] = (addr >> 16) & 0xFF; - xaddr[2] = (addr >> 8) & 0xFF; - xaddr[3] = addr & 0xFF; + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; } #ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW @@ -413,7 +413,7 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) * hidden in the chip address. */ if( alen > 0 ) - chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); + chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW); #endif return (i2c_transfer(I2C_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0); } diff --git a/drivers/sed13806.c b/drivers/sed13806.c index 55fceef94..114a2470b 100644 --- a/drivers/sed13806.c +++ b/drivers/sed13806.c @@ -43,7 +43,7 @@ GraphicDevice sed13806; /*----------------------------------------------------------------------------- - * EpsonSetRegs -- + * EpsonSetRegs -- *----------------------------------------------------------------------------- */ static void EpsonSetRegs (void) @@ -51,13 +51,13 @@ static void EpsonSetRegs (void) /* the content of the chipset register depends on the board (clocks, ...)*/ const S1D_REGS *preg = board_get_regs (); while (preg -> Index) { - writeByte (preg -> Index, preg -> Value); - preg ++; + writeByte (preg -> Index, preg -> Value); + preg ++; } } - + /*----------------------------------------------------------------------------- - * video_hw_init -- + * video_hw_init -- *----------------------------------------------------------------------------- */ void *video_hw_init (void) @@ -70,7 +70,7 @@ void *video_hw_init (void) Retreive base address of the chipset (see board/RPXClassic/eccx.c) */ if ((sed13806.isaBase = board_video_init ()) == 0) { - return (NULL); + return (NULL); } sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; @@ -80,7 +80,7 @@ void *video_hw_init (void) #if defined(CONFIG_VIDEO_SED13806_8BPP) sed13806.gdfIndex = GDF__8BIT_INDEX; sed13806.gdfBytesPP = 1; - + #elif defined(CONFIG_VIDEO_SED13806_16BPP) sed13806.gdfIndex = GDF_16BIT_565RGB; sed13806.gdfBytesPP = 2; @@ -101,9 +101,9 @@ void *video_hw_init (void) i = sed13806.memSize/4; vm = (unsigned int *)sed13806.frameAdrs; while(i--) - *vm++ = 0; - - + *vm++ = 0; + + return (&sed13806); } /*----------------------------------------------------------------------------- @@ -119,7 +119,7 @@ static void Epson_wait_idle (void) } /*----------------------------------------------------------------------------- - * video_hw_bitblt -- + * video_hw_bitblt -- *----------------------------------------------------------------------------- */ void video_hw_bitblt ( @@ -140,29 +140,29 @@ void video_hw_bitblt ( dstAddr = (dst_y * stride) + (dst_x * bpp); Epson_wait_idle (); - - writeByte(BLT_ROP,0x0C); // source - writeByte(BLT_OP,0x02);// move blit in positive direction with ROP + + writeByte(BLT_ROP,0x0C); /* source */ + writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */ writeWord(BLT_MEM_OFF0, stride / 2); if (pGD -> gdfIndex == GDF__8BIT_INDEX) { - writeByte(BLT_CTRL1,0x00); + writeByte(BLT_CTRL1,0x00); } else { - writeByte(BLT_CTRL1,0x01); + writeByte(BLT_CTRL1,0x01); } writeWord(BLT_WIDTH0,(dim_x - 1)); writeWord(BLT_HEIGHT0,(dim_y - 1)); - + /* set up blit registers */ writeByte(BLT_SRC_ADDR0,srcAddr); - writeByte(BLT_SRC_ADDR1,srcAddr>>8); - writeByte(BLT_SRC_ADDR2,srcAddr>>16); - + writeByte(BLT_SRC_ADDR1,srcAddr>>8); + writeByte(BLT_SRC_ADDR2,srcAddr>>16); + writeByte(BLT_DST_ADDR0,dstAddr); - writeByte(BLT_DST_ADDR1,dstAddr>>8); - writeByte(BLT_DST_ADDR2,dstAddr>>16); - + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); + /* Engage the blt engine */ /* rectangular region for src and dst */ writeByte(BLT_CTRL0,0x80); @@ -171,7 +171,7 @@ void video_hw_bitblt ( Epson_wait_idle (); } /*----------------------------------------------------------------------------- - * video_hw_rectfill -- + * video_hw_rectfill -- *----------------------------------------------------------------------------- */ void video_hw_rectfill ( @@ -193,8 +193,8 @@ void video_hw_rectfill ( /* set up blit registers */ writeByte(BLT_DST_ADDR0,dstAddr); - writeByte(BLT_DST_ADDR1,dstAddr>>8); - writeByte(BLT_DST_ADDR2,dstAddr>>16); + writeByte(BLT_DST_ADDR1,dstAddr>>8); + writeByte(BLT_DST_ADDR2,dstAddr>>16); writeWord(BLT_WIDTH0,(dim_x - 1)); writeWord(BLT_HEIGHT0,(dim_y - 1)); @@ -204,12 +204,12 @@ void video_hw_rectfill ( writeWord(BLT_MEM_OFF0,stride / 2); if (pGD -> gdfIndex == GDF__8BIT_INDEX) { - writeByte(BLT_CTRL1,0x00); + writeByte(BLT_CTRL1,0x00); } else { - writeByte(BLT_CTRL1,0x01); + writeByte(BLT_CTRL1,0x01); } - + /* Engage the blt engine */ /* rectangular region for src and dst */ writeByte(BLT_CTRL0,0x80); @@ -219,7 +219,7 @@ void video_hw_rectfill ( } /*----------------------------------------------------------------------------- - * video_set_lut -- + * video_set_lut -- *----------------------------------------------------------------------------- */ void video_set_lut ( @@ -236,7 +236,7 @@ void video_set_lut ( } #ifdef CONFIG_VIDEO_HW_CURSOR /*----------------------------------------------------------------------------- - * video_set_hw_cursor -- + * video_set_hw_cursor -- *----------------------------------------------------------------------------- */ void video_set_hw_cursor (int x, int y) @@ -248,7 +248,7 @@ void video_set_hw_cursor (int x, int y) } /*----------------------------------------------------------------------------- - * video_init_hw_cursor -- + * video_init_hw_cursor -- *----------------------------------------------------------------------------- */ void video_init_hw_cursor (int font_width, int font_height) @@ -256,47 +256,47 @@ void video_init_hw_cursor (int font_width, int font_height) volatile unsigned char *ptr; unsigned char pattern; int i; - + /* Init cursor content Cursor size is 64x64 pixels Start of the cursor memory depends on panel type (dual panel ...) */ if ((i = readByte (LCD_CURSOR_START)) == 0) { - ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); } else { - ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); + ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); } /* Fill the first line and the first empty line after cursor */ for (i = 0, pattern = 0; i < 64; i++) { - if (i < font_width) { - /* Invert background */ - pattern |= 0x3; - - } - else { - /* Background */ - pattern |= 0x2; - } - if ((i & 3) == 3) { - *ptr = pattern; - *(ptr + font_height * 16) = 0xaa; - ptr ++; - pattern = 0; - } - pattern <<= 2; + if (i < font_width) { + /* Invert background */ + pattern |= 0x3; + + } + else { + /* Background */ + pattern |= 0x2; + } + if ((i & 3) == 3) { + *ptr = pattern; + *(ptr + font_height * 16) = 0xaa; + ptr ++; + pattern = 0; + } + pattern <<= 2; } /* Duplicate this line */ for (i = 1; i < font_height; i++) { - memcpy ((void *)ptr, (void *)(ptr - 16), 16); - ptr += 16; + memcpy ((void *)ptr, (void *)(ptr - 16), 16); + ptr += 16; } - + for (; i < 64; i++) { - memcpy ((void *)(ptr + 16), (void *)ptr, 16); - ptr += 16; + memcpy ((void *)(ptr + 16), (void *)ptr, 16); + ptr += 16; } /* Select cursor mode */ diff --git a/drivers/smc91111.c b/drivers/smc91111.c index f29a8a44f..9bee02517 100644 --- a/drivers/smc91111.c +++ b/drivers/smc91111.c @@ -52,7 +52,7 @@ . o skeleton.c by Donald Becker ( becker@cesdis.gsfc.nasa.gov ) . . History: - . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. + . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks. . 10/17/01 Marco Hasewinkel Modify for DNP/1110 . 07/25/01 Woojung Huh Modify for ADS Bitsy . 04/25/01 Daris A Nevil Initial public release through SMSC @@ -153,9 +153,6 @@ extern int eth_rx(void); extern int eth_send(volatile void *packet, int length); - - - /* . This is called by register_netdev(). It is responsible for . checking the portlist for the SMC9000 series chipset. If it finds @@ -201,7 +198,7 @@ static void smc_phy_configure(void); static int smc_rcv(void); /* See if a MAC address is defined in the current environment. If so use it. If not - . print a warning and set the environment and other globals with the default. + . print a warning and set the environment and other globals with the default. . If an EEPROM is present it really should be consulted. */ int smc_get_ethaddr(bd_t *bd); @@ -238,18 +235,18 @@ void smc_set_mac_addr(const char *addr) { #if 0 void smc_get_macaddr( byte *addr ) { /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ - unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); + unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); int i; - for (i=0; i<6; i++) { - addr[0] = *(dnp1110_mac+0); - addr[1] = *(dnp1110_mac+1); - addr[2] = *(dnp1110_mac+2); - addr[3] = *(dnp1110_mac+3); - addr[4] = *(dnp1110_mac+4); - addr[5] = *(dnp1110_mac+5); - } + for (i=0; i<6; i++) { + addr[0] = *(dnp1110_mac+0); + addr[1] = *(dnp1110_mac+1); + addr[2] = *(dnp1110_mac+2); + addr[3] = *(dnp1110_mac+3); + addr[4] = *(dnp1110_mac+4); + addr[5] = *(dnp1110_mac+5); + } } #endif /* 0 */ @@ -258,16 +255,16 @@ void smc_get_macaddr( byte *addr ) { ***********************************************/ void dump_memory_info(void) { - word mem_info; - word old_bank; + word mem_info; + word old_bank; - old_bank = SMC_inw(BANK_SELECT)&0xF; + old_bank = SMC_inw(BANK_SELECT)&0xF; - SMC_SELECT_BANK(0); - mem_info = SMC_inw( MIR_REG ); - PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); + SMC_SELECT_BANK(0); + mem_info = SMC_inw( MIR_REG ); + PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); - SMC_SELECT_BANK(old_bank); + SMC_SELECT_BANK(old_bank); } /* . A rather simple routine to print out a packet for debugging purposes. @@ -279,7 +276,6 @@ static void print_packet( byte *, int ); #define tx_done(dev) 1 - /* this does a soft reset on the device */ static void smc_reset( void ); @@ -308,9 +304,9 @@ static int poll4int( byte mask, int timeout ) { SMC_SELECT_BANK(2); while((SMC_inw(SMC91111_INT_REG) & mask) == 0) { - if (get_timer(0) >= tmo) { + if (get_timer(0) >= tmo) { is_timeout = 1; - break; + break; } } @@ -329,7 +325,7 @@ static inline void smc_wait_mmu_release_complete(void) int count = 0; /* assume bank 2 selected */ while ( SMC_inw(MMU_CMD_REG) & MC_BUSY ) { - udelay(1); // Wait until not busy + udelay(1); /* Wait until not busy */ if( ++count > 200) break; } } @@ -398,7 +394,7 @@ static void smc_reset( void ) /* Note: It doesn't seem that waiting for the MMU busy is needed here, but this is a place where future chipsets _COULD_ break. Be wary - of issuing another MMU command right after this */ + of issuing another MMU command right after this */ /* Disable all interrupts */ SMC_outb( 0, IM_REG ); @@ -526,11 +522,11 @@ again: if ( status & IM_ALLOC_INT ) { /* acknowledge the interrupt */ SMC_outb( IM_ALLOC_INT, SMC91111_INT_REG ); - break; + break; } - } while ( -- time_out ); + } while ( -- time_out ); - if ( !time_out ) { + if ( !time_out ) { PRINTK2("%s: memory allocation, try %d failed ...\n", SMC_DEV_NAME, try); if (try < SMC_ALLOC_MAX_TRY) @@ -564,7 +560,7 @@ again: /* point to the beginning of the packet */ SMC_outw( PTR_AUTOINC , PTR_REG ); - PRINTK3("%s: Trying to xmit packet of length %x\n", + PRINTK3("%s: Trying to xmit packet of length %x\n", SMC_DEV_NAME, length); #if SMC_DEBUG > 2 @@ -573,7 +569,7 @@ again: #endif /* send the packet length ( +6 for status, length and ctl byte ) - and the status word ( set to zeros ) */ + and the status word ( set to zeros ) */ #ifdef USE_32_BIT SMC_outl( (length +6 ) << 16 , SMC91111_DATA_REG ); #else @@ -585,8 +581,8 @@ again: /* send the actual data . I _think_ it's faster to send the longs first, and then . mop up by sending the last word. It depends heavily - . on alignment, at least on the 486. Maybe it would be - . a good idea to check which is optimal? But that could take + . on alignment, at least on the 486. Maybe it would be + . a good idea to check which is optimal? But that could take . almost as much time as is saved? */ #ifdef USE_32_BIT @@ -614,15 +610,15 @@ again: SMC_DEV_NAME); /* release packet */ - SMC_outw(MC_FREEPKT, MMU_CMD_REG); + SMC_outw(MC_FREEPKT, MMU_CMD_REG); - /* wait for MMU getting ready (low) */ - while (SMC_inw(MMU_CMD_REG) & MC_BUSY) - { - udelay(10); - } + /* wait for MMU getting ready (low) */ + while (SMC_inw(MMU_CMD_REG) & MC_BUSY) + { + udelay(10); + } - PRINTK2("MMU ready\n"); + PRINTK2("MMU ready\n"); return 0; @@ -632,15 +628,15 @@ again: PRINTK2("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); /* release packet */ - SMC_outw(MC_FREEPKT, MMU_CMD_REG); + SMC_outw(MC_FREEPKT, MMU_CMD_REG); - /* wait for MMU getting ready (low) */ - while (SMC_inw(MMU_CMD_REG) & MC_BUSY) - { - udelay(10); - } + /* wait for MMU getting ready (low) */ + while (SMC_inw(MMU_CMD_REG) & MC_BUSY) + { + udelay(10); + } - PRINTK2("MMU ready\n"); + PRINTK2("MMU ready\n"); } @@ -690,11 +686,11 @@ static int smc_open(bd_t *bd) /* SMC_SELECT_BANK(0); */ /* SMC_outw(0, RPC_REG); */ SMC_SELECT_BANK(1); - + err = smc_get_ethaddr(bd); /* set smc_mac_addr, and sync it with u-boot globals */ - if(err < 0){ - memset(bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set*/ - return(-1); /* upper code ignores this, but NOT bi_enetaddr */ + if(err < 0){ + memset(bd->bi_enetaddr, 0, 6); /* hack to make error stick! upper code will abort if not set*/ + return(-1); /* upper code ignores this, but NOT bi_enetaddr */ } #ifdef USE_32_BIT @@ -783,7 +779,6 @@ static int smc_rcv() packet_length -= 4; /*4; */ - /* set odd length for bug in LAN91C111, */ /* which never sets RS_ODDFRAME */ /* TODO ? */ @@ -843,7 +838,6 @@ static int smc_rcv() } - /*---------------------------------------------------- . smc_close . @@ -1203,7 +1197,6 @@ static void smc_write_phy_register(byte phyreg, word phydata) #endif /* !CONFIG_SMC91111_EXT_PHY */ - /*------------------------------------------------------------ . Waits the specified number of milliseconds - kernel friendly .-------------------------------------------------------------*/ @@ -1215,7 +1208,6 @@ static void smc_wait_ms(unsigned int ms) #endif /* !CONFIG_SMC91111_EXT_PHY */ - /*------------------------------------------------------------ . Configures the specified PHY using Autonegotiation. Calls . smc_phy_fixed() if the user has requested a certain config. @@ -1233,7 +1225,6 @@ static void smc_phy_configure() PRINTK3("%s:smc_program_phy()\n", SMC_DEV_NAME); - /* Get the detected phy address */ phyaddr = SMC_PHY_ADDR; @@ -1358,36 +1349,36 @@ static void smc_phy_configure() static void print_packet( byte * buf, int length ) { #if 0 - int i; - int remainder; - int lines; + int i; + int remainder; + int lines; - printf("Packet of length %d \n", length ); + printf("Packet of length %d \n", length ); #if SMC_DEBUG > 3 - lines = length / 16; - remainder = length % 16; - - for ( i = 0; i < lines ; i ++ ) { - int cur; - - for ( cur = 0; cur < 8; cur ++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - printf("%02x%02x ", a, b ); - } - printf("\n"); - } - for ( i = 0; i < remainder/2 ; i++ ) { - byte a, b; - - a = *(buf ++ ); - b = *(buf ++ ); - printf("%02x%02x ", a, b ); - } - printf("\n"); + lines = length / 16; + remainder = length % 16; + + for ( i = 0; i < lines ; i ++ ) { + int cur; + + for ( cur = 0; cur < 8; cur ++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); + } + for ( i = 0; i < remainder/2 ; i++ ) { + byte a, b; + + a = *(buf ++ ); + b = *(buf ++ ); + printf("%02x%02x ", a, b ); + } + printf("\n"); #endif #endif } @@ -1413,45 +1404,45 @@ int smc_get_ethaddr(bd_t *bd) { int env_size, rom_valid, env_present = 0, reg; char *s = NULL, *e, *v_mac, es[] = "11:22:33:44:55:66"; - uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6]; + uchar s_env_mac[64], v_env_mac[6], v_rom_mac[6]; - env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); + env_size = getenv_r ("ethaddr", s_env_mac, sizeof (s_env_mac)); if ((env_size > 0) && (env_size < sizeof(es))) { /* exit if env is bad */ - printf("\n*** ERROR: ethaddr is not set properly!!\n"); - return(-1); + printf("\n*** ERROR: ethaddr is not set properly!!\n"); + return(-1); } - + if(env_size > 0){ - env_present = 1; - s = s_env_mac; + env_present = 1; + s = s_env_mac; } - + for (reg = 0; reg < 6; ++reg) { /* turn string into mac value */ - v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; - if (s) - s = (*e) ? e + 1 : e; + v_env_mac[reg] = s ? simple_strtoul (s, &e, 16) : 0; + if (s) + s = (*e) ? e + 1 : e; } - - rom_valid = get_rom_mac(v_rom_mac); /* get ROM mac value if any */ - + + rom_valid = get_rom_mac(v_rom_mac); /* get ROM mac value if any */ + if(!env_present){ /* if NO env */ - if(rom_valid){ /* but ROM is valid */ - v_mac = v_rom_mac; - sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0], - v_mac[1] ,v_mac[2], v_mac[3],v_mac[4], v_mac[5]) ; - setenv ("ethaddr", s_env_mac); - }else{ /* no env, bad ROM */ - printf("\n*** ERROR: ethaddr is NOT set !!\n"); - return(-1); - } + if(rom_valid){ /* but ROM is valid */ + v_mac = v_rom_mac; + sprintf (s_env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", v_mac[0], + v_mac[1] ,v_mac[2], v_mac[3],v_mac[4], v_mac[5]) ; + setenv ("ethaddr", s_env_mac); + }else{ /* no env, bad ROM */ + printf("\n*** ERROR: ethaddr is NOT set !!\n"); + return(-1); + } }else /* good env, don't care ROM */ v_mac = v_env_mac; /* always use a good env over a ROM */ - + if(env_present && rom_valid) /* if both env and ROM are good */ - if(memcmp(v_env_mac, v_rom_mac, 6) != 0){ - printf("\n*** Warning: Environment and ROM MAC addresses don't match\n"); - printf("*** Using Environment MAC\n"); - } + if(memcmp(v_env_mac, v_rom_mac, 6) != 0){ + printf("\n*** Warning: Environment and ROM MAC addresses don't match\n"); + printf("*** Using Environment MAC\n"); + } memcpy (bd->bi_enetaddr, v_mac, 6); /* update global address to match env (allows env changing) */ smc_set_mac_addr(v_mac); /* use old function to update smc default */ return(0); @@ -1460,7 +1451,7 @@ int smc_get_ethaddr(bd_t *bd) int get_rom_mac(char *v_rom_mac) { int is_rom_present = 0; -#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ +#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ char hw_mac_addr[] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; memcpy (v_rom_mac, hw_mac_addr, 6); @@ -1468,12 +1459,12 @@ int get_rom_mac(char *v_rom_mac) #else if(is_rom_present) { - /* if eeprom contents are valid - * extract mac address into hw_mac_addr, 8 or 16 bit accesses - * memcpy (v_rom_mac, hc_mac_addr, 6); - * return(1); - */ - } + /* if eeprom contents are valid + * extract mac address into hw_mac_addr, 8 or 16 bit accesses + * memcpy (v_rom_mac, hc_mac_addr, 6); + * return(1); + */ + } memset(v_rom_mac, 0, 6); return(0); #endif diff --git a/drivers/smc91111.h b/drivers/smc91111.h index 3ac0a03d5..4efa25656 100644 --- a/drivers/smc91111.h +++ b/drivers/smc91111.h @@ -574,7 +574,6 @@ enum { /* Uses the same bit definitions as PHY_INT_REG */ - /*------------------------------------------------------------------------- . I define some macros to make it easier to do somewhat common . or slightly complicated, repeated tasks. @@ -616,4 +615,3 @@ enum { IM_MDINT) #endif /* _SMC_91111_H_ */ - diff --git a/drivers/smiLynxEM.c b/drivers/smiLynxEM.c index 75d5a31bd..c2b98cfa7 100644 --- a/drivers/smiLynxEM.c +++ b/drivers/smiLynxEM.c @@ -54,9 +54,9 @@ GraphicDevice smi; */ #define VIDEO_MODES 7 #define DUAL_800_600 0 /* SMI710:VGA1:75Hz (pitch=1600) */ - /* VGA2:60/120Hz (pitch=1600) */ - /* SMI810:VGA1:75Hz (pitch=1600) */ - /* VGA2:75Hz (pitch=1600) */ + /* VGA2:60/120Hz (pitch=1600) */ + /* SMI810:VGA1:75Hz (pitch=1600) */ + /* VGA2:75Hz (pitch=1600) */ #define DUAL_1024_768 1 /* VGA1:75Hz VGA2:73Hz (pitch=2048) */ #define SINGLE_800_600 2 /* VGA1:75Hz (pitch=800) */ #define SINGLE_1024_768 3 /* VGA1:75Hz (pitch=1024) */ @@ -127,7 +127,6 @@ typedef struct { } SmiCapturePort; - /* * Register values for common video modes */ @@ -514,8 +513,8 @@ static void smiLoadRegs ( for (i=0; i<tabSize; i+=2) { - out8 (iReg, regTab[i]); - out8 (dReg, regTab[i+1]); + out8 (iReg, regTab[i]); + out8 (dReg, regTab[i+1]); } } @@ -568,39 +567,39 @@ static void smiInitVideoProcessor (void) /* data width and offset */ out32r ((pGD->vprBase + 0x0010), - ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | - (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); + ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | + (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); /* video window 1 */ out32r ((pGD->vprBase + 0x0014), - ((pVWin->top << 16) | pVWin->left)); + ((pVWin->top << 16) | pVWin->left)); out32r ((pGD->vprBase + 0x0018), - ((pVWin->bottom << 16) | pVWin->right)); + ((pVWin->bottom << 16) | pVWin->right)); out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); out32r ((pGD->vprBase + 0x0020), - (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); out32r ((pGD->vprBase + 0x0024), - (((pVWin->hStretch) << 8) | pVWin->vStretch)); + (((pVWin->hStretch) << 8) | pVWin->vStretch)); /* video window 2 */ out32r ((pGD->vprBase + 0x0028), - ((pVWin->top << 16) | pVWin->left)); + ((pVWin->top << 16) | pVWin->left)); out32r ((pGD->vprBase + 0x002c), - ((pVWin->bottom << 16) | pVWin->right)); + ((pVWin->bottom << 16) | pVWin->right)); out32r ((pGD->vprBase + 0x0030), - pVWin->srcStart / 8); + pVWin->srcStart / 8); out32r ((pGD->vprBase + 0x0034), - (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); + (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); out32r ((pGD->vprBase + 0x0038), - (((pVWin->hStretch) << 8) | pVWin->vStretch)); + (((pVWin->hStretch) << 8) | pVWin->vStretch)); /* fifo prio control */ out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); @@ -634,31 +633,31 @@ static void smiInitDrawingEngine (void) /* set clip rect */ out32r ((pGD->dprBase + 0x002c), 0); out32r ((pGD->dprBase + 0x0030), - ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); + ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); /* src row pitch */ val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); out32r ((pGD->dprBase + 0x0010), - (val | pGD->plnSizeX * pGD->gdfBytesPP)); + (val | pGD->plnSizeX * pGD->gdfBytesPP)); /* dst row pitch */ val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); out32r ((pGD->dprBase + 0x0010), - (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); + (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); /* window width src/dst */ out32r ((pGD->dprBase + 0x003c), - (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | - (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); + (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | + (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); out16r ((pGD->dprBase + 0x001e), 0x0000); /* src base adrs */ out32r ((pGD->dprBase + 0x0040), - (((pGD->frameAdrs/8) & 0x000fffff))); + (((pGD->frameAdrs/8) & 0x000fffff))); /* dst base adrs */ out32r ((pGD->dprBase + 0x0044), - (((pGD->frameAdrs/8) & 0x000fffff))); + (((pGD->frameAdrs/8) & 0x000fffff))); /* foreground color */ out32r ((pGD->dprBase + 0x0014), pGD->fg); @@ -702,29 +701,29 @@ void *video_hw_init (void) unsigned int gdfTab[] = { 1, 2, 2, 4, 3, 1 }; char *penv; char *gdfModes[] = - { - "8 Bit Index Color", - "15 Bit 5-5-5 RGB", - "16 Bit 5-6-5 RGB", - "32 Bit X-8-8-8 RGB", - "24 Bit 8-8-8 RGB", - "8 Bit 3-3-2 RGB" - }; + { + "8 Bit Index Color", + "15 Bit 5-5-5 RGB", + "16 Bit 5-6-5 RGB", + "32 Bit X-8-8-8 RGB", + "24 Bit 8-8-8 RGB", + "8 Bit 3-3-2 RGB" + }; int vgaModes[16][2] = - { - {769, -1}, {771, 0x00002}, {773, 0x00003}, {775, 0x00004}, - {784, -1}, {787, 0x10002}, {790, 0x10003}, {793, 0x10004}, - {785, -1}, {788, 0x20002}, {791, 0x20003}, {794, 0x20004}, - {786, -1}, {789, 0x40002}, {792, 0x40003}, {795, 0x40004} - }; + { + {769, -1}, {771, 0x00002}, {773, 0x00003}, {775, 0x00004}, + {784, -1}, {787, 0x10002}, {790, 0x10003}, {793, 0x10004}, + {785, -1}, {788, 0x20002}, {791, 0x20003}, {794, 0x20004}, + {786, -1}, {789, 0x40002}, {792, 0x40003}, {795, 0x40004} + }; /* Search for video chip */ printf("Video: "); if ((devbusfn = pci_find_devices(supported, 0)) < 0) { - printf ("Controller not found !\n"); - return (NULL); + printf ("Controller not found !\n"); + return (NULL); } /* PCI setup */ @@ -735,29 +734,29 @@ void *video_hw_init (void) /* Initialize the video controller */ if ((penv = getenv ("videomode")) != NULL) - videomode = (int)simple_strtoul (penv, NULL, 16); + videomode = (int)simple_strtoul (penv, NULL, 16); else - videomode = 0x303; /* Default 800x600 8 bit index color */ + videomode = 0x303; /* Default 800x600 8 bit index color */ /* Compare with common vga mode numbers */ for (i=0; i<16; i++) { - if (vgaModes[i][0] == videomode) - { - if (vgaModes[i][1] == -1) - { - printf("Videomode not supported !\n"); - return (NULL); /* mode not supported */ - } - pGD->mode = vgaModes[i][1]; /* use driver int. mode number */ - break; - } + if (vgaModes[i][0] == videomode) + { + if (vgaModes[i][1] == -1) + { + printf("Videomode not supported !\n"); + return (NULL); /* mode not supported */ + } + pGD->mode = vgaModes[i][1]; /* use driver int. mode number */ + break; + } } /* Extract graphic data format */ pGD->gdfIndex = (pGD->mode & 0x00070000) >> 16; if (pGD->gdfIndex > 5) - pGD->gdfIndex = 0; + pGD->gdfIndex = 0; pGD->gdfBytesPP = gdfTab[pGD->gdfIndex]; /* Extract graphic resolution */ @@ -766,71 +765,71 @@ void *video_hw_init (void) /* Exit for not supported resolutions */ if (((pGD->mode==DUAL_800_600) || (pGD->mode==DUAL_1024_768)) && (pGD->gdfBytesPP > 1)) { - printf ("Dual screen for 1BPP only !\n"); - return (NULL); + printf ("Dual screen for 1BPP only !\n"); + return (NULL); } if ((pGD->mode==SINGLE_1280_1024) && (pGD->gdfBytesPP==4)) { - printf ("Out of memory !\n"); - return (NULL); + printf ("Out of memory !\n"); + return (NULL); } /* Set graphic parameters */ switch (pGD->mode) { case DUAL_800_600: - pGD->winSizeX = 800; - pGD->winSizeY = 600; - pGD->plnSizeX = 1600; - pGD->plnSizeY = 600; - sprintf (pGD->modeIdent, "Dual Screen 800x600 with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 800; + pGD->winSizeY = 600; + pGD->plnSizeX = 1600; + pGD->plnSizeY = 600; + sprintf (pGD->modeIdent, "Dual Screen 800x600 with %s", gdfModes[pGD->gdfIndex]); + break; case DUAL_1024_768: - pGD->winSizeX = 1024; - pGD->winSizeY = 768; - pGD->plnSizeX = 2048; - pGD->plnSizeY = 768; - sprintf (pGD->modeIdent, "Dual Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 1024; + pGD->winSizeY = 768; + pGD->plnSizeX = 2048; + pGD->plnSizeY = 768; + sprintf (pGD->modeIdent, "Dual Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]); + break; case SINGLE_800_600: - pGD->winSizeX = 800; - pGD->winSizeY = 600; - pGD->plnSizeX = 800; - pGD->plnSizeY = 600; - sprintf (pGD->modeIdent, "Single Screen 800x600 with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 800; + pGD->winSizeY = 600; + pGD->plnSizeX = 800; + pGD->plnSizeY = 600; + sprintf (pGD->modeIdent, "Single Screen 800x600 with %s", gdfModes[pGD->gdfIndex]); + break; case SINGLE_1024_768: - pGD->winSizeX = 1024; - pGD->winSizeY = 768; - pGD->plnSizeX = 1024; - pGD->plnSizeY = 768; - sprintf (pGD->modeIdent,"Single Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 1024; + pGD->winSizeY = 768; + pGD->plnSizeX = 1024; + pGD->plnSizeY = 768; + sprintf (pGD->modeIdent,"Single Screen 1024x768 with %s", gdfModes[pGD->gdfIndex]); + break; case TV_MODE_CCIR: - pGD->winSizeX = 720; - pGD->winSizeY = 576; - pGD->plnSizeX = 720; - pGD->plnSizeY = 576; - sprintf (pGD->modeIdent, "TV Mode CCIR with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 720; + pGD->winSizeY = 576; + pGD->plnSizeX = 720; + pGD->plnSizeY = 576; + sprintf (pGD->modeIdent, "TV Mode CCIR with %s", gdfModes[pGD->gdfIndex]); + break; case TV_MODE_EIA: - pGD->winSizeX = 720; - pGD->winSizeY = 484; - pGD->plnSizeX = 720; - pGD->plnSizeY = 484; - sprintf (pGD->modeIdent, "TV Mode EIA with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 720; + pGD->winSizeY = 484; + pGD->plnSizeX = 720; + pGD->plnSizeY = 484; + sprintf (pGD->modeIdent, "TV Mode EIA with %s", gdfModes[pGD->gdfIndex]); + break; case SINGLE_1280_1024: - pGD->winSizeX = 1280; - pGD->winSizeY = 1024; - pGD->plnSizeX = 1280; - pGD->plnSizeY = 1024; - sprintf (pGD->modeIdent, "Single Screen 1280x1024 with %s", gdfModes[pGD->gdfIndex]); - break; + pGD->winSizeX = 1280; + pGD->winSizeY = 1024; + pGD->plnSizeX = 1280; + pGD->plnSizeY = 1024; + sprintf (pGD->modeIdent, "Single Screen 1280x1024 with %s", gdfModes[pGD->gdfIndex]); + break; default: - printf("Videomode not supported !\n"); - return (NULL); + printf("Videomode not supported !\n"); + return (NULL); } @@ -856,51 +855,51 @@ void *video_hw_init (void) /* Sytem Control Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_SCR, sizeof(SMI_SCR)); + SMI_SCR, sizeof(SMI_SCR)); /* extented CRT Register */ smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, - SMI_EXT_CRT[pGD->mode], sizeof(SMI_EXT_CRT)/VIDEO_MODES); + SMI_EXT_CRT[pGD->mode], sizeof(SMI_EXT_CRT)/VIDEO_MODES); /* Sequencer Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_SEQR, sizeof(SMI_SEQR)); + SMI_SEQR, sizeof(SMI_SEQR)); /* Power Control Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_PCR[pGD->mode], sizeof(SMI_PCR)/VIDEO_MODES); + SMI_PCR[pGD->mode], sizeof(SMI_PCR)/VIDEO_MODES); /* Memory Control Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_MCR[pGD->mode], sizeof(SMI_MCR)/VIDEO_MODES); + SMI_MCR[pGD->mode], sizeof(SMI_MCR)/VIDEO_MODES); /* Clock Control Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_CCR[pGD->mode], sizeof(SMI_CCR)/VIDEO_MODES); + SMI_CCR[pGD->mode], sizeof(SMI_CCR)/VIDEO_MODES); /* Shadow VGA Register */ smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, - SMI_SHVGA[pGD->mode], sizeof(SMI_SHVGA)/VIDEO_MODES); + SMI_SHVGA[pGD->mode], sizeof(SMI_SHVGA)/VIDEO_MODES); /* General Purpose Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_GPR[pGD->mode], sizeof(SMI_GPR)/VIDEO_MODES); + SMI_GPR[pGD->mode], sizeof(SMI_GPR)/VIDEO_MODES); /* Hardware Cusor Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_HCR[pGD->mode], sizeof(SMI_HCR)/VIDEO_MODES); + SMI_HCR[pGD->mode], sizeof(SMI_HCR)/VIDEO_MODES); /* Flat Panel Register */ smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, - SMI_FPR[pGD->mode], sizeof(SMI_FPR)/VIDEO_MODES); + SMI_FPR[pGD->mode], sizeof(SMI_FPR)/VIDEO_MODES); /* CRTC Register */ smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, - SMI_CRTCR[pGD->mode], sizeof(SMI_CRTCR)/VIDEO_MODES); + SMI_CRTCR[pGD->mode], sizeof(SMI_CRTCR)/VIDEO_MODES); /* Graphics Controller Register */ smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, - SMI_GCR, sizeof(SMI_GCR)); + SMI_GCR, sizeof(SMI_GCR)); /* Patch memory and refresh settings for SMI710 */ if (device_id == PCI_DEVICE_ID_SMI_710) diff --git a/drivers/sym53c8xx.c b/drivers/sym53c8xx.c index e03a04924..ae10f80ec 100644 --- a/drivers/sym53c8xx.c +++ b/drivers/sym53c8xx.c @@ -38,7 +38,6 @@ #ifdef CONFIG_SCSI_SYM53C8XX #include <command.h> -#include <cmd_boot.h> #include <pci.h> #include <asm/processor.h> #include <sym53c8xx.h> @@ -182,7 +181,6 @@ void scsi_print_error(ccb *pccb) } - /****************************************************************************** * sets-up the SCSI controller * the base memory address is retrived via the pci_read_config_dword @@ -404,7 +402,6 @@ void scsi_print_script(void) } - void scsi_set_script(ccb *pccb) { int busdevfunc = pccb->priv; @@ -587,7 +584,6 @@ void scsi_set_script(ccb *pccb) } - void scsi_issue(ccb *pccb) { int busdevfunc = pccb->priv; @@ -750,8 +746,6 @@ retry: } - - void scsi_chip_init(void) { /* first we issue a soft reset */ diff --git a/drivers/ti_pci1410a.c b/drivers/ti_pci1410a.c index a2b1a17f2..c67238275 100644 --- a/drivers/ti_pci1410a.c +++ b/drivers/ti_pci1410a.c @@ -63,7 +63,6 @@ #include <asm/io.h> #include <pcmcia.h> -#include <cmd_pcmcia.h> #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && defined(CONFIG_IDE_TI_CARDBUS) @@ -94,7 +93,7 @@ int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif int rcode = 0; - + if (argc != 2) { printf ("Usage: pinit {on | off}\n"); return 1; @@ -107,7 +106,7 @@ int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) printf ("Usage: pinit {on | off}\n"); return 1; } - + return rcode; } @@ -125,14 +124,14 @@ static u32 socket_base; static u32 pcmcia_cis_ptr; int pcmcia_on(int ide_base_bus) -{ +{ u16 dev_id; u32 socket_status; int slot = 0; int cis_len; u16 io_base; u16 io_len; - + /* * Find the CardBus PCI device(s). */ @@ -140,9 +139,9 @@ int pcmcia_on(int ide_base_bus) printf("Ti CardBus: not found\n"); return 1; } - + pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id); - + if (dev_id == 0xac56) { debug("Enable PCMCIA Ti PCI1510\n"); } else { @@ -153,7 +152,7 @@ int pcmcia_on(int ide_base_bus) cis_len = CFG_PCMCIA_CIS_WIN_SIZE; io_base = CFG_PCMCIA_IO_WIN; - io_len = CFG_PCMCIA_IO_WIN_SIZE; + io_len = CFG_PCMCIA_IO_WIN_SIZE; /* * Setup the PCI device. @@ -164,9 +163,9 @@ int pcmcia_on(int ide_base_bus) socket_status = readl(socket_base+8); if ((socket_status & 6) == 0) { printf("Card Present: "); - + switch (socket_status & 0x3c00) { - + case 0x400: printf("5V "); break; @@ -188,44 +187,44 @@ int pcmcia_on(int ide_base_bus) printf("32bit CardBus Card\n"); break; default: - printf("8bit PC-Card\n"); + printf("8bit PC-Card\n"); break; - } + } } - - + + writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */ writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */ /* Careful: the linux yenta driver do not seem to reset the offset * in the i/o windows, so leaving them non-zero is a problem */ - + writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */ writeb(io_base>>8, socket_base + 0x809); writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */ writeb((io_base + io_len - 1)>>8, socket_base + 0x80b); - writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */ + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */ writeb(0x00, socket_base + 0x837); - - writeb((pcmcia_cis_ptr&0x000ff000) >> 12, + + writeb((pcmcia_cis_ptr&0x000ff000) >> 12, socket_base + 0x810); /* Memory window 0 start address bits 19-12 */ - writeb((pcmcia_cis_ptr&0x00f00000) >> 20, + writeb((pcmcia_cis_ptr&0x00f00000) >> 20, socket_base + 0x811); /* Memory window 0 start address bits 23-20 */ - writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12, + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12, socket_base + 0x812); /* Memory window 0 end address bits 19-12*/ - writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20, + writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20, socket_base + 0x813); /* Memory window 0 end address bits 23-20*/ - writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */ - writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and + writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */ + writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and * options (read/write, attribute access) */ writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */ writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */ - - writeb((pcmcia_cis_ptr & 0xff000000) >> 24, + + writeb((pcmcia_cis_ptr & 0xff000000) >> 24, socket_base + 0x840); /* Memory window address bits 31-24 */ - + /* turn off voltage */ if (voltage_set(slot, 0, 0)) { return 1; @@ -235,11 +234,11 @@ int pcmcia_on(int ide_base_bus) if (hardware_enable(slot)) { return 1; } - + if (check_ide_device(slot, ide_base_bus)) { return 1; } - + return 0; } @@ -249,30 +248,30 @@ int pcmcia_on(int ide_base_bus) static int pcmcia_off (void) { int slot = 0; - + writeb(0x00, socket_base + 0x806); /* disable all I/O and memory windows */ - + writeb(0x00, socket_base + 0x808); /* I/O window 0 base address */ writeb(0x00, socket_base + 0x809); writeb(0x00, socket_base + 0x80a); /* I/O window 0 end address */ writeb(0x00, socket_base + 0x80b); - writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */ + writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address */ writeb(0x00, socket_base + 0x837); - + writeb(0x00, socket_base + 0x80c); /* I/O window 1 base address */ writeb(0x00, socket_base + 0x80d); writeb(0x00, socket_base + 0x80e); /* I/O window 1 end address */ writeb(0x00, socket_base + 0x80f); - writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */ + writeb(0x00, socket_base + 0x838); /* I/O window 1 offset address */ writeb(0x00, socket_base + 0x839); - + writeb(0x00, socket_base + 0x810); /* Memory window 0 start address */ writeb(0x00, socket_base + 0x811); writeb(0x00, socket_base + 0x812); /* Memory window 0 end address */ writeb(0x00, socket_base + 0x813); writeb(0x00, socket_base + 0x814); /* Memory window 0 offset */ writeb(0x00, socket_base + 0x815); - + writeb(0xc0, socket_base + 0x840); /* Memory window 0 page address */ @@ -282,7 +281,7 @@ static int pcmcia_off (void) /* disable external hardware */ printf ("Shutdown and Poweroff Ti PCI1410A\n"); hardware_disable(slot); - + return 0; } @@ -307,14 +306,14 @@ static int check_ide_device(int slot, int ide_base_bus) u32 socket_status; debug ("PCMCIA MEM: %08X\n", pcmcia_cis_ptr); - + socket_status = readl(socket_base+8); - + if ((socket_status & 6) != 0 || (socket_status & 0x20) != 0) { printf("no card or CardBus card\n"); return 1; } - + start = p = (volatile uchar *) pcmcia_cis_ptr; while ((p - start) < MAX_TUPEL_SZ) { @@ -327,7 +326,7 @@ static int check_ide_device(int slot, int ide_base_bus) len = *p; p += 2; #if defined(DEBUG) && (DEBUG > 1) - { + { volatile uchar *q = p; printf ("\nTuple code %02x length %d\n\tData:", code, len); @@ -378,28 +377,27 @@ static int check_ide_device(int slot, int ide_base_bus) printf("unknown card type\n"); return 1; } - + /* select config index 1 */ - writeb(1, pcmcia_cis_ptr + config_base); + writeb(1, pcmcia_cis_ptr + config_base); #if 0 printf("Confiuration Option Register: %02x\n", readb(pcmcia_cis_ptr + config_base)); printf("Card Confiuration and Status Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 2)); printf("Pin Replacement Register Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 4)); printf("Socket and Copy Register: %02x\n", readb(pcmcia_cis_ptr + config_base + 6)); -#endif +#endif ide_devices_found |= (1 << (slot+ide_base_bus)); - + return 0; } - static int voltage_set(int slot, int vcc, int vpp) { u32 socket_control; int reg=0; - + switch (slot) { case 0: reg = socket_base + 0x10; @@ -407,10 +405,10 @@ static int voltage_set(int slot, int vcc, int vpp) default: return 1; } - + socket_control = 0; - - + + switch (vcc) { case 50: socket_control |= 0x20; @@ -421,7 +419,7 @@ static int voltage_set(int slot, int vcc, int vpp) case 0: default: } - + switch (vpp) { case 120: socket_control |= 0x1; @@ -437,27 +435,27 @@ static int voltage_set(int slot, int vcc, int vpp) } writel(socket_control, reg); - + debug ("voltage_set: Ti PCI1410A Slot %d, Vcc=%d.%d, Vpp=%d.%d\n", slot, vcc/10, vcc%10, vpp/10, vpp%10); - + udelay(500); return 0; } - + static int hardware_enable(int slot) { u32 socket_status; u16 brg_ctrl; int is_82365sl; - + socket_status = readl(socket_base+8); - + if ((socket_status & 6) == 0) { - + switch (socket_status & 0x3c00) { - + case 0x400: printf("5V "); voltage_set(slot, 50, 0); @@ -475,25 +473,24 @@ static int hardware_enable(int slot) } else { voltage_set(slot, 0, 0); } - + pci_read_config_word(devbusfn, PCI_BRIDGE_CONTROL, &brg_ctrl); brg_ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET; pci_write_config_word(devbusfn, PCI_BRIDGE_CONTROL, brg_ctrl); - is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2); + is_82365sl = ((readb(socket_base+0x800) & 0x0f) == 2); writeb(is_82365sl?0x90:0x98, socket_base+0x802); writeb(0x67, socket_base+0x803); udelay(100000); -#if 0 - printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n", +#if 0 + printf("ExCA Id %02x, Card Status %02x, Power config %02x, Interrupt Config %02x, bridge control %04x %d\n", readb(socket_base+0x800), readb(socket_base+0x801), readb(socket_base+0x802), readb(socket_base+0x803), brg_ctrl, is_82365sl); -#endif - +#endif + return ((readb(socket_base+0x801)&0x6c)==0x6c)?0:1; } - static int hardware_disable(int slot) { voltage_set(slot, 0, 0); @@ -546,11 +543,11 @@ static void print_fixed(volatile uchar *p) return; puts(indent); - + switch (*p) { case CISTPL_FUNCE_IDE_IFACE: { uchar iface = *(p+2); - + puts ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown"); puts (" interface "); break; @@ -560,43 +557,43 @@ static void print_fixed(volatile uchar *p) { uchar f1 = *(p+2); uchar f2 = *(p+4); - + puts((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]"); - + if (f1 & CISTPL_IDE_UNIQUE) { puts(" [unique]"); } - + puts((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]"); - + if (f2 & CISTPL_IDE_HAS_SLEEP) { puts(" [sleep]"); } - + if (f2 & CISTPL_IDE_HAS_STANDBY) { puts(" [standby]"); } - + if (f2 & CISTPL_IDE_HAS_IDLE) { puts(" [idle]"); } - + if (f2 & CISTPL_IDE_LOW_POWER) { puts(" [low power]"); } - + if (f2 & CISTPL_IDE_REG_INHIBIT) { puts(" [reg inhibit]"); } - + if (f2 & CISTPL_IDE_HAS_INDEX) { puts(" [index]"); } - + if (f2 & CISTPL_IDE_IOIS16) { puts(" [IOis16]"); } - + break; } } @@ -623,10 +620,10 @@ static int identify(volatile uchar *p) if (p == NULL) return (0); /* Don't know */ - + t = id_str; done =0; - + for (i=0; i<=4 && !done; ++i, p+=2) { while ((data = *p) != '\0') { if (data == 0xFF) { @@ -661,7 +658,7 @@ static int identify(volatile uchar *p) return 1; } } - + return 0; /* don't know */ } diff --git a/drivers/tigon3.c b/drivers/tigon3.c index c20dbe5cd..ec2cd2ac3 100644 --- a/drivers/tigon3.c +++ b/drivers/tigon3.c @@ -53,7 +53,7 @@ STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice); STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice); STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid); STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize); STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number); STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice); STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, @@ -90,7 +90,6 @@ LM_UINT32 Register) { } /* LM_RegRdInd */ - /******************************************************************************/ /* Description: */ /* */ @@ -113,7 +112,6 @@ LM_UINT32 Value32) { } /* LM_RegWrInd */ - /******************************************************************************/ /* Description: */ /* */ @@ -140,7 +138,6 @@ LM_UINT32 MemAddr) { } /* LM_MemRdInd */ - /******************************************************************************/ /* Description: */ /* */ @@ -163,7 +160,6 @@ LM_UINT32 Value32) { } /* LM_MemWrInd */ - /******************************************************************************/ /* Description: */ /* */ @@ -184,84 +180,84 @@ PLM_DEVICE_BLOCK pDevice) { pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); while(pPacket) { - switch(pPacket->u.Rx.RcvProdRing) { + switch(pPacket->u.Rx.RcvProdRing) { #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = - &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; - pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; - - /* Initialize the receive buffer pointer */ + case T3_JUMBO_RCV_PROD_RING: /* Jumbo Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = + &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING; + pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize; + + /* Initialize the receive buffer pointer */ #if 0 /* Jimmy, deleted in new */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; #endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); - /* Update the producer index. */ - pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & - T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + /* Update the producer index. */ + pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) & + T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; - JumboBdAdded++; - break; + JumboBdAdded++; + break; #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ - /* Initialize the buffer descriptor. */ - pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; - pRcvBd->Flags = RCV_BD_FLAG_END; - pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; + case T3_STD_RCV_PROD_RING: /* Standard Receive Ring. */ + /* Initialize the buffer descriptor. */ + pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx]; + pRcvBd->Flags = RCV_BD_FLAG_END; + pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE; - /* Initialize the receive buffer pointer */ + /* Initialize the receive buffer pointer */ #if 0 /* Jimmy, deleted in new replaced with MM_MapRxDma */ - pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; - pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; + pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low; + pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High; #endif - MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); + MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr); - /* The opaque field may point to an offset from a fix addr. */ - pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - - MM_UINT_PTR(pDevice->pPacketDescBase)); + /* The opaque field may point to an offset from a fix addr. */ + pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) - + MM_UINT_PTR(pDevice->pPacketDescBase)); - /* Update the producer index. */ - pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & - T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + /* Update the producer index. */ + pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) & + T3_STD_RCV_RCB_ENTRY_COUNT_MASK; - StdBdAdded++; - break; + StdBdAdded++; + break; - case T3_UNKNOWN_RCV_PROD_RING: - default: - Lmstatus = LM_STATUS_FAILURE; - break; - } /* switch */ + case T3_UNKNOWN_RCV_PROD_RING: + default: + Lmstatus = LM_STATUS_FAILURE; + break; + } /* switch */ - /* Bail out if there is any error. */ - if(Lmstatus != LM_STATUS_SUCCESS) - { - break; - } + /* Bail out if there is any error. */ + if(Lmstatus != LM_STATUS_SUCCESS) + { + break; + } - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); } /* while */ wmb(); /* Update the procedure index. */ if(StdBdAdded) { - MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); + MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx); } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT if(JumboBdAdded) { - MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, - pDevice->RxJumboProdIdx); + MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, + pDevice->RxJumboProdIdx); } #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ @@ -283,12 +279,12 @@ LM_NvramInit( /* Intialize clock period and state machine. */ Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) | - SEEPROM_ADDR_FSM_RESET; + SEEPROM_ADDR_FSM_RESET; REG_WR(pDevice, Grc.EepromAddr, Value32); for(j = 0; j < 100; j++) { - MM_Wait(10); + MM_Wait(10); } /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */ @@ -297,16 +293,16 @@ LM_NvramInit( /* Set the 5701 compatibility mode if we are using EEPROM. */ if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) { - Value32 = REG_RD(pDevice, Nvram.Config1); - if((Value32 & FLASH_INTERFACE_ENABLE) == 0) - { - /* Use the new interface to read EEPROM. */ - Value32 &= ~FLASH_COMPAT_BYPASS; + Value32 = REG_RD(pDevice, Nvram.Config1); + if((Value32 & FLASH_INTERFACE_ENABLE) == 0) + { + /* Use the new interface to read EEPROM. */ + Value32 &= ~FLASH_COMPAT_BYPASS; - REG_WR(pDevice, Nvram.Config1, Value32); - } + REG_WR(pDevice, Nvram.Config1, Value32); + } } } /* LM_NvRamInit */ @@ -329,7 +325,7 @@ LM_EepromRead( if(Offset > SEEPROM_CHIP_SIZE) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } Dev = Offset / SEEPROM_CHIP_SIZE; @@ -337,33 +333,32 @@ LM_EepromRead( Value32 = REG_RD(pDevice, Grc.EepromAddr); Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK | - SEEPROM_ADDR_RW_MASK); + SEEPROM_ADDR_RW_MASK); REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) | - SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); + SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ); for(j = 0; j < 1000; j++) { - Value32 = REG_RD(pDevice, Grc.EepromAddr); - if(Value32 & SEEPROM_ADDR_COMPLETE) - { - break; - } - MM_Wait(10); + Value32 = REG_RD(pDevice, Grc.EepromAddr); + if(Value32 & SEEPROM_ADDR_COMPLETE) + { + break; + } + MM_Wait(10); } if(Value32 & SEEPROM_ADDR_COMPLETE) { - Value32 = REG_RD(pDevice, Grc.EepromData); - *pData = Value32; + Value32 = REG_RD(pDevice, Grc.EepromData); + *pData = Value32; - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } return LM_STATUS_FAILURE; } /* LM_EepromRead */ - /******************************************************************************/ /* Description: */ /* */ @@ -380,88 +375,88 @@ LM_NvramRead( LM_UINT32 j; if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - Status = LM_EepromRead(pDevice, Offset, pData); + Status = LM_EepromRead(pDevice, Offset, pData); } else { - /* Determine if we have flash or EEPROM. */ - Value32 = REG_RD(pDevice, Nvram.Config1); - if(Value32 & FLASH_INTERFACE_ENABLE) - { - if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) - { - Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << - BUFFERED_FLASH_PAGE_POS) + - (Offset % BUFFERED_FLASH_PAGE_SIZE); - } - } - - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); - for (j = 0; j < 1000; j++) - { - if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) - { - break; - } - MM_Wait(20); - } - if (j == 1000) - { - return LM_STATUS_FAILURE; - } - - /* Read from flash or EEPROM with the new 5703/02 interface. */ - REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); - - REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | - NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); - - /* Wait for the done bit to clear. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); - - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(!(Value32 & NVRAM_CMD_DONE)) - { - break; - } - } - - /* Wait for the done bit. */ - if(!(Value32 & NVRAM_CMD_DONE)) - { - for(j = 0; j < 500; j++) - { - MM_Wait(10); - - Value32 = REG_RD(pDevice, Nvram.Cmd); - if(Value32 & NVRAM_CMD_DONE) - { - MM_Wait(10); - - *pData = REG_RD(pDevice, Nvram.ReadData); - - /* Change the endianess. */ - *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| - ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); - - break; - } - } - } - - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); - if(Value32 & NVRAM_CMD_DONE) - { - Status = LM_STATUS_SUCCESS; - } - else - { - Status = LM_STATUS_FAILURE; - } + /* Determine if we have flash or EEPROM. */ + Value32 = REG_RD(pDevice, Nvram.Config1); + if(Value32 & FLASH_INTERFACE_ENABLE) + { + if(Value32 & FLASH_SSRAM_BUFFERRED_MODE) + { + Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) << + BUFFERED_FLASH_PAGE_POS) + + (Offset % BUFFERED_FLASH_PAGE_SIZE); + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + for (j = 0; j < 1000; j++) + { + if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1) + { + break; + } + MM_Wait(20); + } + if (j == 1000) + { + return LM_STATUS_FAILURE; + } + + /* Read from flash or EEPROM with the new 5703/02 interface. */ + REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK); + + REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT | + NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE); + + /* Wait for the done bit to clear. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(!(Value32 & NVRAM_CMD_DONE)) + { + break; + } + } + + /* Wait for the done bit. */ + if(!(Value32 & NVRAM_CMD_DONE)) + { + for(j = 0; j < 500; j++) + { + MM_Wait(10); + + Value32 = REG_RD(pDevice, Nvram.Cmd); + if(Value32 & NVRAM_CMD_DONE) + { + MM_Wait(10); + + *pData = REG_RD(pDevice, Nvram.ReadData); + + /* Change the endianess. */ + *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)| + ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff); + + break; + } + } + } + + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1); + if(Value32 & NVRAM_CMD_DONE) + { + Status = LM_STATUS_SUCCESS; + } + else + { + Status = LM_STATUS_FAILURE; + } } return Status; @@ -480,53 +475,53 @@ LM_ReadVPD(PLM_DEVICE_BLOCK pDevice) /* Read PN from VPD */ for (j = 0; j < 256; j += 4, Vpd_dptr++ ) { - if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { - printf("BCM570x: LM_ReadVPD: VPD read failed" + if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) { + printf("BCM570x: LM_ReadVPD: VPD read failed" " (no EEPROM onboard)\n"); - return; - } - *Vpd_dptr = cpu_to_le32(Value32); + return; + } + *Vpd_dptr = cpu_to_le32(Value32); } for (j = 0; j < 256; ) { - unsigned int Vpd_r_len; - unsigned int Vpd_r_end; - - if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) - { - j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); - } - else if (Vpd[j] == 0x90) - { - Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); - j += 3; - Vpd_r_end = Vpd_r_len + j; - while (j < Vpd_r_end) - { - if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) - { - unsigned int len = Vpd[j + 2]; - - if (len <= 24) - { - memcpy(pDevice->PartNo, &Vpd[j + 3], len); - } - break; - } - else - { - if (Vpd[j + 2] == 0) - { - break; - } - j = j + Vpd[j + 2]; - } - } - break; - } - else { - break; - } + unsigned int Vpd_r_len; + unsigned int Vpd_r_end; + + if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) + { + j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8); + } + else if (Vpd[j] == 0x90) + { + Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8); + j += 3; + Vpd_r_end = Vpd_r_len + j; + while (j < Vpd_r_end) + { + if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) + { + unsigned int len = Vpd[j + 2]; + + if (len <= 24) + { + memcpy(pDevice->PartNo, &Vpd[j + 3], len); + } + break; + } + else + { + if (Vpd[j + 2] == 0) + { + break; + } + j = j + Vpd[j + 2]; + } + } + break; + } + else { + break; + } } } @@ -537,59 +532,59 @@ LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice) int i; if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS) - return; + return; if (Value32 != 0xaa559966) - return; + return; if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS) - return; + return; offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)| - ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); + ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff); if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS) - return; + return; if ((Value32 == 0x0300000e) && - (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && - (Value32 == 0)) { - - if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) - return; - ver_offset = ((ver_offset & 0xff0000) >> 8) | - ((ver_offset >> 24) & 0xff); - for (i = 0; i < 16; i += 4) { - if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != - LM_STATUS_SUCCESS) - { - return; - } - *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); - } + (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) && + (Value32 == 0)) { + + if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS) + return; + ver_offset = ((ver_offset & 0xff0000) >> 8) | + ((ver_offset >> 24) & 0xff); + for (i = 0; i < 16; i += 4) { + if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) != + LM_STATUS_SUCCESS) + { + return; + } + *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32); + } } else { - char c; - - if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) - return; - - i = 0; - c = ((Value32 & 0xff0000) >> 16); - - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; - } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; - } - pDevice->BootCodeVer[i++] = '.'; - c = (Value32 & 0xff000000) >> 24; - if (c < 10) { - pDevice->BootCodeVer[i++] = c + '0'; - } - else { - pDevice->BootCodeVer[i++] = (c / 10) + '0'; - pDevice->BootCodeVer[i++] = (c % 10) + '0'; - } - pDevice->BootCodeVer[i] = 0; + char c; + + if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS) + return; + + i = 0; + c = ((Value32 & 0xff0000) >> 16); + + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i++] = '.'; + c = (Value32 & 0xff000000) >> 24; + if (c < 10) { + pDevice->BootCodeVer[i++] = c + '0'; + } + else { + pDevice->BootCodeVer[i++] = (c / 10) + '0'; + pDevice->BootCodeVer[i++] = (c % 10) + '0'; + } + pDevice->BootCodeVer[i] = 0; } } @@ -602,57 +597,57 @@ LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice) if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) { - strcpy(pDevice->BusSpeedStr, "32-bit "); + strcpy(pDevice->BusSpeedStr, "32-bit "); } else { - strcpy(pDevice->BusSpeedStr, "64-bit "); + strcpy(pDevice->BusSpeedStr, "64-bit "); } if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) { - strcat(pDevice->BusSpeedStr, "PCI "); - if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) - { - SpeedStr = "66MHz"; - } - else - { - SpeedStr = "33MHz"; - } + strcat(pDevice->BusSpeedStr, "PCI "); + if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) + { + SpeedStr = "66MHz"; + } + else + { + SpeedStr = "33MHz"; + } } else { - strcat(pDevice->BusSpeedStr, "PCIX "); - if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) - { - SpeedStr = "133MHz"; - } - else - { - ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; - switch (ClockCtrl) - { - case 0: - SpeedStr = "33MHz"; - break; - - case 2: - SpeedStr = "50MHz"; - break; - - case 4: - SpeedStr = "66MHz"; - break; - - case 6: - SpeedStr = "100MHz"; - break; - - case 7: - SpeedStr = "133MHz"; - break; - } - } + strcat(pDevice->BusSpeedStr, "PCIX "); + if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) + { + SpeedStr = "133MHz"; + } + else + { + ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f; + switch (ClockCtrl) + { + case 0: + SpeedStr = "33MHz"; + break; + + case 2: + SpeedStr = "50MHz"; + break; + + case 4: + SpeedStr = "66MHz"; + break; + + case 6: + SpeedStr = "100MHz"; + break; + + case 7: + SpeedStr = "133MHz"; + break; + } + } } strcat(pDevice->BusSpeedStr, SpeedStr); } @@ -682,7 +677,7 @@ PLM_DEVICE_BLOCK pDevice) Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } pDevice->PciVendorId = (LM_UINT16) Value32; pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16); @@ -697,13 +692,13 @@ PLM_DEVICE_BLOCK pDevice) (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } pDevice->PciRevId = (LM_UINT8) Value32; @@ -711,7 +706,7 @@ PLM_DEVICE_BLOCK pDevice) Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } pDevice->Irq = (LM_UINT8) Value32; @@ -726,7 +721,7 @@ PLM_DEVICE_BLOCK pDevice) Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } pDevice->SubsystemVendorId = (LM_UINT16) Value32; @@ -739,10 +734,10 @@ PLM_DEVICE_BLOCK pDevice) pDevice->SavedCacheLineReg = Value32; if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 && - pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && - pDevice->ChipRevId != T3_CHIP_ID_5704_A0) + pDevice->ChipRevId != T3_CHIP_ID_5703_A2 && + pDevice->ChipRevId != T3_CHIP_ID_5704_A0) { - pDevice->UndiFix = FALSE; + pDevice->UndiFix = FALSE; } #if !PCIX_TARGET_WORKAROUND pDevice->UndiFix = FALSE; @@ -750,13 +745,13 @@ PLM_DEVICE_BLOCK pDevice) /* Map the memory base to system address space. */ if (!pDevice->UndiFix) { - Status = MM_MapMemBase(pDevice); - if(Status != LM_STATUS_SUCCESS) - { - return Status; - } - /* Initialize the memory view pointer. */ - pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; + Status = MM_MapMemBase(pDevice); + if(Status != LM_STATUS_SUCCESS) + { + return Status; + } + /* Initialize the memory view pointer. */ + pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase; } #if PCIX_TARGET_WORKAROUND @@ -766,15 +761,15 @@ PLM_DEVICE_BLOCK pDevice) MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) { - /* Enable PCI-X workaround only if we are running on 5700 BX. */ - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - pDevice->EnablePciXFix = TRUE; - } + /* Enable PCI-X workaround only if we are running on 5700 BX. */ + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + pDevice->EnablePciXFix = TRUE; + } } if (pDevice->UndiFix) { - pDevice->EnablePciXFix = TRUE; + pDevice->EnablePciXFix = TRUE; } #endif /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */ @@ -796,30 +791,30 @@ PLM_DEVICE_BLOCK pDevice) #if PCIX_TARGET_WORKAROUND /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR# - are enabled */ + are enabled */ if (pDevice->EnablePciXFix == TRUE) { - Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | - PCI_PARITY_ERROR_ENABLE); + Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE | + PCI_PARITY_ERROR_ENABLE); } if (pDevice->UndiFix) { - Value32 &= ~PCI_MEM_SPACE_ENABLE; + Value32 &= ~PCI_MEM_SPACE_ENABLE; } #endif if(pDevice->EnableMWI) { - Value32 |= PCI_MEMORY_WRITE_INVALIDATE; + Value32 |= PCI_MEMORY_WRITE_INVALIDATE; } else { - Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); + Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE); } /* Error out if mem-mapping is NOT enabled for PCI systems */ if (!(Value32 | PCI_MEM_SPACE_ENABLE)) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /* save the value we are going to write into the PCI command word */ @@ -828,7 +823,7 @@ PLM_DEVICE_BLOCK pDevice) Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } /* Set power state to D0. */ @@ -836,21 +831,21 @@ PLM_DEVICE_BLOCK pDevice) #ifdef BIG_ENDIAN_PCI pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; #else /* No CPU Swap modes for PCI IO */ /* Setup the mode registers. */ pDevice->MiscHostCtrl = - MISC_HOST_CTRL_MASK_PCI_INT | - MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | + MISC_HOST_CTRL_MASK_PCI_INT | + MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP | #ifdef BIG_ENDIAN_HOST - MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | + MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP | #endif /* BIG_ENDIAN_HOST */ - MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | - MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; + MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS | + MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW; #endif /* !BIG_ENDIAN_PCI */ /* write to PCI misc host ctr first in order to enable indirect accesses */ @@ -865,7 +860,7 @@ PLM_DEVICE_BLOCK pDevice) /* No CPU Swap modes for PCI IO */ #ifdef BIG_ENDIAN_HOST Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; #endif @@ -875,8 +870,8 @@ PLM_DEVICE_BLOCK pDevice) if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1); + REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1); } MM_Wait(40); @@ -885,10 +880,10 @@ PLM_DEVICE_BLOCK pDevice) if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) { - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK); - REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); - MM_Wait(40); /* required delay is 27usec */ + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK); + REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK); + MM_Wait(40); /* required delay is 27usec */ } REG_WR(pDevice, PciCfg.ClockCtrl, 0); REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); @@ -896,21 +891,21 @@ PLM_DEVICE_BLOCK pDevice) #if PCIX_TARGET_WORKAROUND MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32); if ((pDevice->EnablePciXFix == FALSE) && - ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) - { - if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B5) - { - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); - __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); - if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) - { - pDevice->EnablePciXFix = TRUE; - } - } + ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) + { + if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B5) + { + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300])); + __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301])); + if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300]))) + { + pDevice->EnablePciXFix = TRUE; + } + } } #endif #if 1 @@ -927,44 +922,44 @@ PLM_DEVICE_BLOCK pDevice) if((Value32 >> 16) == 0x484b) { - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[1] = (LM_UINT8) Value32; + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[1] = (LM_UINT8) Value32; - Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); + Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX); - pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[5] = (LM_UINT8) Value32; + pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24); + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[5] = (LM_UINT8) Value32; - Status = LM_STATUS_SUCCESS; + Status = LM_STATUS_SUCCESS; } else { - Status = LM_NvramRead(pDevice, 0x7c, &Value32); - if(Status == LM_STATUS_SUCCESS) - { - pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); + Status = LM_NvramRead(pDevice, 0x7c, &Value32); + if(Status == LM_STATUS_SUCCESS) + { + pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24); - Status = LM_NvramRead(pDevice, 0x80, &Value32); + Status = LM_NvramRead(pDevice, 0x80, &Value32); - pDevice->NodeAddress[2] = (LM_UINT8) Value32; - pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); - pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); - pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); - } + pDevice->NodeAddress[2] = (LM_UINT8) Value32; + pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8); + pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16); + pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24); + } } /* Assign a default address. */ if(Status != LM_STATUS_SUCCESS) { #ifndef EMBEDDED - printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); + printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n"); #endif - pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; - pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; - pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; + pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10; + pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68; + pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76; } pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0]; @@ -1016,13 +1011,13 @@ PLM_DEVICE_BLOCK pDevice) switch (T3_ASIC_REV(pDevice->ChipRevId)) { case T3_ASIC_REV_5704: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; - break; + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64; + break; default: - pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; - pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; - break; + pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR; + pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96; + break; } pDevice->LinkStatus = LM_STATUS_LINK_DOWN; @@ -1036,117 +1031,117 @@ PLM_DEVICE_BLOCK pDevice) /* Make this is a known adapter. */ pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId, - pDevice->SubsystemId); + pDevice->SubsystemId); pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK; if (pDevice->BondId != GRC_MISC_BD_ID_5700 && - pDevice->BondId != GRC_MISC_BD_ID_5701 && - pDevice->BondId != GRC_MISC_BD_ID_5702FE && - pDevice->BondId != GRC_MISC_BD_ID_5703 && - pDevice->BondId != GRC_MISC_BD_ID_5703S && - pDevice->BondId != GRC_MISC_BD_ID_5704 && - pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) + pDevice->BondId != GRC_MISC_BD_ID_5701 && + pDevice->BondId != GRC_MISC_BD_ID_5702FE && + pDevice->BondId != GRC_MISC_BD_ID_5703 && + pDevice->BondId != GRC_MISC_BD_ID_5703S && + pDevice->BondId != GRC_MISC_BD_ID_5704 && + pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) { - return LM_STATUS_UNKNOWN_ADAPTER; + return LM_STATUS_UNKNOWN_ADAPTER; } pDevice->SplitModeEnable = SPLIT_MODE_DISABLE; if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) && - (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) + (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) { - pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; - pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; + pDevice->SplitModeEnable = SPLIT_MODE_ENABLE; + pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ; } /* Get Eeprom info. */ Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR); if (Value32 == T3_NIC_DATA_SIG) { - EeSigFound = TRUE; - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); - - /* Determine PHY type. */ - switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) - { - case T3_NIC_CFG_PHY_TYPE_COPPER: - EePhyTypeSerdes = FALSE; - break; - - case T3_NIC_CFG_PHY_TYPE_FIBER: - EePhyTypeSerdes = TRUE; - break; - - default: - EePhyTypeSerdes = FALSE; - break; - } - - /* Determine PHY led mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: - EePhyLedMode = LED_MODE_THREE_LINK; - break; - - case T3_NIC_CFG_LED_MODE_LINK_SPEED: - EePhyLedMode = LED_MODE_LINK10; - break; - - default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - else - { - switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) - { - case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: - EePhyLedMode = LED_MODE_OPEN_DRAIN; - break; - - case T3_NIC_CFG_LED_MODE_OUTPUT: - EePhyLedMode = LED_MODE_OUTPUT; - break; - - default: - EePhyLedMode = LED_MODE_AUTO; - break; - } - } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - /* Enable EEPROM write protection. */ - if(Value32 & T3_NIC_EEPROM_WP) - { - pDevice->EepromWp = TRUE; - } - } - - /* Get the PHY Id. */ - Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); - if (Value32) - { - EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & - PHY_ID1_OUI_MASK) << 10; - - Value32 = Value32 & T3_NIC_PHY_ID2_MASK; - - EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | - (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); - } - else - { - EePhyId = 0; - } + EeSigFound = TRUE; + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR); + + /* Determine PHY type. */ + switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) + { + case T3_NIC_CFG_PHY_TYPE_COPPER: + EePhyTypeSerdes = FALSE; + break; + + case T3_NIC_CFG_PHY_TYPE_FIBER: + EePhyTypeSerdes = TRUE; + break; + + default: + EePhyTypeSerdes = FALSE; + break; + } + + /* Determine PHY led mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED: + EePhyLedMode = LED_MODE_THREE_LINK; + break; + + case T3_NIC_CFG_LED_MODE_LINK_SPEED: + EePhyLedMode = LED_MODE_LINK10; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + else + { + switch(Value32 & T3_NIC_CFG_LED_MODE_MASK) + { + case T3_NIC_CFG_LED_MODE_OPEN_DRAIN: + EePhyLedMode = LED_MODE_OPEN_DRAIN; + break; + + case T3_NIC_CFG_LED_MODE_OUTPUT: + EePhyLedMode = LED_MODE_OUTPUT; + break; + + default: + EePhyLedMode = LED_MODE_AUTO; + break; + } + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + /* Enable EEPROM write protection. */ + if(Value32 & T3_NIC_EEPROM_WP) + { + pDevice->EepromWp = TRUE; + } + } + + /* Get the PHY Id. */ + Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR); + if (Value32) + { + EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) & + PHY_ID1_OUI_MASK) << 10; + + Value32 = Value32 & T3_NIC_PHY_ID2_MASK; + + EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) | + (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK); + } + else + { + EePhyId = 0; + } } else { - EeSigFound = FALSE; + EeSigFound = FALSE; } /* Set the PHY address. */ @@ -1168,163 +1163,163 @@ PLM_DEVICE_BLOCK pDevice) /* Set the EnableTbi flag to false if we have a copper PHY. */ switch(pDevice->PhyId & PHY_ID_MASK) { - case PHY_BCM5400_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5400_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM5401_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5401_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM5411_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5411_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM5701_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5701_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM5703_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5703_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM5704_PHY_ID: - pDevice->EnableTbi = FALSE; - break; + case PHY_BCM5704_PHY_ID: + pDevice->EnableTbi = FALSE; + break; - case PHY_BCM8002_PHY_ID: - pDevice->EnableTbi = TRUE; - break; + case PHY_BCM8002_PHY_ID: + pDevice->EnableTbi = TRUE; + break; - default: + default: - if (pAdapterInfo) - { - pDevice->PhyId = pAdapterInfo->PhyId; - pDevice->EnableTbi = pAdapterInfo->Serdes; - } - else if (EeSigFound) - { - pDevice->PhyId = EePhyId; - pDevice->EnableTbi = EePhyTypeSerdes; - } - break; + if (pAdapterInfo) + { + pDevice->PhyId = pAdapterInfo->PhyId; + pDevice->EnableTbi = pAdapterInfo->Serdes; + } + else if (EeSigFound) + { + pDevice->PhyId = EePhyId; + pDevice->EnableTbi = EePhyTypeSerdes; + } + break; } /* Bail out if we don't know the copper PHY id. */ if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) { - if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) - { - pDevice->SavedCacheLineReg &= 0xffff00ff; - pDevice->SavedCacheLineReg |= 0x4000; - } + if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) + { + pDevice->SavedCacheLineReg &= 0xffff00ff; + pDevice->SavedCacheLineReg |= 0x4000; + } } /* Change driver parameters. */ Status = MM_GetConfig(pDevice); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } #if INCLUDE_5701_AX_FIX if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { - pDevice->ResetPhyOnInit = TRUE; + pDevice->ResetPhyOnInit = TRUE; } #endif /* Save the current phy link status. */ if(!pDevice->EnableTbi) { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - /* If we don't have link reset the PHY. */ - if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) - { + /* If we don't have link reset the PHY. */ + if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit) + { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - for(j = 0; j < 100; j++) - { - MM_Wait(10); + for(j = 0; j < 100; j++) + { + MM_Wait(10); - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; - } - } + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } #if INCLUDE_5701_AX_FIX - /* 5701_AX_BX bug: only advertises 10mb speed. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - - Value32 = BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); - } + /* 5701_AX_BX bug: only advertises 10mb speed. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + Value32 = BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); + } #endif - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) - { - LM_WritePhy(pDevice, 0x18, 0x0c00); - LM_WritePhy(pDevice, 0x17, 0x201f); - LM_WritePhy(pDevice, 0x15, 0x2aaa); - } - if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - } - /* Enable Ethernet@WireSpeed. */ - if(pDevice->EnableWireSpeed) - { - LM_WritePhy(pDevice, 0x18, 0x7007); - LM_ReadPhy(pDevice, 0x18, &Value32); - LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); - } - } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) + { + LM_WritePhy(pDevice, 0x18, 0x0c00); + LM_WritePhy(pDevice, 0x17, 0x201f); + LM_WritePhy(pDevice, 0x15, 0x2aaa); + } + if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + } + /* Enable Ethernet@WireSpeed. */ + if(pDevice->EnableWireSpeed) + { + LM_WritePhy(pDevice, 0x18, 0x7007); + LM_ReadPhy(pDevice, 0x18, &Value32); + LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4); + } + } } /* Turn off tap power management. */ if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - MM_Wait(40); + MM_Wait(40); } #if INCLUDE_TBI_SUPPORT @@ -1332,110 +1327,110 @@ PLM_DEVICE_BLOCK pDevice) if(pDevice->EnableTbi) { - pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; - if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || - pDevice->DisableAutoNeg) - { - pDevice->PollTbiLink = FALSE; - } + pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE; + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) || + pDevice->DisableAutoNeg) + { + pDevice->PollTbiLink = FALSE; + } } else { - pDevice->PollTbiLink = FALSE; + pDevice->PollTbiLink = FALSE; } #endif /* INCLUDE_TBI_SUPPORT */ /* UseTaggedStatus is only valid for 5701 and later. */ if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - pDevice->UseTaggedStatus = FALSE; + pDevice->UseTaggedStatus = FALSE; - pDevice->CoalesceMode = 0; + pDevice->CoalesceMode = 0; } else { - pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | - HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; + pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT | + HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT; } /* Set the status block size. */ if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX && - T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) + T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) { - pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; + pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE; } /* Check the DURING_INT coalescing ticks parameters. */ if(pDevice->UseTaggedStatus) { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = - DEFAULT_RX_COALESCING_TICKS_DURING_INT; - } - - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = - DEFAULT_TX_COALESCING_TICKS_DURING_INT; - } - - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = - DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; - } - - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = - DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; - } + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = + DEFAULT_RX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = + DEFAULT_TX_COALESCING_TICKS_DURING_INT; + } + + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = + DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT; + } + + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = + DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT; + } } else { - if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxCoalescingTicksDuringInt = 0; - } + if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxCoalescingTicksDuringInt = 0; + } - if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxCoalescingTicksDuringInt = 0; - } + if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxCoalescingTicksDuringInt = 0; + } - if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->RxMaxCoalescedFramesDuringInt = 0; - } + if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->RxMaxCoalescedFramesDuringInt = 0; + } - if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) - { - pDevice->TxMaxCoalescedFramesDuringInt = 0; - } + if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) + { + pDevice->TxMaxCoalescedFramesDuringInt = 0; + } } #if T3_JUMBO_RCV_RCB_ENTRY_COUNT if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */)) { - pDevice->RxJumboDescCnt = 0; - if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) - { - pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; - } + pDevice->RxJumboDescCnt = 0; + if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) + { + pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + } } else { - pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + - COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; + pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ + + COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK; - if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) - { - pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; - pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; - } - pDevice->TxMtu = pDevice->RxMtu; + if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) + { + pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE; + pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */; + } + pDevice->TxMtu = pDevice->RxMtu; } #else @@ -1444,128 +1439,128 @@ PLM_DEVICE_BLOCK pDevice) pDevice->RxPacketDescCnt = #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - pDevice->RxJumboDescCnt + + pDevice->RxJumboDescCnt + #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - pDevice->RxStdDescCnt; + pDevice->RxStdDescCnt; if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) { - pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; + pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC; } if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) { - pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; + pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE; } /* Configure the proper ways to get link change interrupt. */ if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; - } - else - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; - } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } + else + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY; + } } else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - /* Auto-polling does not work on 5700_AX and 5700_BX. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; - } + /* Auto-polling does not work on 5700_AX and 5700_BX. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + } } /* Determine the method to get link change status. */ if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) { - /* The link status bit in the status block does not work on 5700_AX */ - /* and 5700_BX chips. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } - else - { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; - } + /* The link status bit in the status block does not work on 5700_AX */ + /* and 5700_BX chips. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + else + { + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK; + } } if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; } /* Configure PHY led mode. */ if(pDevice->LedMode == LED_MODE_AUTO) { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - if(pDevice->SubsystemVendorId == T3_SVID_DELL) - { - pDevice->LedMode = LED_MODE_LINK10; - } - else - { - pDevice->LedMode = LED_MODE_THREE_LINK; - - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; - } - } - - /* bug? 5701 in LINK10 mode does not seem to work when */ - /* PhyIntMode is LINK_READY. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + if(pDevice->SubsystemVendorId == T3_SVID_DELL) + { + pDevice->LedMode = LED_MODE_LINK10; + } + else + { + pDevice->LedMode = LED_MODE_THREE_LINK; + + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + } + + /* bug? 5701 in LINK10 mode does not seem to work when */ + /* PhyIntMode is LINK_READY. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && #if INCLUDE_TBI_SUPPORT - pDevice->EnableTbi == FALSE && + pDevice->EnableTbi == FALSE && #endif - pDevice->LedMode == LED_MODE_LINK10) - { - pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; - pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; - } - - if(pDevice->EnableTbi) - { - pDevice->LedMode = LED_MODE_THREE_LINK; - } - } - else - { - if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) - { - pDevice->LedMode = EePhyLedMode; - } - else - { - pDevice->LedMode = LED_MODE_OPEN_DRAIN; - } - } + pDevice->LedMode == LED_MODE_LINK10) + { + pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT; + pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG; + } + + if(pDevice->EnableTbi) + { + pDevice->LedMode = LED_MODE_THREE_LINK; + } + } + else + { + if(EeSigFound && EePhyLedMode != LED_MODE_AUTO) + { + pDevice->LedMode = EePhyLedMode; + } + else + { + pDevice->LedMode = LED_MODE_OPEN_DRAIN; + } + } } /* Enable OneDmaAtOnce. */ if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) { - pDevice->OneDmaAtOnce = FALSE; + pDevice->OneDmaAtOnce = FALSE; } if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B2) + pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B2) { - pDevice->WolSpeed = WOL_SPEED_10MB; + pDevice->WolSpeed = WOL_SPEED_10MB; } else { - pDevice->WolSpeed = WOL_SPEED_100MB; + pDevice->WolSpeed = WOL_SPEED_100MB; } /* Offloadings. */ @@ -1574,8 +1569,8 @@ PLM_DEVICE_BLOCK pDevice) /* Turn off task offloading on Ax. */ if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0) { - pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | - LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); + pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM | + LM_TASK_OFFLOAD_TX_UDP_CHECKSUM); } pDevice->PciState = REG_RD(pDevice, PciCfg.PciState); LM_ReadVPD(pDevice); @@ -1592,44 +1587,44 @@ LM_GetAdapterInfoBySsid( { static LM_ADAPTER_INFO AdapterArr[] = { - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, - { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, - - { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, - { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, - - { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, - { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, - - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, - { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 }, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0}, + { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0}, + + { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 }, + { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 }, + + { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 }, + + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 }, + { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 }, }; LM_UINT32 j; for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++) { - if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) - { - return &AdapterArr[j]; - } + if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) + { + return &AdapterArr[j]; + } } return NULL; @@ -1659,9 +1654,9 @@ PLM_DEVICE_BLOCK pDevice) /* Intialize the queues. */ QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container, - MAX_RX_PACKET_DESC_COUNT); + MAX_RX_PACKET_DESC_COUNT); QQ_InitQueue(&pDevice->RxPacketFreeQ.Container, - MAX_RX_PACKET_DESC_COUNT); + MAX_RX_PACKET_DESC_COUNT); QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT); QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT); @@ -1670,60 +1665,60 @@ PLM_DEVICE_BLOCK pDevice) /* Allocate shared memory for: status block, the buffers for receive */ /* rings -- standard, mini, jumbo, and return rings. */ Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) + - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + #if T3_JUMBO_RCV_RCB_ENTRY_COUNT - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) + #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); /* Memory for host based Send BD. */ if(pDevice->NicSendBd == FALSE) { - Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; } /* Allocate the memory block. */ Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } /* Program DMA Read/Write */ if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) { - pDevice->DmaReadWriteCtrl = 0x763f000f; + pDevice->DmaReadWriteCtrl = 0x763f000f; } else { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) - { - pDevice->DmaReadWriteCtrl = 0x761f0000; - } - else - { - pDevice->DmaReadWriteCtrl = 0x761b000f; - } - if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || - pDevice->ChipRevId == T3_CHIP_ID_5703_A2) - { - pDevice->OneDmaAtOnce = TRUE; - } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704) + { + pDevice->DmaReadWriteCtrl = 0x761f0000; + } + else + { + pDevice->DmaReadWriteCtrl = 0x761b000f; + } + if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 || + pDevice->ChipRevId == T3_CHIP_ID_5703_A2) + { + pDevice->OneDmaAtOnce = TRUE; + } } if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703) { - pDevice->DmaReadWriteCtrl &= 0xfffffff0; + pDevice->DmaReadWriteCtrl &= 0xfffffff0; } if(pDevice->OneDmaAtOnce) { - pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; + pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE; } REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl); if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /* Status block. */ @@ -1744,7 +1739,7 @@ PLM_DEVICE_BLOCK pDevice) pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT /* Receive jumbo BD buffer. */ @@ -1753,7 +1748,7 @@ PLM_DEVICE_BLOCK pDevice) pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ /* Receive return BD buffer. */ @@ -1762,33 +1757,33 @@ PLM_DEVICE_BLOCK pDevice) pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD); LM_INC_PHYSICAL_ADDRESS(&MemPhy, - T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); + T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD)); /* Set up Send BD. */ if(pDevice->NicSendBd == FALSE) { - pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; - pDevice->SendBdPhy = MemPhy; + pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt; + pDevice->SendBdPhy = MemPhy; - pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; - LM_INC_PHYSICAL_ADDRESS(&MemPhy, - sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); + pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT; + LM_INC_PHYSICAL_ADDRESS(&MemPhy, + sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT); } else { - pDevice->pSendBdVirt = (PT3_SND_BD) - pDevice->pMemView->uIntMem.First32k.BufferDesc; - pDevice->SendBdPhy.High = 0; - pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; + pDevice->pSendBdVirt = (PT3_SND_BD) + pDevice->pMemView->uIntMem.First32k.BufferDesc; + pDevice->SendBdPhy.High = 0; + pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR; } /* Allocate memory for packet descriptors. */ Size = (pDevice->RxPacketDescCnt + - pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; + pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE; Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } pDevice->pPacketDescBase = (PLM_VOID) pPacket; @@ -1796,54 +1791,54 @@ PLM_DEVICE_BLOCK pDevice) /* to the TxPacketFreeQ for each send ring. */ for(j = 0; j < pDevice->TxPacketDescCnt; j++) { - /* Ring index. */ - pPacket->Flags = 0; + /* Ring index. */ + pPacket->Flags = 0; - /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ - QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); + /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */ + QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); } /* for(j.. */ /* Create receive packet descriptors from the memory block and add them */ /* to the RxPacketFreeQ. Create the Standard packet descriptors. */ for(j = 0; j < pDevice->RxStdDescCnt; j++) { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING; - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE; - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); } /* for */ #if T3_JUMBO_RCV_RCB_ENTRY_COUNT /* Create the Jumbo packet descriptors. */ for(j = 0; j < pDevice->RxJumboDescCnt; j++) { - /* Receive producer ring. */ - pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; + /* Receive producer ring. */ + pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING; - /* Receive buffer size. */ - pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; + /* Receive buffer size. */ + pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize; - /* Add the descriptor to RxPacketFreeQ. */ - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + /* Add the descriptor to RxPacketFreeQ. */ + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ - /* is the total size of the packet descriptor including the */ - /* os-specific extensions in the UM_PACKET structure. */ - pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); + /* Get the pointer to the next descriptor. MM_PACKET_DESC_SIZE */ + /* is the total size of the packet descriptor including the */ + /* os-specific extensions in the UM_PACKET structure. */ + pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE); } /* for */ #endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */ @@ -1851,12 +1846,12 @@ PLM_DEVICE_BLOCK pDevice) Status = MM_InitializeUmPackets(pDevice); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } /* if */ /* Default receive mask. */ pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST | - LM_ACCEPT_UNICAST; + LM_ACCEPT_UNICAST; /* Make sure we are in the first 32k memory window or NicSendBd. */ REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0); @@ -1865,7 +1860,7 @@ PLM_DEVICE_BLOCK pDevice) Status = LM_ResetAdapter(pDevice); if(Status != LM_STATUS_SUCCESS) { - return Status; + return Status; } /* We are done with initialization. */ @@ -1875,7 +1870,6 @@ PLM_DEVICE_BLOCK pDevice) } /* LM_InitializeAdapter */ - /******************************************************************************/ /* Description: */ /* This function Enables/Disables a given block. */ @@ -1896,399 +1890,399 @@ LM_UINT32 mask,LM_UINT32 cntrl) for(i = 0 ; i < 32; i++) { - if(!(mask & (1 << i))) - continue; - - switch (1 << i) - { - case T3_BLOCK_DMA_RD: - data = REG_RD(pDevice, DmaRead.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_READ_MODE_ENABLE; - REG_WR(pDevice, DmaRead.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); - break; - - case T3_BLOCK_DMA_COMP: - data = REG_RD(pDevice,DmaComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_COMP_MODE_ENABLE; - REG_WR(pDevice, DmaComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); - break; - - case T3_BLOCK_RX_BD_INITIATOR: - data = REG_RD(pDevice, RcvBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); - break; - - case T3_BLOCK_RX_BD_COMP: - data = REG_RD(pDevice, RcvBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvBdComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); - break; - - case T3_BLOCK_DMA_WR: - data = REG_RD(pDevice, DmaWrite.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~DMA_WRITE_MODE_ENABLE; - REG_WR(pDevice, DmaWrite.Mode,data); - - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); - break; - - case T3_BLOCK_MSI_HANDLER: - data = REG_RD(pDevice, Msi.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MSI_MODE_ENABLE; - REG_WR(pDevice, Msi.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); - break; - - case T3_BLOCK_RX_LIST_PLMT: - data = REG_RD(pDevice, RcvListPlmt.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_PLMT_MODE_ENABLE; - REG_WR(pDevice, RcvListPlmt.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); - break; - - case T3_BLOCK_RX_LIST_SELECTOR: - data = REG_RD(pDevice, RcvListSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_LIST_SEL_MODE_ENABLE; - REG_WR(pDevice, RcvListSel.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); - break; - - case T3_BLOCK_RX_DATA_INITIATOR: - data = REG_RD(pDevice, RcvDataBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_BD_IN_MODE_ENABLE; - REG_WR(pDevice, RcvDataBdIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); - break; - - case T3_BLOCK_RX_DATA_COMP: - data = REG_RD(pDevice, RcvDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~RCV_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, RcvDataComp.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); - break; - - case T3_BLOCK_HOST_COALESING: - data = REG_RD(pDevice, HostCoalesce.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~HOST_COALESCE_ENABLE; - REG_WR(pDevice, HostCoalesce.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); - break; - - case T3_BLOCK_MAC_RX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->RxMode &= ~RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) - { - break; - } - MM_Wait(10); - } - } - else - { - pDevice->RxMode |= RX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - } - break; - - case T3_BLOCK_MBUF_CLUSTER_FREE: - data = REG_RD(pDevice, MbufClusterFree.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; - REG_WR(pDevice, MbufClusterFree.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); - break; - - case T3_BLOCK_SEND_BD_INITIATOR: - data = REG_RD(pDevice, SndBdIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_IN_MODE_ENABLE; - REG_WR(pDevice, SndBdIn.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); - break; - - case T3_BLOCK_SEND_BD_COMP: - data = REG_RD(pDevice, SndBdComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_COMP_MODE_ENABLE; - REG_WR(pDevice, SndBdComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); - break; - - case T3_BLOCK_SEND_BD_SELECTOR: - data = REG_RD(pDevice, SndBdSel.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_BD_SEL_MODE_ENABLE; - REG_WR(pDevice, SndBdSel.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); - break; - - case T3_BLOCK_SEND_DATA_INITIATOR: - data = REG_RD(pDevice, SndDataIn.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_SND_DATA_IN_MODE_ENABLE; - REG_WR(pDevice, SndDataIn.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); - break; - - case T3_BLOCK_SEND_DATA_COMP: - data = REG_RD(pDevice, SndDataComp.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~SND_DATA_COMP_MODE_ENABLE; - REG_WR(pDevice, SndDataComp.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); - break; - - case T3_BLOCK_MAC_TX_ENGINE: - if(cntrl == LM_DISABLE) - { - pDevice->TxMode &= ~TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - { - pDevice->TxMode |= TX_MODE_ENABLE; - REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); - } - break; - - case T3_BLOCK_MEM_ARBITOR: - data = REG_RD(pDevice, MemArbiter.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~T3_MEM_ARBITER_MODE_ENABLE; - REG_WR(pDevice, MemArbiter.Mode, data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); - break; - - case T3_BLOCK_MBUF_MANAGER: - data = REG_RD(pDevice, BufMgr.Mode); - if (cntrl == LM_DISABLE) - { - data &= ~BUFMGR_MODE_ENABLE; - REG_WR(pDevice, BufMgr.Mode,data); - for(j = 0; j < MaxWaitCnt; j++) - { - if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) - break; - MM_Wait(10); - } - } - else - REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); - break; - - case T3_BLOCK_MAC_GLOBAL: - if(cntrl == LM_DISABLE) - { - pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - else - { - pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | - MAC_MODE_ENABLE_FHDE); - } - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - break; - - default: - return LM_STATUS_FAILURE; - } /* switch */ - - if(j >= MaxWaitCnt) - { - return LM_STATUS_FAILURE; - } + if(!(mask & (1 << i))) + continue; + + switch (1 << i) + { + case T3_BLOCK_DMA_RD: + data = REG_RD(pDevice, DmaRead.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_READ_MODE_ENABLE; + REG_WR(pDevice, DmaRead.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_COMP: + data = REG_RD(pDevice,DmaComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_COMP_MODE_ENABLE; + REG_WR(pDevice, DmaComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_INITIATOR: + data = REG_RD(pDevice, RcvBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_BD_COMP: + data = REG_RD(pDevice, RcvBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvBdComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_DMA_WR: + data = REG_RD(pDevice, DmaWrite.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~DMA_WRITE_MODE_ENABLE; + REG_WR(pDevice, DmaWrite.Mode,data); + + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE); + break; + + case T3_BLOCK_MSI_HANDLER: + data = REG_RD(pDevice, Msi.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MSI_MODE_ENABLE; + REG_WR(pDevice, Msi.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_PLMT: + data = REG_RD(pDevice, RcvListPlmt.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_PLMT_MODE_ENABLE; + REG_WR(pDevice, RcvListPlmt.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE); + break; + + case T3_BLOCK_RX_LIST_SELECTOR: + data = REG_RD(pDevice, RcvListSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_LIST_SEL_MODE_ENABLE; + REG_WR(pDevice, RcvListSel.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_INITIATOR: + data = REG_RD(pDevice, RcvDataBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_BD_IN_MODE_ENABLE; + REG_WR(pDevice, RcvDataBdIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_RX_DATA_COMP: + data = REG_RD(pDevice, RcvDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~RCV_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, RcvDataComp.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_HOST_COALESING: + data = REG_RD(pDevice, HostCoalesce.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~HOST_COALESCE_ENABLE; + REG_WR(pDevice, HostCoalesce.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE); + break; + + case T3_BLOCK_MAC_RX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->RxMode &= ~RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE)) + { + break; + } + MM_Wait(10); + } + } + else + { + pDevice->RxMode |= RX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + } + break; + + case T3_BLOCK_MBUF_CLUSTER_FREE: + data = REG_RD(pDevice, MbufClusterFree.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE; + REG_WR(pDevice, MbufClusterFree.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_INITIATOR: + data = REG_RD(pDevice, SndBdIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_IN_MODE_ENABLE; + REG_WR(pDevice, SndBdIn.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdIn.Mode, data | SND_BD_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_COMP: + data = REG_RD(pDevice, SndBdComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_COMP_MODE_ENABLE; + REG_WR(pDevice, SndBdComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_BD_SELECTOR: + data = REG_RD(pDevice, SndBdSel.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_BD_SEL_MODE_ENABLE; + REG_WR(pDevice, SndBdSel.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_INITIATOR: + data = REG_RD(pDevice, SndDataIn.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_SND_DATA_IN_MODE_ENABLE; + REG_WR(pDevice, SndDataIn.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE); + break; + + case T3_BLOCK_SEND_DATA_COMP: + data = REG_RD(pDevice, SndDataComp.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~SND_DATA_COMP_MODE_ENABLE; + REG_WR(pDevice, SndDataComp.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_TX_ENGINE: + if(cntrl == LM_DISABLE) + { + pDevice->TxMode &= ~TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + { + pDevice->TxMode |= TX_MODE_ENABLE; + REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); + } + break; + + case T3_BLOCK_MEM_ARBITOR: + data = REG_RD(pDevice, MemArbiter.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~T3_MEM_ARBITER_MODE_ENABLE; + REG_WR(pDevice, MemArbiter.Mode, data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE); + break; + + case T3_BLOCK_MBUF_MANAGER: + data = REG_RD(pDevice, BufMgr.Mode); + if (cntrl == LM_DISABLE) + { + data &= ~BUFMGR_MODE_ENABLE; + REG_WR(pDevice, BufMgr.Mode,data); + for(j = 0; j < MaxWaitCnt; j++) + { + if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)) + break; + MM_Wait(10); + } + } + else + REG_WR(pDevice, BufMgr.Mode,data | BUFMGR_MODE_ENABLE); + break; + + case T3_BLOCK_MAC_GLOBAL: + if(cntrl == LM_DISABLE) + { + pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + else + { + pDevice->MacMode |= (MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | + MAC_MODE_ENABLE_FHDE); + } + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + break; + + default: + return LM_STATUS_FAILURE; + } /* switch */ + + if(j >= MaxWaitCnt) + { + return LM_STATUS_FAILURE; + } } return LM_STATUS_SUCCESS; @@ -2318,7 +2312,7 @@ PLM_DEVICE_BLOCK pDevice) /* Disable transmit and receive DMA engines. Abort all pending requests. */ if(pDevice->InitDone) { - LM_Abort(pDevice); + LM_Abort(pDevice); } pDevice->ShuttingDown = FALSE; @@ -2329,36 +2323,36 @@ PLM_DEVICE_BLOCK pDevice) /* in other chip revisions. */ if(pDevice->DelayPciGrant) { - Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); - REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); + Value32 = REG_RD(pDevice, PciCfg.ClockCtrl); + REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31); } if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; - REG_WR(pDevice, PciCfg.PciState, Value32); - } + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + REG_WR(pDevice, PciCfg.PciState, Value32); + } } /* Enable TaggedStatus mode. */ if(pDevice->UseTaggedStatus) { - pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; + pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE; } /* Restore PCI configuration registers. */ MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); + pDevice->SavedCacheLineReg); MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); /* Clear the statistics block. */ for(j = 0x0300; j < 0x0b00; j++) { - MEM_WR_OFFSET(pDevice, j, 0); + MEM_WR_OFFSET(pDevice, j, 0); } /* Initialize the statistis Block */ @@ -2383,8 +2377,8 @@ PLM_DEVICE_BLOCK pDevice) /* Receive jumbo BD buffer. */ for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) { - pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; - pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.High = 0; + pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0; } #endif @@ -2393,46 +2387,46 @@ PLM_DEVICE_BLOCK pDevice) /* GRC mode control register. */ #ifdef BIG_ENDIAN_PCI /* Jimmy, this ifdef block deleted in new code! */ Value32 = - GRC_MODE_WORD_SWAP_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; + GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; #else /* No CPU Swap modes for PCI IO */ Value32 = #ifdef BIG_ENDIAN_HOST - GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | #else - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA | + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA | #endif - GRC_MODE_INT_ON_MAC_ATTN | - GRC_MODE_HOST_STACK_UP; + GRC_MODE_INT_ON_MAC_ATTN | + GRC_MODE_HOST_STACK_UP; #endif /* !BIG_ENDIAN_PCI */ /* Configure send BD mode. */ if(pDevice->NicSendBd == FALSE) { - Value32 |= GRC_MODE_HOST_SEND_BDS; + Value32 |= GRC_MODE_HOST_SEND_BDS; } else { - Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; + Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS; } /* Configure pseudo checksum mode. */ if(pDevice->NoTxPseudoHdrChksum) { - Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; + Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM; } if(pDevice->NoRxPseudoHdrChksum) { - Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; + Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM; } REG_WR(pDevice, Grc.Mode, Value32); @@ -2452,60 +2446,60 @@ PLM_DEVICE_BLOCK pDevice) /* Configure the DMA read MBUF low water mark. */ if(pDevice->DmaMbufLowMark) { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - pDevice->DmaMbufLowMark); + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + pDevice->DmaMbufLowMark); } else { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK); - } - else - { - REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, - T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); - } + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark, + T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO); + } } /* Configure the MAC Rx MBUF low water mark. */ if(pDevice->RxMacMbufLowMark) { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - pDevice->RxMacMbufLowMark); + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + pDevice->RxMacMbufLowMark); } else { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK); - } - else - { - REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, - T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); - } + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark, + T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO); + } } /* Configure the MBUF high water mark. */ if(pDevice->MbufHighMark) { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); + REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark); } else { - if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK); - } - else - { - REG_WR(pDevice, BufMgr.MbufHighWaterMark, - T3_DEF_MBUF_HIGH_WMARK_JUMBO); - } + if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK); + } + else + { + REG_WR(pDevice, BufMgr.MbufHighWaterMark, + T3_DEF_MBUF_HIGH_WMARK_JUMBO); + } } REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK); @@ -2516,14 +2510,14 @@ PLM_DEVICE_BLOCK pDevice) for(j = 0 ;j < 2000; j++) { - if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) - break; - MM_Wait(10); + if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE) + break; + MM_Wait(10); } if(j >= 2000) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /* Enable the FTQs. */ @@ -2533,32 +2527,32 @@ PLM_DEVICE_BLOCK pDevice) /* Wait until FTQ is ready */ for(j = 0; j < 2000; j++) { - if(REG_RD(pDevice, Ftq.Reset) == 0) - break; - MM_Wait(10); + if(REG_RD(pDevice, Ftq.Reset) == 0) + break; + MM_Wait(10); } if(j >= 2000) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /* Initialize the Standard Receive RCB. */ REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High, - pDevice->RxStdBdPhy.High); + pDevice->RxStdBdPhy.High); REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low, - pDevice->RxStdBdPhy.Low); + pDevice->RxStdBdPhy.Low); REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags, - MAX_STD_RCV_BUFFER_SIZE << 16); + MAX_STD_RCV_BUFFER_SIZE << 16); /* Initialize the Jumbo Receive RCB. */ REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); + T3_RCB_FLAG_RING_DISABLED); #if T3_JUMBO_RCV_RCB_ENTRY_COUNT REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High, - pDevice->RxJumboBdPhy.High); + pDevice->RxJumboBdPhy.High); REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low, - pDevice->RxJumboBdPhy.Low); + pDevice->RxJumboBdPhy.Low); REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0); @@ -2566,13 +2560,13 @@ PLM_DEVICE_BLOCK pDevice) /* Initialize the Mini Receive RCB. */ REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags, - T3_RCB_FLAG_RING_DISABLED); + T3_RCB_FLAG_RING_DISABLED); { - REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); - REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, - (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); + REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR); + REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr, + (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR); } /* Receive BD Ring replenish threshold. */ @@ -2583,7 +2577,7 @@ PLM_DEVICE_BLOCK pDevice) /* Disable all the unused rings. */ for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) { - MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); } /* for */ /* Initialize the indices. */ @@ -2596,54 +2590,54 @@ PLM_DEVICE_BLOCK pDevice) /* Set up host or NIC based send RCB. */ if(pDevice->NicSendBd == FALSE) { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, - pDevice->SendBdPhy.High); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, - pDevice->SendBdPhy.Low); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, + pDevice->SendBdPhy.High); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, + pDevice->SendBdPhy.Low); - /* Set up the NIC ring address in the RCB. */ - MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); + /* Set up the NIC ring address in the RCB. */ + MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR); - /* Setup the RCB. */ - MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, - T3_SEND_RCB_ENTRY_COUNT << 16); + /* Setup the RCB. */ + MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags, + T3_SEND_RCB_ENTRY_COUNT << 16); - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - pDevice->pSendBdVirt[k].HostAddr.High = 0; - pDevice->pSendBdVirt[k].HostAddr.Low = 0; - } + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + pDevice->pSendBdVirt[k].HostAddr.High = 0; + pDevice->pSendBdVirt[k].HostAddr.Low = 0; + } } else { - MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); - MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); - MEM_WR(pDevice, SendRcb[0].NicRingAddr, - pDevice->SendBdPhy.Low); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0); + MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0); + MEM_WR(pDevice, SendRcb[0].NicRingAddr, + pDevice->SendBdPhy.Low); - for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) - { - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); - __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); - pDevice->ShadowSendBd[k].HostAddr.High = 0; - pDevice->ShadowSendBd[k].u1.Len_Flags = 0; - } + for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) + { + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low)); + __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags)); + pDevice->ShadowSendBd[k].HostAddr.High = 0; + pDevice->ShadowSendBd[k].u1.Len_Flags = 0; + } } atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1); /* Configure the receive return rings. */ for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) { - MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); + MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED); } pDevice->RcvRetConIdx = 0; MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High, - pDevice->RcvRetBdPhy.High); + pDevice->RcvRetBdPhy.High); MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low, - pDevice->RcvRetBdPhy.Low); + pDevice->RcvRetBdPhy.Low); /* Set up the NIC ring address in the RCB. */ /* Not very clear from the spec. I am guessing that for Receive */ @@ -2652,7 +2646,7 @@ PLM_DEVICE_BLOCK pDevice) /* Setup the RCB. */ MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags, - T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); + T3_RCV_RETURN_RCB_ENTRY_COUNT << 16); /* Reinitialize RX ring producer index */ MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0); @@ -2677,9 +2671,9 @@ PLM_DEVICE_BLOCK pDevice) /* Initialize the transmit random backoff seed. */ Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] + - pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + - pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & - MAC_TX_BACKOFF_SEED_MASK; + pDevice->NodeAddress[2] + pDevice->NodeAddress[3] + + pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) & + MAC_TX_BACKOFF_SEED_MASK; REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32); /* Receive MTU. Frames larger than the MTU is marked as oversized. */ @@ -2708,88 +2702,88 @@ PLM_DEVICE_BLOCK pDevice) /* Enable Send Data Initator Statistics */ REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff); REG_WR(pDevice, SndDataIn.StatsCtrl, - T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ - T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); + T3_SND_DATA_IN_STATS_CTRL_ENABLE | \ + T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE); /* Disable the host coalescing state machine before configuring it's */ /* parameters. */ REG_WR(pDevice, HostCoalesce.Mode, 0); for(j = 0; j < 2000; j++) { - Value32 = REG_RD(pDevice, HostCoalesce.Mode); - if(!(Value32 & HOST_COALESCE_ENABLE)) - { - break; - } - MM_Wait(10); + Value32 = REG_RD(pDevice, HostCoalesce.Mode); + if(!(Value32 & HOST_COALESCE_ENABLE)) + { + break; + } + MM_Wait(10); } /* Host coalescing configurations. */ REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks); REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks); REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames, - pDevice->RxMaxCoalescedFrames); + pDevice->RxMaxCoalescedFrames); REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames, - pDevice->TxMaxCoalescedFrames); + pDevice->TxMaxCoalescedFrames); REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt, - pDevice->RxCoalescingTicksDuringInt); + pDevice->RxCoalescingTicksDuringInt); REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt, - pDevice->TxCoalescingTicksDuringInt); + pDevice->TxCoalescingTicksDuringInt); REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt, - pDevice->RxMaxCoalescedFramesDuringInt); + pDevice->RxMaxCoalescedFramesDuringInt); REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt, - pDevice->TxMaxCoalescedFramesDuringInt); + pDevice->TxMaxCoalescedFramesDuringInt); /* Initialize the address of the status block. The NIC will DMA */ /* the status block to this memory which resides on the host. */ REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High, - pDevice->StatusBlkPhy.High); + pDevice->StatusBlkPhy.High); REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low, - pDevice->StatusBlkPhy.Low); + pDevice->StatusBlkPhy.Low); /* Initialize the address of the statistics block. The NIC will DMA */ /* the statistics to this block of memory. */ REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High, - pDevice->StatsBlkPhy.High); + pDevice->StatsBlkPhy.High); REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low, - pDevice->StatsBlkPhy.Low); + pDevice->StatsBlkPhy.Low); REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks, - pDevice->StatsCoalescingTicks); + pDevice->StatsCoalescingTicks); REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300); REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00); /* Enable Host Coalesing state machine */ REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE | - pDevice->CoalesceMode); + pDevice->CoalesceMode); /* Enable the Receive BD Completion state machine. */ REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE | - RCV_BD_COMP_MODE_ATTN_ENABLE); + RCV_BD_COMP_MODE_ATTN_ENABLE); /* Enable the Receive List Placement state machine. */ REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE); /* Enable the Receive List Selector state machine. */ REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE | - RCV_LIST_SEL_MODE_ATTN_ENABLE); + RCV_LIST_SEL_MODE_ATTN_ENABLE); /* Enable transmit DMA, clear statistics. */ pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS | - MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | - MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; + MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE | + MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE; REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); + MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS); /* GRC miscellaneous local control register. */ pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN | - GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; + GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM; if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; + pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1; } REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); @@ -2798,13 +2792,13 @@ PLM_DEVICE_BLOCK pDevice) /* Reset RX counters. */ for(j = 0; j < sizeof(LM_RX_COUNTERS); j++) { - ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; + ((PLM_UINT8) &pDevice->RxCounters)[j] = 0; } /* Reset TX counters. */ for(j = 0; j < sizeof(LM_TX_COUNTERS); j++) { - ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; + ((PLM_UINT8) &pDevice->TxCounters)[j] = 0; } MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); @@ -2814,53 +2808,53 @@ PLM_DEVICE_BLOCK pDevice) /* Enable the DMA Write state machine. */ Value32 = DMA_WRITE_MODE_ENABLE | - DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; + DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE; REG_WR(pDevice, DmaWrite.Mode, Value32); if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) { - if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) - { - Value16 = REG_RD(pDevice, PciCfg.PciXCommand); - Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); - Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & - PCIX_CMD_MAX_BURST_MASK); - if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) - { - Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) - & PCIX_CMD_MAX_SPLIT_MASK; - } - REG_WR(pDevice, PciCfg.PciXCommand, Value16); - } + if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) + { + Value16 = REG_RD(pDevice, PciCfg.PciXCommand); + Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK); + Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) & + PCIX_CMD_MAX_BURST_MASK); + if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) + { + Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL) + & PCIX_CMD_MAX_SPLIT_MASK; + } + REG_WR(pDevice, PciCfg.PciXCommand, Value16); + } } /* Enable the Read DMA state machine. */ Value32 = DMA_READ_MODE_ENABLE | - DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | - DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | - DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | - DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | - DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | - DMA_READ_MODE_LONG_READ_ATTN_ENABLE; + DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE | + DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE | + DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE | + DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE | + DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE | + DMA_READ_MODE_LONG_READ_ATTN_ENABLE; if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) { - Value32 |= DMA_READ_MODE_SPLIT_ENABLE; + Value32 |= DMA_READ_MODE_SPLIT_ENABLE; } REG_WR(pDevice, DmaRead.Mode, Value32); /* Enable the Receive Data Completion state machine. */ REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE | - RCV_DATA_COMP_MODE_ATTN_ENABLE); + RCV_DATA_COMP_MODE_ATTN_ENABLE); /* Enable the Mbuf Cluster Free state machine. */ REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE); @@ -2870,32 +2864,32 @@ PLM_DEVICE_BLOCK pDevice) /* Enable the Send BD Completion state machine. */ REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE | - SND_BD_COMP_MODE_ATTN_ENABLE); + SND_BD_COMP_MODE_ATTN_ENABLE); /* Enable the Receive BD Initiator state machine. */ REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE | - RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); + RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE); /* Enable the Receive Data and Receive BD Initiator state machine. */ REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE | - RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); + RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE); /* Enable the Send Data Initiator state machine. */ REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE); /* Enable the Send BD Initiator state machine. */ REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE | - SND_BD_IN_MODE_ATTN_ENABLE); + SND_BD_IN_MODE_ATTN_ENABLE); /* Enable the Send BD Selector state machine. */ REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE | - SND_BD_SEL_MODE_ATTN_ENABLE); + SND_BD_SEL_MODE_ATTN_ENABLE); #if INCLUDE_5701_AX_FIX /* Load the firmware for the 5701_A0 workaround. */ if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0) { - LM_LoadRlsFirmware(pDevice); + LM_LoadRlsFirmware(pDevice); } #endif @@ -2909,9 +2903,9 @@ PLM_DEVICE_BLOCK pDevice) if (pDevice->RestoreOnWakeUp) { - pDevice->RestoreOnWakeUp = FALSE; - pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; - pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; + pDevice->RestoreOnWakeUp = FALSE; + pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg; + pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType; } /* Disable auto polling. */ @@ -2919,20 +2913,20 @@ PLM_DEVICE_BLOCK pDevice) REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) { - Value32 = LED_CTRL_PHY_MODE_1; + Value32 = LED_CTRL_PHY_MODE_1; } else { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } } REG_WR(pDevice, MacCtrl.LedCtrl, Value32); @@ -2941,22 +2935,22 @@ PLM_DEVICE_BLOCK pDevice) if (pDevice->EnableTbi) { - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); - MM_Wait(10); - REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); - if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) - { - REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); - } + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET); + MM_Wait(10); + REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); + if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) + { + REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000); + } } /* Setup the phy chip. */ LM_SetupPhy(pDevice); if (!pDevice->EnableTbi) { - /* Clear CRC stats */ - LM_ReadPhy(pDevice, 0x1e, &Value32); - LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); - LM_ReadPhy(pDevice, 0x14, &Value32); + /* Clear CRC stats */ + LM_ReadPhy(pDevice, 0x1e, &Value32); + LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000); + LM_ReadPhy(pDevice, 0x14, &Value32); } /* Set up the receive mask. */ @@ -2965,13 +2959,13 @@ PLM_DEVICE_BLOCK pDevice) /* Queue Rx packet buffers. */ if(pDevice->QueueRxPackets) { - LM_QueueRxPackets(pDevice); + LM_QueueRxPackets(pDevice); } /* Enable interrupt to the host. */ if(pDevice->InitDone) { - LM_EnableInterrupt(pDevice); + LM_EnableInterrupt(pDevice); } return LM_STATUS_SUCCESS; @@ -2990,14 +2984,13 @@ LM_DisableInterrupt( PLM_DEVICE_BLOCK pDevice) { REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl | - MISC_HOST_CTRL_MASK_PCI_INT); + MISC_HOST_CTRL_MASK_PCI_INT); MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1); return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine enables the adapter to generate interrupts. */ @@ -3010,20 +3003,19 @@ LM_EnableInterrupt( PLM_DEVICE_BLOCK pDevice) { REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl & - ~MISC_HOST_CTRL_MASK_PCI_INT); + ~MISC_HOST_CTRL_MASK_PCI_INT); MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0); if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) { - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_SET_INT); + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_SET_INT); } return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* This routine puts a packet on the wire if there is a transmit DMA */ @@ -3045,7 +3037,7 @@ LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) LM_UINT32 Idx; if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - return LM_5700SendPacket(pDevice, pPacket); + return LM_5700SendPacket(pDevice, pPacket); } /* Update the SendBdLeft count. */ @@ -3059,103 +3051,103 @@ LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) /* Next producer index. */ if (pDevice->NicSendBd == TRUE) { - T3_64BIT_HOST_ADDR paddr; - - pShadowSendBd = &pDevice->ShadowSendBd[Idx]; - for(FragCount = 0; ; ) - { - MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); - /* Initialize the pointer to the send buffer fragment. */ - if (paddr.High != pShadowSendBd->HostAddr.High) - { - __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = paddr.High; - } - __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); - - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; - - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - Value32 |= SND_BD_FLAG_END; - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - break; - } - else - { - if (Value32 != pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { - __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); - } - } - - pSendBd++; - pShadowSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - pShadowSendBd = &pDevice->ShadowSendBd[0]; - } - } /* for */ - - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); - - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + T3_64BIT_HOST_ADDR paddr; + + pShadowSendBd = &pDevice->ShadowSendBd[Idx]; + for(FragCount = 0; ; ) + { + MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount); + /* Initialize the pointer to the send buffer fragment. */ + if (paddr.High != pShadowSendBd->HostAddr.High) + { + __raw_writel(paddr.High, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = paddr.High; + } + __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low)); + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + Value32 |= SND_BD_FLAG_END; + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + break; + } + else + { + if (Value32 != pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) { + __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag)); + } + } + + pSendBd++; + pShadowSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + pShadowSendBd = &pDevice->ShadowSendBd[0]; + } + } /* for */ + + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); } else { - for(FragCount = 0; ; ) - { - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + for(FragCount = 0; ; ) + { + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); - pSendBd->u2.VlanTag = pPacket->VlanTag; + pSendBd->u2.VlanTag = pPacket->VlanTag; - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ - /* Put the packet descriptor in the ActiveQ. */ - QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); + /* Put the packet descriptor in the ActiveQ. */ + QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); } @@ -3176,121 +3168,121 @@ LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket) while (1) { - /* Initalize the send buffer descriptors. */ - StartIdx = Idx = pDevice->SendProdIdx; - - if (pDevice->NicSendBd) - { - pTmpSendBd = pSendBd = &NicSendBdArr[0]; - } - else - { - pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; - } - - /* Next producer index. */ - for(FragCount = 0; ; ) - { - LM_UINT32 Value32, Len; - - /* Initialize the pointer to the send buffer fragment. */ - MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); - - pSendBd->u2.VlanTag = pPacket->VlanTag; - - /* Setup the control flags and send buffer size. */ - Value32 = (Len << 16) | pPacket->Flags; - - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; - break; - } - else - { - pSendBd->u1.Len_Flags = Value32; - } - pSendBd++; - if ((Idx == 0) && !pDevice->NicSendBd) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } /* for */ - if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == - LM_STATUS_SUCCESS) - { - if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) - { - QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); - return LM_STATUS_FAILURE; - } - continue; - } - } - break; + /* Initalize the send buffer descriptors. */ + StartIdx = Idx = pDevice->SendProdIdx; + + if (pDevice->NicSendBd) + { + pTmpSendBd = pSendBd = &NicSendBdArr[0]; + } + else + { + pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx]; + } + + /* Next producer index. */ + for(FragCount = 0; ; ) + { + LM_UINT32 Value32, Len; + + /* Initialize the pointer to the send buffer fragment. */ + MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount); + + pSendBd->u2.VlanTag = pPacket->VlanTag; + + /* Setup the control flags and send buffer size. */ + Value32 = (Len << 16) | pPacket->Flags; + + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END; + break; + } + else + { + pSendBd->u1.Len_Flags = Value32; + } + pSendBd++; + if ((Idx == 0) && !pDevice->NicSendBd) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } /* for */ + if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) == + LM_STATUS_SUCCESS) + { + if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS) + { + QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket); + return LM_STATUS_FAILURE; + } + continue; + } + } + break; } /* Put the packet descriptor in the ActiveQ. */ QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket); if (pDevice->NicSendBd) { - pSendBd = &pDevice->pSendBdVirt[StartIdx]; - pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; - - while (StartIdx != Idx) - { - LM_UINT32 Value32; - - if ((Value32 = pTmpSendBd->HostAddr.High) != - pShadowSendBd->HostAddr.High) - { - __raw_writel(Value32, &(pSendBd->HostAddr.High)); - pShadowSendBd->HostAddr.High = Value32; - } - - __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); - - if ((Value32 = pTmpSendBd->u1.Len_Flags) != - pShadowSendBd->u1.Len_Flags) - { - __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); - pShadowSendBd->u1.Len_Flags = Value32; - } - - if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) - { - __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); - } - - StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (StartIdx == 0) - pSendBd = &pDevice->pSendBdVirt[0]; - else - pSendBd++; - pTmpSendBd++; - } - wmb(); - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); - } + pSendBd = &pDevice->pSendBdVirt[StartIdx]; + pShadowSendBd = &pDevice->ShadowSendBd[StartIdx]; + + while (StartIdx != Idx) + { + LM_UINT32 Value32; + + if ((Value32 = pTmpSendBd->HostAddr.High) != + pShadowSendBd->HostAddr.High) + { + __raw_writel(Value32, &(pSendBd->HostAddr.High)); + pShadowSendBd->HostAddr.High = Value32; + } + + __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low)); + + if ((Value32 = pTmpSendBd->u1.Len_Flags) != + pShadowSendBd->u1.Len_Flags) + { + __raw_writel(Value32, &(pSendBd->u1.Len_Flags)); + pShadowSendBd->u1.Len_Flags = Value32; + } + + if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) + { + __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag)); + } + + StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (StartIdx == 0) + pSendBd = &pDevice->pSendBdVirt[0]; + else + pSendBd++; + pTmpSendBd++; + } + wmb(); + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx); + } } else { - wmb(); - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + wmb(); + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); - if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) - { - MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); - } + if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) + { + MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx); + } } /* Update the SendBdLeft count. */ @@ -3312,27 +3304,27 @@ LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket, Idx = pDevice->SendProdIdx; for(FragCount = 0; ; ) { - Len = pSendBd->u1.Len_Flags >> 16; - if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && - (pSendBd->HostAddr.High == 0) && - ((Base + 8 + Len) < Base)) - { - return LM_STATUS_SUCCESS; - } - FragCount++; - if (FragCount >= pPacket->u.Tx.FragCount) - { - break; - } - pSendBd++; - if (!pDevice->NicSendBd) - { - Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; - if (Idx == 0) - { - pSendBd = &pDevice->pSendBdVirt[0]; - } - } + Len = pSendBd->u1.Len_Flags >> 16; + if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) && + (pSendBd->HostAddr.High == 0) && + ((Base + 8 + Len) < Base)) + { + return LM_STATUS_SUCCESS; + } + FragCount++; + if (FragCount >= pPacket->u.Tx.FragCount) + { + break; + } + pSendBd++; + if (!pDevice->NicSendBd) + { + Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK; + if (Idx == 0) + { + pSendBd = &pDevice->pSendBdVirt[0]; + } + } } return LM_STATUS_FAILURE; } @@ -3354,26 +3346,25 @@ unsigned long BufferSize) { for(j = 0; j < BufferSize; j++) { - Reg ^= pBuffer[j]; + Reg ^= pBuffer[j]; - for(k = 0; k < 8; k++) - { - Tmp = Reg & 0x01; + for(k = 0; k < 8; k++) + { + Tmp = Reg & 0x01; - Reg >>= 1; + Reg >>= 1; - if(Tmp) - { - Reg ^= 0xedb88320; - } - } + if(Tmp) + { + Reg ^= 0xedb88320; + } + } } return ~Reg; } /* ComputeCrc32 */ - /******************************************************************************/ /* Description: */ /* This routine sets the receive control register according to ReceiveMask */ @@ -3395,42 +3386,42 @@ LM_UINT32 Mask) { if(Mask & LM_ACCEPT_UNICAST) { - Mask &= ~LM_ACCEPT_UNICAST; + Mask &= ~LM_ACCEPT_UNICAST; } if(Mask & LM_ACCEPT_MULTICAST) { - Mask &= ~LM_ACCEPT_MULTICAST; + Mask &= ~LM_ACCEPT_MULTICAST; } if(Mask & LM_ACCEPT_ALL_MULTICAST) { - Mask &= ~LM_ACCEPT_ALL_MULTICAST; + Mask &= ~LM_ACCEPT_ALL_MULTICAST; } if(Mask & LM_ACCEPT_BROADCAST) { - Mask &= ~LM_ACCEPT_BROADCAST; + Mask &= ~LM_ACCEPT_BROADCAST; } RxMode &= ~RX_MODE_PROMISCUOUS_MODE; if(Mask & LM_PROMISCUOUS_MODE) { - RxMode |= RX_MODE_PROMISCUOUS_MODE; - Mask &= ~LM_PROMISCUOUS_MODE; + RxMode |= RX_MODE_PROMISCUOUS_MODE; + Mask &= ~LM_PROMISCUOUS_MODE; } RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED); if(Mask & LM_ACCEPT_ERROR_PACKET) { - RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; - Mask &= ~LM_ACCEPT_ERROR_PACKET; + RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED; + Mask &= ~LM_ACCEPT_ERROR_PACKET; } /* Make sure all the bits are valid before committing changes. */ if(Mask) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } /* Commit the new filter. */ @@ -3442,90 +3433,89 @@ LM_UINT32 Mask) { /* Set up the MC hash table. */ if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST) { - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); - } + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff); + } } else if(ReceiveMask & LM_ACCEPT_MULTICAST) { - LM_UINT32 HashReg[4]; + LM_UINT32 HashReg[4]; - HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; - for(j = 0; j < pDevice->McEntryCount; j++) - { - LM_UINT32 RegIndex; - LM_UINT32 Bitpos; - LM_UINT32 Crc32; + HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0; + for(j = 0; j < pDevice->McEntryCount; j++) + { + LM_UINT32 RegIndex; + LM_UINT32 Bitpos; + LM_UINT32 Crc32; - Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); + Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE); - /* The most significant 7 bits of the CRC32 (no inversion), */ - /* are used to index into one of the possible 128 bit positions. */ - Bitpos = ~Crc32 & 0x7f; + /* The most significant 7 bits of the CRC32 (no inversion), */ + /* are used to index into one of the possible 128 bit positions. */ + Bitpos = ~Crc32 & 0x7f; - /* Hash register index. */ - RegIndex = (Bitpos & 0x60) >> 5; + /* Hash register index. */ + RegIndex = (Bitpos & 0x60) >> 5; - /* Bit to turn on within a hash register. */ - Bitpos &= 0x1f; + /* Bit to turn on within a hash register. */ + Bitpos &= 0x1f; - /* Enable the multicast bit. */ - HashReg[RegIndex] |= (1 << Bitpos); - } + /* Enable the multicast bit. */ + HashReg[RegIndex] |= (1 << Bitpos); + } - /* REV_AX has problem with multicast filtering where it uses both */ - /* DA and SA to perform hashing. */ - for(k = 0; k < 4; k++) - { - REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); - } + /* REV_AX has problem with multicast filtering where it uses both */ + /* DA and SA to perform hashing. */ + for(k = 0; k < 4; k++) + { + REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]); + } } else { - /* Reject all multicast frames. */ - for(j = 0; j < 4; j++) - { - REG_WR(pDevice, MacCtrl.HashReg[j], 0); - } + /* Reject all multicast frames. */ + for(j = 0; j < 4; j++) + { + REG_WR(pDevice, MacCtrl.HashReg[j], 0); + } } /* By default, Tigon3 will accept broadcast frames. We need to setup */ if(ReceiveMask & LM_ACCEPT_BROADCAST) { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK); } else { - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE1_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE1_VALUE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, - REJECT_BROADCAST_RULE2_RULE); - REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, - REJECT_BROADCAST_RULE2_VALUE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE1_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE1_VALUE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule, + REJECT_BROADCAST_RULE2_RULE); + REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value, + REJECT_BROADCAST_RULE2_VALUE); } /* disable the rest of the rules. */ for(j = RCV_LAST_RULE_IDX; j < 16; j++) { - REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); - REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); + REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0); + REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0); } return LM_STATUS_SUCCESS; } /* LM_SetReceiveMask */ - /******************************************************************************/ /* Description: */ /* Disable the interrupt and put the transmitter and receiver engines in */ @@ -3584,15 +3574,15 @@ PLM_DEVICE_BLOCK pDevice) while(pPacket) { - pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; - pDevice->TxCounters.TxPacketAbortedCnt++; + pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED; + pDevice->TxCounters.TxPacketAbortedCnt++; - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); - pPacket = (PLM_PACKET) - QQ_PopHead(&pDevice->TxPacketActiveQ.Container); + pPacket = (PLM_PACKET) + QQ_PopHead(&pDevice->TxPacketActiveQ.Container); } /* Cleanup the receive return rings. */ @@ -3602,38 +3592,38 @@ PLM_DEVICE_BLOCK pDevice) /* Doing so may cause system crash. */ if(!pDevice->ShuttingDown) { - /* Indicate packets to the protocol. */ - MM_IndicateTxPackets(pDevice); + /* Indicate packets to the protocol. */ + MM_IndicateTxPackets(pDevice); - /* Indicate received packets to the protocols. */ - MM_IndicateRxPackets(pDevice); + /* Indicate received packets to the protocols. */ + MM_IndicateRxPackets(pDevice); } else { - /* Move the receive packet descriptors in the ReceivedQ to the */ - /* free queue. */ - for(; ;) - { - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->RxPacketReceivedQ.Container); - if(pPacket == NULL) - { - break; - } - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - } + /* Move the receive packet descriptors in the ReceivedQ to the */ + /* free queue. */ + for(; ;) + { + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->RxPacketReceivedQ.Container); + if(pPacket == NULL) + { + break; + } + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + } } /* Clean up the Std Receive Producer ring. */ Idx = pDevice->pStatusBlkVirt->RcvStdConIdx; while(Idx != pDevice->RxStdProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque)); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK; } /* while */ /* Reinitialize our copy of the indices. */ @@ -3644,12 +3634,12 @@ PLM_DEVICE_BLOCK pDevice) Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx; while(Idx != pDevice->RxJumboProdIdx) { - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque)); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); - Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; + Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK; } /* while */ /* Reinitialize our copy of the indices. */ @@ -3668,7 +3658,6 @@ PLM_DEVICE_BLOCK pDevice) } /* LM_Abort */ - /******************************************************************************/ /* Description: */ /* Disable the interrupt and put the transmitter and receiver engines in */ @@ -3692,22 +3681,22 @@ PLM_DEVICE_BLOCK pDevice) { /* Make sure all the packets have been accounted for. */ for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) { - pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); - if (pPacket == 0) - break; + pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container); + if (pPacket == 0) + break; - MM_FreeRxBuffer(pDevice, pPacket); + MM_FreeRxBuffer(pDevice, pPacket); - QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); + QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket); } LM_ResetChip(pDevice); /* Restore PCI configuration registers. */ MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, - pDevice->SavedCacheLineReg); + pDevice->SavedCacheLineReg); LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, - (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); + (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId); /* Reprogram the MAC address. */ LM_SetMacAddress(pDevice, pDevice->NodeAddress); @@ -3725,20 +3714,20 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) /* Wait for access to the nvram interface before resetting. This is */ /* a workaround to prevent EEPROM corruption. */ if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) { - /* Request access to the flash interface. */ - REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); + /* Request access to the flash interface. */ + REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1); - for(j = 0; j < 100000; j++) - { - Value32 = REG_RD(pDevice, Nvram.SwArb); - if(Value32 & SW_ARB_GNT1) - { - break; - } - MM_Wait(10); - } + for(j = 0; j < 100000; j++) + { + Value32 = REG_RD(pDevice, Nvram.SwArb); + if(Value32 & SW_ARB_GNT1) + { + break; + } + MM_Wait(10); + } } /* Global reset. */ @@ -3747,22 +3736,22 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) /* make sure we re-enable indirect accesses */ MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, - pDevice->MiscHostCtrl); + pDevice->MiscHostCtrl); /* Set MAX PCI retry to zero. */ Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE; if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; - } + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 |= T3_PCI_STATE_RETRY_SAME_DMA; + } } MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32); /* Restore PCI command register. */ MM_WriteConfig32(pDevice, PCI_COMMAND_REG, - pDevice->PciCommandStatusWords); + pDevice->PciCommandStatusWords); /* Disable PCI-X relaxed ordering bit. */ MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32); @@ -3773,15 +3762,15 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE); #ifdef BIG_ENDIAN_PCI /* This from jfd */ - Value32 = GRC_MODE_WORD_SWAP_DATA| - GRC_MODE_WORD_SWAP_NON_FRAME_DATA; + Value32 = GRC_MODE_WORD_SWAP_DATA| + GRC_MODE_WORD_SWAP_NON_FRAME_DATA; #else #ifdef BIG_ENDIAN_HOST /* Reconfigure the mode register. */ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | - GRC_MODE_WORD_SWAP_NON_FRAME_DATA | - GRC_MODE_BYTE_SWAP_DATA | - GRC_MODE_WORD_SWAP_DATA; + GRC_MODE_WORD_SWAP_NON_FRAME_DATA | + GRC_MODE_BYTE_SWAP_DATA | + GRC_MODE_WORD_SWAP_DATA; #else /* Reconfigure the mode register. */ Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA; @@ -3793,23 +3782,23 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice) MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM); if(pDevice->EnableTbi) { - pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; - REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); + pDevice->MacMode = MAC_MODE_PORT_MODE_TBI; + REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI); } else { - REG_WR(pDevice, MacCtrl.Mode, 0); + REG_WR(pDevice, MacCtrl.Mode, 0); } /* Wait for the firmware to finish initialization. */ for(j = 0; j < 100000; j++) { - MM_Wait(10); + MM_Wait(10); - Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); - if(Value32 == ~T3_MAGIC_NUM) - { - break; - } + Value32 = MEM_RD_OFFSET(pDevice, 0x0b50); + if(Value32 == ~T3_MAGIC_NUM) + { + break; + } } return LM_STATUS_SUCCESS; } @@ -3837,25 +3826,25 @@ PLM_DEVICE_BLOCK pDevice) { /* descriptors that are between SwConIdx and HwConIdx. */ while(SwConIdx != HwConIdx) { - /* Get the packet that was sent from the TxPacketActiveQ. */ - pPacket = (PLM_PACKET) QQ_PopHead( - &pDevice->TxPacketActiveQ.Container); + /* Get the packet that was sent from the TxPacketActiveQ. */ + pPacket = (PLM_PACKET) QQ_PopHead( + &pDevice->TxPacketActiveQ.Container); - /* Set the return status. */ - pPacket->PacketStatus = LM_STATUS_SUCCESS; + /* Set the return status. */ + pPacket->PacketStatus = LM_STATUS_SUCCESS; - /* Put the packet in the TxPacketXmittedQ for indication later. */ - QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); + /* Put the packet in the TxPacketXmittedQ for indication later. */ + QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket); - /* Move to the next packet's BD. */ - SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & - T3_SEND_RCB_ENTRY_COUNT_MASK; + /* Move to the next packet's BD. */ + SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) & + T3_SEND_RCB_ENTRY_COUNT_MASK; - /* Update the number of unused BDs. */ - atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); + /* Update the number of unused BDs. */ + atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft); - /* Get the new updated HwConIdx. */ - HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; + /* Get the new updated HwConIdx. */ + HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx; } /* while */ /* Save the new SwConIdx. */ @@ -3864,7 +3853,6 @@ PLM_DEVICE_BLOCK pDevice) { } /* LM_ServiceTxInterrupt */ - /******************************************************************************/ /* Description: */ /* */ @@ -3884,89 +3872,89 @@ PLM_DEVICE_BLOCK pDevice) { SwRcvRetConIdx = pDevice->RcvRetConIdx; while(SwRcvRetConIdx != HwRcvRetProdIdx) { - pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; - - /* Get the received packet descriptor. */ - pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + - MM_UINT_PTR(pRcvBd->Opaque)); - - /* Check the error flag. */ - if(pRcvBd->ErrorFlag && - pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pPacket->PacketStatus = LM_STATUS_FAILURE; - - pDevice->RxCounters.RxPacketErrCnt++; - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) - { - pDevice->RxCounters.RxErrCrcCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) - { - pDevice->RxCounters.RxErrCollCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) - { - pDevice->RxCounters.RxErrLinkLostCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) - { - pDevice->RxCounters.RxErrPhyDecodeCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) - { - pDevice->RxCounters.RxErrOddNibbleCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) - { - pDevice->RxCounters.RxErrMacAbortCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) - { - pDevice->RxCounters.RxErrShortPacketCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) - { - pDevice->RxCounters.RxErrNoResourceCnt++; - } - - if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) - { - pDevice->RxCounters.RxErrLargePacketCnt++; - } - } - else - { - pPacket->PacketStatus = LM_STATUS_SUCCESS; - pPacket->PacketSize = pRcvBd->Len - 4; - - pPacket->Flags = pRcvBd->Flags; - if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) - { - pPacket->VlanTag = pRcvBd->VlanTag; - } - - pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; - } - - /* Put the packet descriptor containing the received packet */ - /* buffer in the RxPacketReceivedQ for indication later. */ - QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); - - /* Go to the next buffer descriptor. */ - SwRcvRetConIdx = (SwRcvRetConIdx + 1) & - T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; - - /* Get the updated HwRcvRetProdIdx. */ - HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; + pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx]; + + /* Get the received packet descriptor. */ + pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) + + MM_UINT_PTR(pRcvBd->Opaque)); + + /* Check the error flag. */ + if(pRcvBd->ErrorFlag && + pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pPacket->PacketStatus = LM_STATUS_FAILURE; + + pDevice->RxCounters.RxPacketErrCnt++; + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) + { + pDevice->RxCounters.RxErrCrcCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) + { + pDevice->RxCounters.RxErrCollCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) + { + pDevice->RxCounters.RxErrLinkLostCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) + { + pDevice->RxCounters.RxErrPhyDecodeCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) + { + pDevice->RxCounters.RxErrOddNibbleCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) + { + pDevice->RxCounters.RxErrMacAbortCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) + { + pDevice->RxCounters.RxErrShortPacketCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) + { + pDevice->RxCounters.RxErrNoResourceCnt++; + } + + if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) + { + pDevice->RxCounters.RxErrLargePacketCnt++; + } + } + else + { + pPacket->PacketStatus = LM_STATUS_SUCCESS; + pPacket->PacketSize = pRcvBd->Len - 4; + + pPacket->Flags = pRcvBd->Flags; + if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) + { + pPacket->VlanTag = pRcvBd->VlanTag; + } + + pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum; + } + + /* Put the packet descriptor containing the received packet */ + /* buffer in the RxPacketReceivedQ for indication later. */ + QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket); + + /* Go to the next buffer descriptor. */ + SwRcvRetConIdx = (SwRcvRetConIdx + 1) & + T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK; + + /* Get the updated HwRcvRetProdIdx. */ + HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx; } /* while */ pDevice->RcvRetConIdx = SwRcvRetConIdx; @@ -3976,7 +3964,6 @@ PLM_DEVICE_BLOCK pDevice) { } /* LM_ServiceRxInterrupt */ - /******************************************************************************/ /* Description: */ /* This is the interrupt event handler routine. It acknowledges all */ @@ -3995,37 +3982,37 @@ LM_ServiceInterrupts( /* Setup the phy chip whenever the link status changes. */ if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) - { - if (Value32 & MAC_STATUS_MI_INTERRUPT) - { - ServicePhyInt = TRUE; - } - } - else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) - { - ServicePhyInt = TRUE; - } + Value32 = REG_RD(pDevice, MacCtrl.Status); + if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) + { + if (Value32 & MAC_STATUS_MI_INTERRUPT) + { + ServicePhyInt = TRUE; + } + } + else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED) + { + ServicePhyInt = TRUE; + } } else { - if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) - { - pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); - ServicePhyInt = TRUE; - } + if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS) + { + pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + ServicePhyInt = TRUE; + } } #if INCLUDE_TBI_SUPPORT if (pDevice->IgnoreTbiLinkChange == TRUE) { - ServicePhyInt = FALSE; + ServicePhyInt = FALSE; } #endif if (ServicePhyInt == TRUE) { - LM_SetupPhy(pDevice); + LM_SetupPhy(pDevice); } /* Service receive and transmit interrupts. */ @@ -4035,22 +4022,21 @@ LM_ServiceInterrupts( /* No spinlock for this queue since this routine is serialized. */ if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container)) { - /* Indicate receive packets. */ - MM_IndicateRxPackets(pDevice); + /* Indicate receive packets. */ + MM_IndicateRxPackets(pDevice); /* LM_QueueRxPackets(pDevice); */ } /* No spinlock for this queue since this routine is serialized. */ if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container)) { - MM_IndicateTxPackets(pDevice); + MM_IndicateTxPackets(pDevice); } return LM_STATUS_SUCCESS; } /* LM_ServiceInterrupts */ - /******************************************************************************/ /* Description: */ /* */ @@ -4066,20 +4052,20 @@ PLM_UINT8 pMcAddress) { pEntry = pDevice->McTable[0]; for(j = 0; j < pDevice->McEntryCount; j++) { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, increment the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, increment the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1; - return LM_STATUS_SUCCESS; - } + return LM_STATUS_SUCCESS; + } - pEntry += LM_MC_ENTRY_SIZE; + pEntry += LM_MC_ENTRY_SIZE; } if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } pEntry = pDevice->McTable[pDevice->McEntryCount]; @@ -4095,7 +4081,6 @@ PLM_UINT8 pMcAddress) { } /* LM_MulticastAdd */ - /******************************************************************************/ /* Description: */ /* */ @@ -4111,43 +4096,42 @@ PLM_UINT8 pMcAddress) { pEntry = pDevice->McTable[0]; for(j = 0; j < pDevice->McEntryCount; j++) { - if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) - { - /* Found a match, decrement the instance count. */ - pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; - - /* No more instance left, remove the address from the table. */ - /* Move the last entry in the table to the delete slot. */ - if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && - pDevice->McEntryCount > 1) - { - - COPY_ETH_ADDRESS( - pDevice->McTable[pDevice->McEntryCount-1], pEntry); - pEntry[LM_MC_INSTANCE_COUNT_INDEX] = - pDevice->McTable[pDevice->McEntryCount-1] - [LM_MC_INSTANCE_COUNT_INDEX]; - } - pDevice->McEntryCount--; - - /* Update the receive mask if the table is empty. */ - if(pDevice->McEntryCount == 0) - { - LM_SetReceiveMask(pDevice, - pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); - } - - return LM_STATUS_SUCCESS; - } + if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress)) + { + /* Found a match, decrement the instance count. */ + pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1; + + /* No more instance left, remove the address from the table. */ + /* Move the last entry in the table to the delete slot. */ + if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 && + pDevice->McEntryCount > 1) + { + + COPY_ETH_ADDRESS( + pDevice->McTable[pDevice->McEntryCount-1], pEntry); + pEntry[LM_MC_INSTANCE_COUNT_INDEX] = + pDevice->McTable[pDevice->McEntryCount-1] + [LM_MC_INSTANCE_COUNT_INDEX]; + } + pDevice->McEntryCount--; + + /* Update the receive mask if the table is empty. */ + if(pDevice->McEntryCount == 0) + { + LM_SetReceiveMask(pDevice, + pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST); + } + + return LM_STATUS_SUCCESS; + } - pEntry += LM_MC_ENTRY_SIZE; + pEntry += LM_MC_ENTRY_SIZE; } return LM_STATUS_FAILURE; } /* LM_MulticastDel */ - /******************************************************************************/ /* Description: */ /* */ @@ -4164,7 +4148,6 @@ PLM_DEVICE_BLOCK pDevice) { } /* LM_MulticastClear */ - /******************************************************************************/ /* Description: */ /* */ @@ -4179,11 +4162,11 @@ LM_SetMacAddress( for(j = 0; j < 4; j++) { - REG_WR(pDevice, MacCtrl.MacAddr[j].High, - (pMacAddress[0] << 8) | pMacAddress[1]); - REG_WR(pDevice, MacCtrl.MacAddr[j].Low, - (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | - (pMacAddress[4] << 8) | pMacAddress[5]); + REG_WR(pDevice, MacCtrl.MacAddr[j].High, + (pMacAddress[0] << 8) | pMacAddress[1]); + REG_WR(pDevice, MacCtrl.MacAddr[j].Low, + (pMacAddress[2] << 24) | (pMacAddress[3] << 16) | + (pMacAddress[4] << 8) | pMacAddress[5]); } return LM_STATUS_SUCCESS; @@ -4210,78 +4193,78 @@ PLM_DUPLEX_MODE pDuplexMode) { /* determine media type */ switch(RequestedMediaType) { - case LM_REQUESTED_MEDIA_TYPE_BNC: - *pMediaType = LM_MEDIA_TYPE_BNC; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: - *pMediaType = LM_MEDIA_TYPE_UTP; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_10MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_UTP; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_100MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: - *pMediaType = LM_MEDIA_TYPE_FIBER; - *pLineSpeed = LM_LINE_SPEED_1000MBPS; - *pDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - default: - break; + case LM_REQUESTED_MEDIA_TYPE_BNC: + *pMediaType = LM_MEDIA_TYPE_BNC; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO: + *pMediaType = LM_MEDIA_TYPE_UTP; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_10MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_UTP; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_100MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX: + *pMediaType = LM_MEDIA_TYPE_FIBER; + *pLineSpeed = LM_LINE_SPEED_1000MBPS; + *pDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + break; } /* switch */ return LM_STATUS_SUCCESS; @@ -4309,92 +4292,92 @@ PLM_DEVICE_BLOCK pDevice) #endif if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(!pDevice->InitDone) - { - Value32 = 0; - } + if(!pDevice->InitDone) + { + Value32 = 0; + } - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - for(j = 0; j < 1000; j++) - { - MM_Wait(10); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + for(j = 0; j < 1000; j++) + { + MM_Wait(10); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - MM_Wait(40); - break; - } - } + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + MM_Wait(40); + break; + } + } - if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) - { - if(!(Value32 & PHY_STATUS_LINK_PASS) && - (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) - { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); - for(j = 0; j < 100; j++) - { - MM_Wait(10); + if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV) + { + if(!(Value32 & PHY_STATUS_LINK_PASS) && + (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS)) + { + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET); + for(j = 0; j < 100; j++) + { + MM_Wait(10); - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(!(Value32 & PHY_CTRL_PHY_RESET)) - { - MM_Wait(40); - break; - } - } + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(!(Value32 & PHY_CTRL_PHY_RESET)) + { + MM_Wait(40); + break; + } + } - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232); - LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); - LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); - } - } - } + LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f); + LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20); + } + } + } } else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) { - /* Bug: 5701 A0, B0 TX CRC workaround. */ - LM_WritePhy(pDevice, 0x15, 0x0a75); - LM_WritePhy(pDevice, 0x1c, 0x8c68); - LM_WritePhy(pDevice, 0x1c, 0x8d68); - LM_WritePhy(pDevice, 0x1c, 0x8c68); + /* Bug: 5701 A0, B0 TX CRC workaround. */ + LM_WritePhy(pDevice, 0x15, 0x0a75); + LM_WritePhy(pDevice, 0x1c, 0x8c68); + LM_WritePhy(pDevice, 0x1c, 0x8d68); + LM_WritePhy(pDevice, 0x1c, 0x8c68); } /* Acknowledge interrupts. */ @@ -4404,22 +4387,22 @@ PLM_DEVICE_BLOCK pDevice) /* Configure the interrupt mask. */ if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { - LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); + LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE); } /* Configure PHY led mode. */ if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 || - (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) + (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)) { - if(pDevice->LedMode == LED_MODE_THREE_LINK) - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, - BCM540X_EXT_CTRL_LINK3_LED_MODE); - } - else - { - LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); - } + if(pDevice->LedMode == LED_MODE_THREE_LINK) + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, + BCM540X_EXT_CTRL_LINK3_LED_MODE); + } + else + { + LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0); + } } CurrentLinkStatus = LM_STATUS_LINK_DOWN; @@ -4427,148 +4410,148 @@ PLM_DEVICE_BLOCK pDevice) /* Get current link and duplex mode. */ for(j = 0; j < 100; j++) { - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - break; - } - MM_Wait(40); + if(Value32 & PHY_STATUS_LINK_PASS) + { + break; + } + MM_Wait(40); } if(Value32 & PHY_STATUS_LINK_PASS) { - /* Determine the current line and duplex settings. */ - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - for(j = 0; j < 2000; j++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); - if(Value32) - { - break; - } - } - - switch(Value32 & BCM540X_AUX_SPEED_MASK) - { - case BCM540X_AUX_10BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case BCM540X_AUX_10BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_10MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case BCM540X_AUX_100BASETX_HD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case BCM540X_AUX_100BASETX_FD: - CurrentLineSpeed = LM_LINE_SPEED_100MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - case BCM540X_AUX_100BASET_HD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_HALF; - break; - - case BCM540X_AUX_100BASET_FD: - CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; - CurrentDuplexMode = LM_DUPLEX_MODE_FULL; - break; - - default: - - CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; - CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; - break; - } - - /* Make sure we are in auto-neg mode. */ - for (j = 0; j < 200; j++) - { - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 && Value32 != 0x7fff) - { - break; - } - - if(Value32 == 0 && pDevice->RequestedMediaType == - LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) - { - break; - } - - MM_Wait(10); - } - - /* Use the current line settings for "auto" mode. */ - if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - - /* We may be exiting low power mode and the link is in */ - /* 10mb. In this case, we need to restart autoneg. */ - LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); - pDevice->advertising1000 = Value32; - /* 5702FE supports 10/100Mb only. */ - if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || - pDevice->BondId != GRC_MISC_BD_ID_5702FE) - { - if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | - BCM540X_AN_AD_1000BASET_FULL))) - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - else - { - /* Force line settings. */ - /* Use the current setting if it matches the user's requested */ - /* setting. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if((pDevice->LineSpeed == CurrentLineSpeed) && - (pDevice->DuplexMode == CurrentDuplexMode)) - { - if ((pDevice->DisableAutoNeg && - !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || - (!pDevice->DisableAutoNeg && - (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - else - { - CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; - } - } - - /* Save line settings. */ - pDevice->LineSpeed = CurrentLineSpeed; - pDevice->DuplexMode = CurrentDuplexMode; - pDevice->MediaType = LM_MEDIA_TYPE_UTP; + /* Determine the current line and duplex settings. */ + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + for(j = 0; j < 2000; j++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32); + if(Value32) + { + break; + } + } + + switch(Value32 & BCM540X_AUX_SPEED_MASK) + { + case BCM540X_AUX_10BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_10BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_10MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASETX_HD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASETX_FD: + CurrentLineSpeed = LM_LINE_SPEED_100MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + case BCM540X_AUX_100BASET_HD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_HALF; + break; + + case BCM540X_AUX_100BASET_FD: + CurrentLineSpeed = LM_LINE_SPEED_1000MBPS; + CurrentDuplexMode = LM_DUPLEX_MODE_FULL; + break; + + default: + + CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN; + CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN; + break; + } + + /* Make sure we are in auto-neg mode. */ + for (j = 0; j < 200; j++) + { + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 && Value32 != 0x7fff) + { + break; + } + + if(Value32 == 0 && pDevice->RequestedMediaType == + LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) + { + break; + } + + MM_Wait(10); + } + + /* Use the current line settings for "auto" mode. */ + if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + + /* We may be exiting low power mode and the link is in */ + /* 10mb. In this case, we need to restart autoneg. */ + LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32); + pDevice->advertising1000 = Value32; + /* 5702FE supports 10/100Mb only. */ + if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 || + pDevice->BondId != GRC_MISC_BD_ID_5702FE) + { + if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF | + BCM540X_AN_AD_1000BASET_FULL))) + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + /* Force line settings. */ + /* Use the current setting if it matches the user's requested */ + /* setting. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if((pDevice->LineSpeed == CurrentLineSpeed) && + (pDevice->DuplexMode == CurrentDuplexMode)) + { + if ((pDevice->DisableAutoNeg && + !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) || + (!pDevice->DisableAutoNeg && + (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + else + { + CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH; + } + } + + /* Save line settings. */ + pDevice->LineSpeed = CurrentLineSpeed; + pDevice->DuplexMode = CurrentDuplexMode; + pDevice->MediaType = LM_MEDIA_TYPE_UTP; } return CurrentLinkStatus; @@ -4593,51 +4576,51 @@ LM_SetFlowControl( /* See Table 28B-3 of 802.3ab-1999 spec. */ if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) { - if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) - { - if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) - { - FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - else - { - if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | - LM_FLOW_CONTROL_RECEIVE_PAUSE; - } - } - } - else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) - { - if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && - (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) - { - FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; - } - } + if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) + { + if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE) + { + FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + else + { + if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE | + LM_FLOW_CONTROL_RECEIVE_PAUSE; + } + } + } + else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) + { + if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) && + (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) + { + FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE; + } + } } else { - FlowCap = pDevice->FlowControlCap; + FlowCap = pDevice->FlowControlCap; } /* Enable/disable rx PAUSE. */ pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL; if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) { - pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; - pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; + pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE; + pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL; } REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode); @@ -4645,11 +4628,11 @@ LM_SetFlowControl( /* Enable/disable tx PAUSE. */ pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL; if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE && - (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || - pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) + (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE || + pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) { - pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; - pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; + pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE; + pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL; } REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode); @@ -4676,51 +4659,50 @@ LM_InitBcm800xPhy( /* Reset the SERDES during init and when we have link. */ if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) { - /* Set PLL lock range. */ - LM_WritePhy(pDevice, 0x16, 0x8007); + /* Set PLL lock range. */ + LM_WritePhy(pDevice, 0x16, 0x8007); - /* Software reset. */ - LM_WritePhy(pDevice, 0x00, 0x8000); + /* Software reset. */ + LM_WritePhy(pDevice, 0x00, 0x8000); - /* Wait for reset to complete. */ - for(j = 0; j < 500; j++) - { - MM_Wait(10); - } + /* Wait for reset to complete. */ + for(j = 0; j < 500; j++) + { + MM_Wait(10); + } - /* Config mode; seletct PMA/Ch 1 regs. */ - LM_WritePhy(pDevice, 0x10, 0x8411); + /* Config mode; seletct PMA/Ch 1 regs. */ + LM_WritePhy(pDevice, 0x10, 0x8411); - /* Enable auto-lock and comdet, select txclk for tx. */ - LM_WritePhy(pDevice, 0x11, 0x0a10); + /* Enable auto-lock and comdet, select txclk for tx. */ + LM_WritePhy(pDevice, 0x11, 0x0a10); - LM_WritePhy(pDevice, 0x18, 0x00a0); - LM_WritePhy(pDevice, 0x16, 0x41ff); + LM_WritePhy(pDevice, 0x18, 0x00a0); + LM_WritePhy(pDevice, 0x16, 0x41ff); - /* Assert and deassert POR. */ - LM_WritePhy(pDevice, 0x13, 0x0400); - MM_Wait(40); - LM_WritePhy(pDevice, 0x13, 0x0000); + /* Assert and deassert POR. */ + LM_WritePhy(pDevice, 0x13, 0x0400); + MM_Wait(40); + LM_WritePhy(pDevice, 0x13, 0x0000); - LM_WritePhy(pDevice, 0x11, 0x0a50); - MM_Wait(40); - LM_WritePhy(pDevice, 0x11, 0x0a10); + LM_WritePhy(pDevice, 0x11, 0x0a50); + MM_Wait(40); + LM_WritePhy(pDevice, 0x11, 0x0a10); - /* Delay for signal to stabilize. */ - for(j = 0; j < 15000; j++) - { - MM_Wait(10); - } + /* Delay for signal to stabilize. */ + for(j = 0; j < 15000; j++) + { + MM_Wait(10); + } - /* Deselect the channel register so we can read the PHY id later. */ - LM_WritePhy(pDevice, 0x10, 0x8011); + /* Deselect the channel register so we can read the PHY id later. */ + LM_WritePhy(pDevice, 0x10, 0x8011); } return LM_STATUS_SUCCESS; } - /******************************************************************************/ /* Description: */ /* */ @@ -4748,12 +4730,12 @@ LM_SetupFiberPhy( /* Initialize the BCM8002 SERDES PHY. */ switch(pDevice->PhyId & PHY_ID_MASK) { - case PHY_BCM8002_PHY_ID: - LM_InitBcm800xPhy(pDevice); - break; + case PHY_BCM8002_PHY_ID: + LM_InitBcm800xPhy(pDevice); + break; - default: - break; + default: + break; } /* Enable link change interrupt. */ @@ -4766,218 +4748,218 @@ LM_SetupFiberPhy( Value32 = REG_RD(pDevice, MacCtrl.Status); if(Value32 & MAC_STATUS_PCS_SYNCED) { - if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || - (pDevice->DisableAutoNeg == FALSE)) - { - /* auto-negotiation mode. */ - /* Initialize the autoneg default capaiblities. */ - AutonegInit(&pDevice->AnInfo); - - /* Set the context pointer to point to the main device structure. */ - pDevice->AnInfo.pContext = pDevice; - - /* Setup flow control advertisement register. */ - Value32 = GetPhyAdFlowCntrlSettings(pDevice); - if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) - { - pDevice->AnInfo.mr_adv_sym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_sym_pause = 0; - } - - if(Value32 & PHY_AN_AD_ASYM_PAUSE) - { - pDevice->AnInfo.mr_adv_asym_pause = 1; - } - else - { - pDevice->AnInfo.mr_adv_asym_pause = 0; - } - - /* Try to autoneg up to six times. */ - if (pDevice->IgnoreTbiLinkChange) - { - Cnt = 1; - } - else - { - Cnt = 6; - } - for (j = 0; j < Cnt; j++) - { - REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); - - Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(20); - - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - - MM_Wait(20); - - pDevice->AnInfo.State = AN_STATE_UNKNOWN; - pDevice->AnInfo.CurrentTime_us = 0; - - REG_WR(pDevice, Grc.Timer, 0); - for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && - (k < 75000); k++) - { - AnStatus = Autoneg8023z(&pDevice->AnInfo); - - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } - - pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); - - } - if((AnStatus == AUTONEG_STATUS_DONE) || - (AnStatus == AUTONEG_STATUS_FAILED)) - { - break; - } - if (j >= 1) - { - if (!(REG_RD(pDevice, MacCtrl.Status) & - MAC_STATUS_PCS_SYNCED)) { - break; - } - } - } - - /* Stop sending configs. */ - MM_AnTxIdle(&pDevice->AnInfo); - - /* Resolve flow control settings. */ - if((AnStatus == AUTONEG_STATUS_DONE) && - pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && - pDevice->AnInfo.mr_lp_adv_full_duplex) - { - LM_UINT32 RemotePhyAd; - LM_UINT32 LocalPhyAd; - - LocalPhyAd = 0; - if(pDevice->AnInfo.mr_adv_sym_pause) - { - LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; - } - - if(pDevice->AnInfo.mr_adv_asym_pause) - { - LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; - } - - RemotePhyAd = 0; - if(pDevice->AnInfo.mr_lp_adv_sym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; - } - - if(pDevice->AnInfo.mr_lp_adv_asym_pause) - { - RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; - } - - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); - - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - for (j = 0; j < 30; j++) - { - MM_Wait(20); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(20); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; - } - if (pDevice->PollTbiLink) - { - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (Value32 & MAC_STATUS_RECEIVING_CFG) - { - pDevice->IgnoreTbiLinkChange = TRUE; - } - else - { - pDevice->IgnoreTbiLinkChange = FALSE; - } - } - Value32 = REG_RD(pDevice, MacCtrl.Status); - if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && - (Value32 & MAC_STATUS_PCS_SYNCED) && - ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } - } - else - { - /* We are forcing line speed. */ - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - } + if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) || + (pDevice->DisableAutoNeg == FALSE)) + { + /* auto-negotiation mode. */ + /* Initialize the autoneg default capaiblities. */ + AutonegInit(&pDevice->AnInfo); + + /* Set the context pointer to point to the main device structure. */ + pDevice->AnInfo.pContext = pDevice; + + /* Setup flow control advertisement register. */ + Value32 = GetPhyAdFlowCntrlSettings(pDevice); + if(Value32 & PHY_AN_AD_PAUSE_CAPABLE) + { + pDevice->AnInfo.mr_adv_sym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_sym_pause = 0; + } + + if(Value32 & PHY_AN_AD_ASYM_PAUSE) + { + pDevice->AnInfo.mr_adv_asym_pause = 1; + } + else + { + pDevice->AnInfo.mr_adv_asym_pause = 0; + } + + /* Try to autoneg up to six times. */ + if (pDevice->IgnoreTbiLinkChange) + { + Cnt = 1; + } + else + { + Cnt = 6; + } + for (j = 0; j < Cnt; j++) + { + REG_WR(pDevice, MacCtrl.TxAutoNeg, 0); + + Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK; + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(20); + + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + + MM_Wait(20); + + pDevice->AnInfo.State = AN_STATE_UNKNOWN; + pDevice->AnInfo.CurrentTime_us = 0; + + REG_WR(pDevice, Grc.Timer, 0); + for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) && + (k < 75000); k++) + { + AnStatus = Autoneg8023z(&pDevice->AnInfo); + + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + + pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer); + + } + if((AnStatus == AUTONEG_STATUS_DONE) || + (AnStatus == AUTONEG_STATUS_FAILED)) + { + break; + } + if (j >= 1) + { + if (!(REG_RD(pDevice, MacCtrl.Status) & + MAC_STATUS_PCS_SYNCED)) { + break; + } + } + } + + /* Stop sending configs. */ + MM_AnTxIdle(&pDevice->AnInfo); + + /* Resolve flow control settings. */ + if((AnStatus == AUTONEG_STATUS_DONE) && + pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok && + pDevice->AnInfo.mr_lp_adv_full_duplex) + { + LM_UINT32 RemotePhyAd; + LM_UINT32 LocalPhyAd; + + LocalPhyAd = 0; + if(pDevice->AnInfo.mr_adv_sym_pause) + { + LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_adv_asym_pause) + { + LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE; + } + + RemotePhyAd = 0; + if(pDevice->AnInfo.mr_lp_adv_sym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE; + } + + if(pDevice->AnInfo.mr_lp_adv_asym_pause) + { + RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE; + } + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + for (j = 0; j < 30; j++) + { + MM_Wait(20); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(20); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; + } + if (pDevice->PollTbiLink) + { + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (Value32 & MAC_STATUS_RECEIVING_CFG) + { + pDevice->IgnoreTbiLinkChange = TRUE; + } + else + { + pDevice->IgnoreTbiLinkChange = FALSE; + } + } + Value32 = REG_RD(pDevice, MacCtrl.Status); + if (CurrentLinkStatus == LM_STATUS_LINK_DOWN && + (Value32 & MAC_STATUS_PCS_SYNCED) && + ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } + } + else + { + /* We are forcing line speed. */ + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + } } /* Set the link polarity bit. */ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED | - (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); + (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS); for (j = 0; j < 100; j++) { - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MM_Wait(5); - if ((REG_RD(pDevice, MacCtrl.Status) & - (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) - break; + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MM_Wait(5); + if ((REG_RD(pDevice, MacCtrl.Status) & + (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0) + break; } Value32 = REG_RD(pDevice, MacCtrl.Status); if((Value32 & MAC_STATUS_PCS_SYNCED) == 0) { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - if (pDevice->DisableAutoNeg == FALSE) - { - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | - MAC_MODE_SEND_CONFIGS); - MM_Wait(1); - REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); - } + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + if (pDevice->DisableAutoNeg == FALSE) + { + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode | + MAC_MODE_SEND_CONFIGS); + MM_Wait(1); + REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); + } } /* Initialize the current link status. */ if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { - pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; - pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_1000MBPS_LED_ON); + pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS; + pDevice->DuplexMode = LM_DUPLEX_MODE_FULL; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_1000MBPS_LED_ON); } else { - pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; - pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; - REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | - LED_CTRL_OVERRIDE_TRAFFIC_LED); + pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN; + pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN; + REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | + LED_CTRL_OVERRIDE_TRAFFIC_LED); } /* Indicate link status. */ if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); } return LM_STATUS_SUCCESS; @@ -5005,7 +4987,7 @@ LM_SetupCopperPhy( /* Clear link change attention. */ REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); + MAC_STATUS_CFG_CHANGED); /* Disable auto-polling for the moment. */ pDevice->MiMode = 0xc0000; @@ -5015,147 +4997,147 @@ LM_SetupCopperPhy( /* Determine the requested line speed and duplex. */ pDevice->OldLineSpeed = pDevice->LineSpeed; LM_TranslateRequestedMediaType(pDevice->RequestedMediaType, - &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); + &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode); /* Initialize the phy chip. */ switch(pDevice->PhyId & PHY_ID_MASK) { - case PHY_BCM5400_PHY_ID: - case PHY_BCM5401_PHY_ID: - case PHY_BCM5411_PHY_ID: - case PHY_BCM5701_PHY_ID: - case PHY_BCM5703_PHY_ID: - case PHY_BCM5704_PHY_ID: - CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); - break; + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + CurrentLinkStatus = LM_InitBcm540xPhy(pDevice); + break; - default: - break; + default: + break; } if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; + CurrentLinkStatus = LM_STATUS_LINK_DOWN; } /* Setup flow control. */ pDevice->FlowControl = LM_FLOW_CONTROL_NONE; if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { - LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ - - FlowCap = LM_FLOW_CONTROL_NONE; + LM_FLOW_CONTROL FlowCap; /* Flow control capability. */ - if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) - { - if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - LM_UINT32 ExpectedPhyAd; - LM_UINT32 LocalPhyAd; - LM_UINT32 RemotePhyAd; + FlowCap = LM_FLOW_CONTROL_NONE; - LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); + if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) + { + if(pDevice->DisableAutoNeg == FALSE || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + LM_UINT32 ExpectedPhyAd; + LM_UINT32 LocalPhyAd; + LM_UINT32 RemotePhyAd; + + LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd); pDevice->advertising = LocalPhyAd; - LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); - - ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); - - if(LocalPhyAd != ExpectedPhyAd) - { - CurrentLinkStatus = LM_STATUS_LINK_DOWN; - } - else - { - LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, - &RemotePhyAd); - - LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); - } - } - else - { - pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; - LM_SetFlowControl(pDevice, 0, 0); - } - } + LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE); + + ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice); + + if(LocalPhyAd != ExpectedPhyAd) + { + CurrentLinkStatus = LM_STATUS_LINK_DOWN; + } + else + { + LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG, + &RemotePhyAd); + + LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd); + } + } + else + { + pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE; + LM_SetFlowControl(pDevice, 0, 0); + } + } } if(CurrentLinkStatus == LM_STATUS_LINK_DOWN) { - LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); + LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType); - /* If we force line speed, we make get link right away. */ - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - if(Value32 & PHY_STATUS_LINK_PASS) - { - CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; - } + /* If we force line speed, we make get link right away. */ + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + if(Value32 & PHY_STATUS_LINK_PASS) + { + CurrentLinkStatus = LM_STATUS_LINK_ACTIVE; + } } /* GMII interface. */ pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK; if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) { - if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; - } - else - { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; - } + if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS || + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_MII; + } + else + { + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + } } else { - pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; + pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII; } /* Set the MAC to operate in the appropriate duplex mode. */ pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX; if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) { - pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; + pDevice->MacMode |= MAC_MODE_HALF_DUPLEX; } /* Set the link polarity bit. */ pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY; if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) { - if((pDevice->LedMode == LED_MODE_LINK10) || - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && - pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; - } + if((pDevice->LedMode == LED_MODE_LINK10) || + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE && + pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } } else { - if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) - { - pDevice->MacMode |= MAC_MODE_LINK_POLARITY; - } - - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } - } - REG_WR(pDevice, MacCtrl.LedCtrl, Value32); + if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) + { + pDevice->MacMode |= MAC_MODE_LINK_POLARITY; + } + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + REG_WR(pDevice, MacCtrl.LedCtrl, Value32); } REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode); @@ -5163,38 +5145,38 @@ LM_SetupCopperPhy( /* Enable auto polling. */ if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE; + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); } /* Enable phy link change attention. */ if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) { - REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); + REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT); } else { - REG_WR(pDevice, MacCtrl.MacEvent, - MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); + REG_WR(pDevice, MacCtrl.MacEvent, + MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN); } if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) && - (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && - (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && - (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || - !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) + (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) && + (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && + (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) && + (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) || + !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) { - MM_Wait(120); - REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | - MAC_STATUS_CFG_CHANGED); - MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, - T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); + MM_Wait(120); + REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED | + MAC_STATUS_CFG_CHANGED); + MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX, + T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE); } /* Indicate link status. */ if (pDevice->LinkStatus != CurrentLinkStatus) { - pDevice->LinkStatus = CurrentLinkStatus; - MM_IndicateStatus(pDevice, CurrentLinkStatus); + pDevice->LinkStatus = CurrentLinkStatus; + MM_IndicateStatus(pDevice, CurrentLinkStatus); } return LM_STATUS_SUCCESS; @@ -5215,30 +5197,30 @@ LM_SetupPhy( #if INCLUDE_TBI_SUPPORT if(pDevice->EnableTbi) { - LmStatus = LM_SetupFiberPhy(pDevice); + LmStatus = LM_SetupFiberPhy(pDevice); } else #endif /* INCLUDE_TBI_SUPPORT */ { - LmStatus = LM_SetupCopperPhy(pDevice); + LmStatus = LM_SetupCopperPhy(pDevice); } if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) { - if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) - { - Value32 = REG_RD(pDevice, PciCfg.PciState); - REG_WR(pDevice, PciCfg.PciState, - Value32 | T3_PCI_STATE_RETRY_SAME_DMA); - } + if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) + { + Value32 = REG_RD(pDevice, PciCfg.PciState); + REG_WR(pDevice, PciCfg.PciState, + Value32 | T3_PCI_STATE_RETRY_SAME_DMA); + } } if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) && - (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) + (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) { - REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); + REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff); } else { - REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); + REG_WR(pDevice, MacCtrl.TxLengths, 0x2620); } return LmStatus; @@ -5259,48 +5241,47 @@ PLM_UINT32 pData32) { if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); } Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - MI_COM_CMD_READ | MI_COM_START; + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + MI_COM_CMD_READ | MI_COM_START; REG_WR(pDevice, MacCtrl.MiCom, Value32); for(j = 0; j < 20; j++) { - MM_Wait(25); + MM_Wait(25); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 = REG_RD(pDevice, MacCtrl.MiCom); - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); - Value32 &= MI_COM_PHY_DATA_MASK; - break; - } + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 &= MI_COM_PHY_DATA_MASK; + break; + } } if(Value32 & MI_COM_BUSY) { - Value32 = 0; + Value32 = 0; } *pData32 = Value32; if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); } } /* LM_ReadPhy */ - /******************************************************************************/ /* Description: */ /* */ @@ -5316,34 +5297,34 @@ LM_UINT32 Data32) { if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & - ~MI_MODE_AUTO_POLLING_ENABLE); - MM_Wait(40); + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode & + ~MI_MODE_AUTO_POLLING_ENABLE); + MM_Wait(40); } Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) | - ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | - (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; + ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) | + (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START; REG_WR(pDevice, MacCtrl.MiCom, Value32); for(j = 0; j < 20; j++) { - MM_Wait(25); + MM_Wait(25); - Value32 = REG_RD(pDevice, MacCtrl.MiCom); + Value32 = REG_RD(pDevice, MacCtrl.MiCom); - if(!(Value32 & MI_COM_BUSY)) - { - MM_Wait(5); - break; - } + if(!(Value32 & MI_COM_BUSY)) + { + MM_Wait(5); + break; + } } if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) { - REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); - MM_Wait(40); + REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode); + MM_Wait(40); } } /* LM_WritePhy */ @@ -5375,33 +5356,33 @@ LM_POWER_STATE PowerLevel) { if(PowerLevel == LM_POWER_STATE_D0) { - /* Bring the card out of low power mode. */ - PmCtrl |= T3_PM_POWER_STATE_D0; - MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); + /* Bring the card out of low power mode. */ + PmCtrl |= T3_PM_POWER_STATE_D0; + MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl); - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); - MM_Wait (40); + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl); + MM_Wait (40); #if 0 /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02); #endif - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } else if(PowerLevel == LM_POWER_STATE_D1) { - PmCtrl |= T3_PM_POWER_STATE_D1; + PmCtrl |= T3_PM_POWER_STATE_D1; } else if(PowerLevel == LM_POWER_STATE_D2) { - PmCtrl |= T3_PM_POWER_STATE_D2; + PmCtrl |= T3_PM_POWER_STATE_D2; } else if(PowerLevel == LM_POWER_STATE_D3) { - PmCtrl |= T3_PM_POWER_STATE_D3; + PmCtrl |= T3_PM_POWER_STATE_D3; } else { - return LM_STATUS_FAILURE; + return LM_STATUS_FAILURE; } PmCtrl |= T3_PM_PME_ENABLE; @@ -5412,9 +5393,9 @@ LM_POWER_STATE PowerLevel) { if(!pDevice->RestoreOnWakeUp) { - pDevice->RestoreOnWakeUp = TRUE; - pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; - pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; + pDevice->RestoreOnWakeUp = TRUE; + pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg; + pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType; } /* Force auto-negotiation to 10 line speed. */ @@ -5431,168 +5412,168 @@ LM_POWER_STATE PowerLevel) { if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) { - /* Enable WOL. */ - LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); - MM_Wait(40); - - /* Set LED mode. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = LED_CTRL_PHY_MODE_1; - } - else - { - if(pDevice->LedMode == LED_MODE_OUTPUT) - { - Value32 = LED_CTRL_PHY_MODE_2; - } - else - { - Value32 = LED_CTRL_PHY_MODE_1; - } - } - - Value32 = MAC_MODE_PORT_MODE_MII; - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) - { - if(pDevice->LedMode == LED_MODE_LINK10 || - pDevice->WolSpeed == WOL_SPEED_10MB) - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - } - else - { - Value32 |= MAC_MODE_LINK_POLARITY; - } - REG_WR(pDevice, MacCtrl.Mode, Value32); - MM_Wait(40); MM_Wait(40); MM_Wait(40); - - /* Always enable magic packet wake-up if we have vaux. */ - if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && - (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) - { - Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; - } - - REG_WR(pDevice, MacCtrl.Mode, Value32); - - /* Enable the receiver. */ - REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); + /* Enable WOL. */ + LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a); + MM_Wait(40); + + /* Set LED mode. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = LED_CTRL_PHY_MODE_1; + } + else + { + if(pDevice->LedMode == LED_MODE_OUTPUT) + { + Value32 = LED_CTRL_PHY_MODE_2; + } + else + { + Value32 = LED_CTRL_PHY_MODE_1; + } + } + + Value32 = MAC_MODE_PORT_MODE_MII; + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) + { + if(pDevice->LedMode == LED_MODE_LINK10 || + pDevice->WolSpeed == WOL_SPEED_10MB) + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + } + else + { + Value32 |= MAC_MODE_LINK_POLARITY; + } + REG_WR(pDevice, MacCtrl.Mode, Value32); + MM_Wait(40); MM_Wait(40); MM_Wait(40); + + /* Always enable magic packet wake-up if we have vaux. */ + if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) && + (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) + { + Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE; + } + + REG_WR(pDevice, MacCtrl.Mode, Value32); + + /* Enable the receiver. */ + REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE); } /* Disable tx/rx clocks, and seletect an alternate clock. */ if(pDevice->WolSpeed == WOL_SPEED_100MB) { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; - } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - - MM_Wait(40); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } - - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); - - MM_Wait(40); - - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_44MHZ_CORE_CLOCK; - } - else - { - Value32 = T3_PCI_44MHZ_CORE_CLOCK; - } - - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK; + } + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + + MM_Wait(40); + + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_44MHZ_CORE_CLOCK; + } + else + { + Value32 = T3_PCI_44MHZ_CORE_CLOCK; + } + + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); } else { - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | - T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; - } - else - { - Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | - T3_PCI_POWER_DOWN_PCI_PLL133; - } + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK | + T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } + else + { + Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK | + T3_PCI_POWER_DOWN_PCI_PLL133; + } - REG_WR(pDevice, PciCfg.ClockCtrl, Value32); + REG_WR(pDevice, PciCfg.ClockCtrl, Value32); } MM_Wait(40); if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) { - /* Switch adapter to auxilliary power. */ - if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || - T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) - { - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); - } - else - { - /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); - MM_Wait(40); - - /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ - REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | - GRC_MISC_LOCAL_CTRL_GPIO_OE0 | - GRC_MISC_LOCAL_CTRL_GPIO_OE1 | - GRC_MISC_LOCAL_CTRL_GPIO_OE2 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | - GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); - MM_Wait(40); - } + /* Switch adapter to auxilliary power. */ + if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 || + T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) + { + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } + else + { + /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2); + MM_Wait(40); + + /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */ + REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl | + GRC_MISC_LOCAL_CTRL_GPIO_OE0 | + GRC_MISC_LOCAL_CTRL_GPIO_OE1 | + GRC_MISC_LOCAL_CTRL_GPIO_OE2 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 | + GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1); + MM_Wait(40); + } } /* Set the phy to low power mode. */ @@ -5603,7 +5584,6 @@ LM_POWER_STATE PowerLevel) { } /* LM_SetPowerState */ - /******************************************************************************/ /* Description: */ /* */ @@ -5619,31 +5599,30 @@ GetPhyAdFlowCntrlSettings( /* Auto negotiation flow control only when autonegotiation is enabled. */ if(pDevice->DisableAutoNeg == FALSE || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || - pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) - { - /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ - if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || - ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && - (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) - { - Value32 |= PHY_AN_AD_ASYM_PAUSE; - } - else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) - { - Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; - } + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO || + pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) + { + /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */ + if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) || + ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) && + (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) + { + Value32 |= PHY_AN_AD_ASYM_PAUSE; + } + else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) + { + Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE; + } } return Value32; } - /******************************************************************************/ /* Description: */ /* */ @@ -5666,184 +5645,183 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType) /* Get the interface type, line speed, and duplex mode. */ LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed, - &DuplexMode); + &DuplexMode); if (pDevice->RestoreOnWakeUp) { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; - if (pDevice->WolSpeed == WOL_SPEED_100MB) - { - Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - } - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF; + if (pDevice->WolSpeed == WOL_SPEED_100MB) + { + Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + } + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; } /* Setup the auto-negotiation advertisement register. */ else if(LineSpeed == LM_LINE_SPEED_UNKNOWN) { - /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | - PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | - PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + /* Setup the 10/100 Mbps auto-negotiation advertisement register. */ + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD | + PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL | + PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; - /* Advertise 1000Mbps */ - Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; + /* Advertise 1000Mbps */ + Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL; #if INCLUDE_5701_AX_FIX - /* Bug: workaround for CRC error in gigabit mode when we are in */ - /* slave mode. This will force the PHY to operate in */ - /* master mode. */ - if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || - pDevice->ChipRevId == T3_CHIP_ID_5701_B0) - { - Value32 |= BCM540X_CONFIG_AS_MASTER | - BCM540X_ENABLE_CONFIG_AS_MASTER; - } + /* Bug: workaround for CRC error in gigabit mode when we are in */ + /* slave mode. This will force the PHY to operate in */ + /* master mode. */ + if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 || + pDevice->ChipRevId == T3_CHIP_ID_5701_B0) + { + Value32 |= BCM540X_CONFIG_AS_MASTER | + BCM540X_ENABLE_CONFIG_AS_MASTER; + } #endif - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; } else { - if(LineSpeed == LM_LINE_SPEED_1000MBPS) - { - Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = BCM540X_AN_AD_1000BASET_HALF; - } - else - { - Value32 = BCM540X_AN_AD_1000BASET_FULL; - } - - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); - pDevice->advertising1000 = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_100MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_100BASETX_HALF; - } - else - { - Value32 = PHY_AN_AD_100BASETX_FULL; - } - - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } - else if(LineSpeed == LM_LINE_SPEED_10MBPS) - { - LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); - pDevice->advertising1000 = 0; - - if(DuplexMode != LM_DUPLEX_MODE_FULL) - { - Value32 = PHY_AN_AD_10BASET_HALF; - } - else - { - Value32 = PHY_AN_AD_10BASET_FULL; - } - - Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; - Value32 |= GetPhyAdFlowCntrlSettings(pDevice); - - LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); - pDevice->advertising = Value32; - } + if(LineSpeed == LM_LINE_SPEED_1000MBPS) + { + Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = BCM540X_AN_AD_1000BASET_HALF; + } + else + { + Value32 = BCM540X_AN_AD_1000BASET_FULL; + } + + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32); + pDevice->advertising1000 = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_100MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_100BASETX_HALF; + } + else + { + Value32 = PHY_AN_AD_100BASETX_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } + else if(LineSpeed == LM_LINE_SPEED_10MBPS) + { + LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0); + pDevice->advertising1000 = 0; + + if(DuplexMode != LM_DUPLEX_MODE_FULL) + { + Value32 = PHY_AN_AD_10BASET_HALF; + } + else + { + Value32 = PHY_AN_AD_10BASET_FULL; + } + + Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD; + Value32 |= GetPhyAdFlowCntrlSettings(pDevice); + + LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32); + pDevice->advertising = Value32; + } } /* Force line speed if auto-negotiation is disabled. */ if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) { - /* This code path is executed only when there is link. */ - pDevice->MediaType = MediaType; - pDevice->LineSpeed = LineSpeed; - pDevice->DuplexMode = DuplexMode; - - /* Force line seepd. */ - NewPhyCtrl = 0; - switch(LineSpeed) - { - case LM_LINE_SPEED_10MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; - break; - case LM_LINE_SPEED_100MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; - break; - case LM_LINE_SPEED_1000MBPS: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; - default: - NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; - break; - } - - if(DuplexMode == LM_DUPLEX_MODE_FULL) - { - NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; - } - - /* Don't do anything if the PHY_CTRL is already what we wanted. */ - LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); - if(Value32 != NewPhyCtrl) - { - /* Temporary bring the link down before forcing line speed. */ - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); - - /* Wait for link to go down. */ - for(Cnt = 0; Cnt < 15000; Cnt++) - { - MM_Wait(10); - - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); - - if(!(Value32 & PHY_STATUS_LINK_PASS)) - { - MM_Wait(40); - break; - } - } - - LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); - MM_Wait(40); - } + /* This code path is executed only when there is link. */ + pDevice->MediaType = MediaType; + pDevice->LineSpeed = LineSpeed; + pDevice->DuplexMode = DuplexMode; + + /* Force line seepd. */ + NewPhyCtrl = 0; + switch(LineSpeed) + { + case LM_LINE_SPEED_10MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS; + break; + case LM_LINE_SPEED_100MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS; + break; + case LM_LINE_SPEED_1000MBPS: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + default: + NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS; + break; + } + + if(DuplexMode == LM_DUPLEX_MODE_FULL) + { + NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE; + } + + /* Don't do anything if the PHY_CTRL is already what we wanted. */ + LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32); + if(Value32 != NewPhyCtrl) + { + /* Temporary bring the link down before forcing line speed. */ + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE); + + /* Wait for link to go down. */ + for(Cnt = 0; Cnt < 15000; Cnt++) + { + MM_Wait(10); + + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32); + + if(!(Value32 & PHY_STATUS_LINK_PASS)) + { + MM_Wait(40); + break; + } + } + + LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl); + MM_Wait(40); + } } else { - LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | - PHY_CTRL_RESTART_AUTO_NEG); + LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE | + PHY_CTRL_RESTART_AUTO_NEG); } return LM_STATUS_SUCCESS; } /* LM_ForceAutoNegBcm540xPhy */ - /******************************************************************************/ /* Description: */ /* */ @@ -5859,18 +5837,18 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType) /* Initialize the phy chip. */ switch(pDevice->PhyId & PHY_ID_MASK) { - case PHY_BCM5400_PHY_ID: - case PHY_BCM5401_PHY_ID: - case PHY_BCM5411_PHY_ID: - case PHY_BCM5701_PHY_ID: - case PHY_BCM5703_PHY_ID: - case PHY_BCM5704_PHY_ID: - LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); - break; + case PHY_BCM5400_PHY_ID: + case PHY_BCM5401_PHY_ID: + case PHY_BCM5411_PHY_ID: + case PHY_BCM5701_PHY_ID: + case PHY_BCM5703_PHY_ID: + case PHY_BCM5704_PHY_ID: + LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType); + break; - default: - LmStatus = LM_STATUS_FAILURE; - break; + default: + LmStatus = LM_STATUS_FAILURE; + break; } return LmStatus; @@ -5882,123 +5860,123 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType) /* Return: */ /******************************************************************************/ LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, - PT3_FWIMG_INFO pFwImg, - LM_UINT32 LoadCpu, - LM_UINT32 StartCpu) + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, + LM_UINT32 StartCpu) { LM_UINT32 i; LM_UINT32 address; if (LoadCpu & T3_RX_CPU_ID) { - if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } - - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); - } - - /* Copy code first */ - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i = 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); - } - - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); - } - - address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); - } + if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i = 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } } if (LoadCpu & T3_TX_CPU_ID) { - if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) - { - return LM_STATUS_FAILURE; - } - - /* First of all clear scrach pad memory */ - for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) - { - LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); - } - - /* Copy code first */ - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); - for (i= 0; i <= pFwImg->Text.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); - } - - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); - for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); - } - - address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); - for (i= 0; i <= pFwImg->Data.Length; i+=4) - { - LM_RegWrInd(pDevice,address+i, - ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); - } + if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS) + { + return LM_STATUS_FAILURE; + } + + /* First of all clear scrach pad memory */ + for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4) + { + LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0); + } + + /* Copy code first */ + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff); + for (i= 0; i <= pFwImg->Text.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff); + for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]); + } + + address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff); + for (i= 0; i <= pFwImg->Data.Length; i+=4) + { + LM_RegWrInd(pDevice,address+i, + ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]); + } } if (StartCpu & T3_RX_CPU_ID) { - /* Start Rx CPU */ - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) - break; + /* Start Rx CPU */ + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC)) + break; - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); - } + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode, 0); + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode, 0); } if (StartCpu & T3_TX_CPU_ID) { - /* Start Tx CPU */ - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - for (i = 0 ; i < 5; i++) - { - if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) - break; + /* Start Tx CPU */ + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + for (i = 0 ; i < 5; i++) + { + if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC)) + break; - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); - REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); - MM_Wait(1000); - } + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress); + MM_Wait(1000); + } - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode, 0); + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode, 0); } return LM_STATUS_SUCCESS; @@ -6010,29 +5988,29 @@ STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number) if (cpu_number == T3_RX_CPU_ID) { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) - break; - } + if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT) + break; + } - REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); - REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); - MM_Wait(10); + REG_WR(pDevice,rxCpu.reg.state, 0xffffffff); + REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT); + MM_Wait(10); } else { - for (i = 0 ; i < 10000; i++) - { - REG_WR(pDevice,txCpu.reg.state, 0xffffffff); - REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); + for (i = 0 ; i < 10000; i++) + { + REG_WR(pDevice,txCpu.reg.state, 0xffffffff); + REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT); - if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) - break; - } + if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT) + break; + } } return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS); @@ -6049,10 +6027,10 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) if(BlinkDurationSec == 0) { return 0; - } + } if(BlinkDurationSec > 120) - { - BlinkDurationSec = 120; + { + BlinkDurationSec = 120; } Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl); @@ -6060,7 +6038,7 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) { if(j % 2) { - /* Turn on the LEDs. */ + /* Turn on the LEDs. */ REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_1000MBPS_LED_ON | @@ -6072,20 +6050,20 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) } else { - /* Turn off the LEDs. */ + /* Turn off the LEDs. */ REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED | LED_CTRL_OVERRIDE_TRAFFIC_LED); } #ifndef EMBEDDED - current->state = TASK_INTERRUPTIBLE; - if (schedule_timeout(HZ/2) != 0) { - ret = -EINTR; - break; - } + current->state = TASK_INTERRUPTIBLE; + if (schedule_timeout(HZ/2) != 0) { + ret = -EINTR; + break; + } #else - udelay(100000); /* 1s sleep */ + udelay(100000); /* 1s sleep */ #endif } REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg); @@ -6093,8 +6071,8 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec) } int t3_do_dma(PLM_DEVICE_BLOCK pDevice, - LM_PHYSICAL_ADDRESS host_addr_phy, int length, - int dma_read) + LM_PHYSICAL_ADDRESS host_addr_phy, int length, + int dma_read) { T3_DMA_DESC dma_desc; int i; @@ -6112,15 +6090,15 @@ int t3_do_dma(PLM_DEVICE_BLOCK pDevice, if (dma_read) { - dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | - T3_QID_DMA_HIGH_PRI_READ; - REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); + dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) | + T3_QID_DMA_HIGH_PRI_READ; + REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE); } else { - dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | - T3_QID_DMA_HIGH_PRI_WRITE; - REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); + dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) | + T3_QID_DMA_HIGH_PRI_WRITE; + REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE); } dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR; @@ -6128,28 +6106,28 @@ int t3_do_dma(PLM_DEVICE_BLOCK pDevice, /* Writing this DMA descriptor to DMA memory */ for (i = 0; i < sizeof(T3_DMA_DESC); i += 4) { - value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); - MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); + value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i)); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i); + MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32)); } MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0); if (dma_read) - REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); + REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr); else - REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); + REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr); for (i = 0; i < 40; i++) { - if (dma_read) - value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); - else - value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); + if (dma_read) + value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue); + else + value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue); - if ((value32 & 0xffff) == dma_desc_addr) - break; + if ((value32 & 0xffff) == dma_desc_addr) + break; - MM_Wait(10); + MM_Wait(10); } return LM_STATUS_SUCCESS; @@ -6157,65 +6135,65 @@ int t3_do_dma(PLM_DEVICE_BLOCK pDevice, STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt, - LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) + LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize) { int j; LM_UINT32 *ptr; int dma_success = 0; if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 && - T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) + T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701) { - return LM_STATUS_SUCCESS; + return LM_STATUS_SUCCESS; } while (!dma_success) { - /* Fill data with incremental patterns */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - *ptr++ = j; - - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; - } - - MM_Wait(40); - ptr = (LM_UINT32 *)pBufferVirt; - /* Fill data with zero */ - for (j = 0; j < BufferSize/4; j++) - *ptr++ = 0; - - if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) - { - return LM_STATUS_FAILURE; - } - - MM_Wait(40); - /* Check for data */ - ptr = (LM_UINT32 *)pBufferVirt; - for (j = 0; j < BufferSize/4; j++) - { - if (*ptr++ != j) - { - if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) - == DMA_CTRL_WRITE_BOUNDARY_DISABLE) - { - pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & - ~DMA_CTRL_WRITE_BOUNDARY_MASK) | - DMA_CTRL_WRITE_BOUNDARY_16; - REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, - pDevice->DmaReadWriteCtrl); - break; - } - else - { - return LM_STATUS_FAILURE; - } - } - } - if (j == (BufferSize/4)) - dma_success = 1; + /* Fill data with incremental patterns */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + *ptr++ = j; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + ptr = (LM_UINT32 *)pBufferVirt; + /* Fill data with zero */ + for (j = 0; j < BufferSize/4; j++) + *ptr++ = 0; + + if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE) + { + return LM_STATUS_FAILURE; + } + + MM_Wait(40); + /* Check for data */ + ptr = (LM_UINT32 *)pBufferVirt; + for (j = 0; j < BufferSize/4; j++) + { + if (*ptr++ != j) + { + if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK) + == DMA_CTRL_WRITE_BOUNDARY_DISABLE) + { + pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl & + ~DMA_CTRL_WRITE_BOUNDARY_MASK) | + DMA_CTRL_WRITE_BOUNDARY_16; + REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, + pDevice->DmaReadWriteCtrl); + break; + } + else + { + return LM_STATUS_FAILURE; + } + } + } + if (j == (BufferSize/4)) + dma_success = 1; } return LM_STATUS_SUCCESS; } diff --git a/drivers/tigon3.h b/drivers/tigon3.h index 8d30ac933..ea4367d61 100644 --- a/drivers/tigon3.h +++ b/drivers/tigon3.h @@ -25,9 +25,9 @@ /* io defines */ #if !defined(BIG_ENDIAN_HOST) #define readl(addr) \ - (LONGSWAP((*(volatile unsigned int *)(addr)))) + (LONGSWAP((*(volatile unsigned int *)(addr)))) #define writel(b,addr) \ - ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) + ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b))) #else #if 0 /* !defined(PPC603) */ #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr))) @@ -56,8 +56,6 @@ static __inline void writel(unsigned int b, unsigned int addr){ #endif - - /******************************************************************************/ /* Constants. */ /******************************************************************************/ @@ -95,7 +93,7 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define BCM5700_BX_MIN_FRAG_BUF_SIZE 16 /* nice aligned size. */ #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK (BCM5700_BX_MIN_FRAG_BUF_SIZE-1) #define BCM5700_BX_TX_COPY_BUF_SIZE (BCM5700_BX_MIN_FRAG_BUF_SIZE * \ - MAX_FRAGMENT_COUNT) + MAX_FRAGMENT_COUNT) /* MAGIC number. */ /* #define T3_MAGIC_NUM 'KevT' */ @@ -259,13 +257,13 @@ static __inline void writel(unsigned int b, unsigned int addr){ #define T3_NIC_MINI_RCV_BUFFER_DESC_ADDR_EXT_MEM 0xe000 #define T3_NIC_SND_BUFFER_DESC_SIZE (T3_SEND_RCB_ENTRY_COUNT * \ - sizeof(T3_SND_BD) / 4) + sizeof(T3_SND_BD) / 4) #define T3_NIC_STD_RCV_BUFFER_DESC_SIZE (T3_STD_RCV_RCB_ENTRY_COUNT * \ - sizeof(T3_RCV_BD) / 4) + sizeof(T3_RCV_BD) / 4) #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \ - sizeof(T3_EXT_RCV_BD) / 4) + sizeof(T3_EXT_RCV_BD) / 4) /* MBUF pool. */ @@ -321,7 +319,6 @@ typedef struct T3_FWIMG_INFO } T3_FWIMG_INFO, *PT3_FWIMG_INFO; - /******************************************************************************/ /* Tigon3 PCI Registers. */ /******************************************************************************/ @@ -534,7 +531,6 @@ typedef struct T3_FWIMG_INFO #define PHY_AN_EXPANSION_REG 0x06 - /******************************************************************************/ /* BCM5400 and BCM5401 phy info. */ /******************************************************************************/ @@ -559,17 +555,16 @@ typedef struct T3_FWIMG_INFO #define PHY_ID_MODEL_MASK 0x000003f0 #define PHY_ID_REV_MASK 0x0000000f #define PHY_ID_MASK (PHY_ID_OUI_MASK | \ - PHY_ID_MODEL_MASK) + PHY_ID_MODEL_MASK) #define UNKNOWN_PHY_ID(x) ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ - (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) - + (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5701_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5703_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \ + (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID)) /* 1000Base-T control register. */ @@ -697,7 +692,6 @@ typedef struct T3_FWIMG_INFO #define BCM540X_INT_MASK_REG 0x1b - /******************************************************************************/ /* Register definitions. */ /******************************************************************************/ @@ -730,7 +724,6 @@ typedef struct }T3_DMA_DESC, *PT3_DMA_DESC; - /******************************************************************************/ /* Ring control block. */ /******************************************************************************/ @@ -739,17 +732,17 @@ typedef struct { T3_64BIT_REGISTER HostRingAddr; union { - struct { + struct { #ifdef BIG_ENDIAN_HOST - T3_16BIT_REGISTER MaxLen; - T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; #else /* BIG_ENDIAN_HOST */ - T3_16BIT_REGISTER Flags; - T3_16BIT_REGISTER MaxLen; + T3_16BIT_REGISTER Flags; + T3_16BIT_REGISTER MaxLen; #endif - } s; + } s; - T3_32BIT_REGISTER MaxLen_Flags; + T3_32BIT_REGISTER MaxLen_Flags; } u; T3_32BIT_REGISTER NicRingAddr; @@ -759,7 +752,6 @@ typedef struct { #define T3_RCB_FLAG_RING_DISABLED BIT_1 - /******************************************************************************/ /* Status block. */ /******************************************************************************/ @@ -786,8 +778,8 @@ typedef struct { volatile LM_UINT16 RcvMiniConIdx; struct { - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ } Idx[16]; #else /* BIG_ENDIAN_HOST */ volatile LM_UINT16 RcvJumboConIdx; @@ -797,14 +789,13 @@ typedef struct { volatile LM_UINT16 Reserved2; struct { - volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ - volatile LM_UINT16 SendConIdx; /* Send consumer index. */ + volatile LM_UINT16 RcvProdIdx; /* Receive producer index. */ + volatile LM_UINT16 SendConIdx; /* Send consumer index. */ } Idx[16]; #endif } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK; - /******************************************************************************/ /* Receive buffer descriptors. */ /******************************************************************************/ @@ -887,7 +878,6 @@ typedef struct { #define RCV_BD_FLAG_TCP_PACKET 0x4000 - /******************************************************************************/ /* Send buffer descriptor. */ /******************************************************************************/ @@ -896,31 +886,31 @@ typedef struct { T3_64BIT_HOST_ADDR HostAddr; union { - struct { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Len; - LM_UINT16 Flags; + LM_UINT16 Len; + LM_UINT16 Flags; #else /* BIG_ENDIAN_HOST */ - LM_UINT16 Flags; - LM_UINT16 Len; + LM_UINT16 Flags; + LM_UINT16 Len; #endif - } s1; + } s1; - LM_UINT32 Len_Flags; + LM_UINT32 Len_Flags; } u1; union { - struct { + struct { #ifdef BIG_ENDIAN_HOST - LM_UINT16 Reserved; - LM_UINT16 VlanTag; + LM_UINT16 Reserved; + LM_UINT16 VlanTag; #else /* BIG_ENDIAN_HOST */ - LM_UINT16 VlanTag; - LM_UINT16 Reserved; + LM_UINT16 VlanTag; + LM_UINT16 Reserved; #endif - } s2; + } s2; - LM_UINT32 VlanTag; + LM_UINT32 VlanTag; } u2; } T3_SND_BD, *PT3_SND_BD; @@ -1116,7 +1106,6 @@ typedef struct T3_MBUF #define T3_MBUF_END ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7) - /******************************************************************************/ /* Statistics block. */ /******************************************************************************/ @@ -1221,7 +1210,6 @@ typedef struct { } T3_STATS_BLOCK, *PT3_STATS_BLOCK; - /******************************************************************************/ /* PCI configuration registers. */ /******************************************************************************/ @@ -1463,8 +1451,8 @@ typedef struct { /* MAC addresses. */ struct { - T3_32BIT_REGISTER High; /* Upper 2 bytes. */ - T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ + T3_32BIT_REGISTER High; /* Upper 2 bytes. */ + T3_32BIT_REGISTER Low; /* Lower 4 bytes. */ } MacAddr[4]; /* ACPI Mbuf pointer. */ @@ -1578,8 +1566,8 @@ typedef struct { /* Receive placement rules registers. */ struct { - T3_32BIT_REGISTER Rule; - T3_32BIT_REGISTER Value; + T3_32BIT_REGISTER Rule; + T3_32BIT_REGISTER Value; } RcvRules[16]; #define RCV_DISABLE_RULE_MASK 0x7fffffff @@ -1623,7 +1611,6 @@ typedef struct { } T3_MAC_CONTROL, *PT3_MAC_CONTROL; - /******************************************************************************/ /* Send data initiator control registers. */ /******************************************************************************/ @@ -1665,7 +1652,6 @@ typedef struct { } T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR; - /******************************************************************************/ /* Send data completion control registers. */ /******************************************************************************/ @@ -1680,7 +1666,6 @@ typedef struct { } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION; - /******************************************************************************/ /* Send BD Ring Selector Control Registers. */ /******************************************************************************/ @@ -1707,7 +1692,6 @@ typedef struct { } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR; - /******************************************************************************/ /* Send BD initiator control registers. */ /******************************************************************************/ @@ -1729,7 +1713,6 @@ typedef struct { } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR; - /******************************************************************************/ /* Send BD Completion Control. */ /******************************************************************************/ @@ -1745,7 +1728,6 @@ typedef struct { } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION; - /******************************************************************************/ /* Receive list placement control registers. */ /******************************************************************************/ @@ -1792,12 +1774,12 @@ typedef struct { LM_UINT8 Unused1[224]; struct { - T3_32BIT_REGISTER Head; - T3_32BIT_REGISTER Tail; - T3_32BIT_REGISTER Count; + T3_32BIT_REGISTER Head; + T3_32BIT_REGISTER Tail; + T3_32BIT_REGISTER Count; - /* Unused space. */ - LM_UINT8 Unused[4]; + /* Unused space. */ + LM_UINT8 Unused[4]; } RcvSelectorList[16]; /* Local statistics counter. */ @@ -1816,7 +1798,6 @@ typedef struct { } T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT; - /******************************************************************************/ /* Receive Data and Receive BD Initiator Control. */ /******************************************************************************/ @@ -1867,7 +1848,6 @@ typedef struct { } T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR; - /******************************************************************************/ /* Receive Data Completion Control Registes. */ /******************************************************************************/ @@ -1883,7 +1863,6 @@ typedef struct { } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION; - /******************************************************************************/ /* Receive BD Initiator Control. */ /******************************************************************************/ @@ -1910,7 +1889,6 @@ typedef struct { } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR; - /******************************************************************************/ /* Receive BD Completion Control Registers. */ /******************************************************************************/ @@ -1933,7 +1911,6 @@ typedef struct { } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION; - /******************************************************************************/ /* Receive list selector control register. */ /******************************************************************************/ @@ -1952,7 +1929,6 @@ typedef struct { } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR; - /******************************************************************************/ /* Mbuf cluster free registers. */ /******************************************************************************/ @@ -1969,7 +1945,6 @@ typedef struct { } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE; - /******************************************************************************/ /* Host coalescing control registers. */ /******************************************************************************/ @@ -2056,7 +2031,6 @@ typedef struct { } T3_HOST_COALESCING, *PT3_HOST_COALESCING; - /******************************************************************************/ /* Memory arbiter registers. */ /******************************************************************************/ @@ -2076,7 +2050,6 @@ typedef struct { } T3_MEM_ARBITER, *PT3_MEM_ARBITER; - /******************************************************************************/ /* Buffer manager control register. */ /******************************************************************************/ @@ -2122,7 +2095,6 @@ typedef struct { } T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER; - /******************************************************************************/ /* Read DMA control registers. */ /******************************************************************************/ @@ -2215,7 +2187,6 @@ typedef struct { } T3_DMA_WRITE, *PT3_DMA_WRITE; - /******************************************************************************/ /* Mailbox registers. */ /******************************************************************************/ @@ -2358,7 +2329,6 @@ typedef struct { } T3_FTQ, *PT3_FTQ; - /******************************************************************************/ /* Message signaled interrupt registers. */ /******************************************************************************/ @@ -2376,7 +2346,6 @@ typedef struct { } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT; - /******************************************************************************/ /* DMA Completion registes. */ /******************************************************************************/ @@ -2391,7 +2360,6 @@ typedef struct { } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION; - /******************************************************************************/ /* GRC registers. */ /******************************************************************************/ @@ -2603,7 +2571,6 @@ typedef struct { } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM; - /******************************************************************************/ /* Memory layout. */ /******************************************************************************/ @@ -2705,12 +2672,12 @@ typedef struct { /* Address register. This register is located */ /* in the PCI configuration space. */ union { /* 0x8000 */ - T3_FIRST_32K_SRAM First32k; + T3_FIRST_32K_SRAM First32k; - /* Use the memory window base address register to determine the */ - /* MBUF segment. */ - LM_UINT32 Mbuf[32768/4]; - LM_UINT32 MemBlock32K[32768/4]; + /* Use the memory window base address register to determine the */ + /* MBUF segment. */ + LM_UINT32 Mbuf[32768/4]; + LM_UINT32 MemBlock32K[32768/4]; } uIntMem; } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP; @@ -2736,7 +2703,6 @@ DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT); DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT); - /******************************************************************************/ /* Tx counters. */ /******************************************************************************/ @@ -2752,7 +2718,6 @@ typedef struct { } LM_TX_COUNTERS, *PLM_TX_COUNTERS; - /******************************************************************************/ /* Rx counters. */ /******************************************************************************/ @@ -2773,7 +2738,6 @@ typedef struct { } LM_RX_COUNTERS, *PLM_RX_COUNTERS; - /******************************************************************************/ /* Receive producer rings. */ /******************************************************************************/ @@ -2786,7 +2750,6 @@ typedef enum { } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING; - /******************************************************************************/ /* Packet descriptor. */ /******************************************************************************/ @@ -2806,31 +2769,30 @@ typedef struct _LM_PACKET { LM_UINT16 VlanTag; union { - /* Send info. */ - struct { - /* Set up by UM. */ - LM_UINT32 FragCount; + /* Send info. */ + struct { + /* Set up by UM. */ + LM_UINT32 FragCount; - } Tx; + } Tx; - /* Receive info. */ - struct { - /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ - T3_RCV_PROD_RING RcvProdRing; + /* Receive info. */ + struct { + /* This descriptor belongs to either Std, Mini, or Jumbo ring. */ + T3_RCV_PROD_RING RcvProdRing; - /* Receive buffer size */ - LM_UINT32 RxBufferSize; + /* Receive buffer size */ + LM_UINT32 RxBufferSize; - /* Checksum information. */ - LM_UINT16 IpChecksum; - LM_UINT16 TcpUdpChecksum; + /* Checksum information. */ + LM_UINT16 IpChecksum; + LM_UINT16 TcpUdpChecksum; - } Rx; + } Rx; } u; } LM_PACKET; - /******************************************************************************/ /* Tigon3 device block. */ /******************************************************************************/ @@ -3322,9 +3284,9 @@ typedef struct _LM_DEVICE_BLOCK { #define T3_QID_SW_TYPE2 17 LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice, - PT3_FWIMG_INFO pFwImg, - LM_UINT32 LoadCpu, - LM_UINT32 StartCpu); + PT3_FWIMG_INFO pFwImg, + LM_UINT32 LoadCpu, + LM_UINT32 StartCpu); /******************************************************************************/ /* NIC register read/write macros. */ @@ -3427,19 +3389,19 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, #define MB_REG_WR(pDevice, OffsetName, Value32) \ ((pDevice)->UndiFix) ? \ - LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ - Value32) : \ - (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) + LM_RegWrInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600, \ + Value32) : \ + (void) __raw_writel(Value32, &((pDevice)->pMemView->OffsetName)) #define MB_REG_RD(pDevice, OffsetName) \ (((pDevice)->UndiFix) ? \ - LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ - __raw_readl(&((pDevice)->pMemView->OffsetName))) + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)+0x5600) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) #define REG_RD(pDevice, OffsetName) \ (((pDevice)->UndiFix) ? \ - LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ - __raw_readl(&((pDevice)->pMemView->OffsetName))) + LM_RegRdInd(pDevice, OFFSETOF(T3_STD_MEM_MAP, OffsetName)) : \ + __raw_readl(&((pDevice)->pMemView->OffsetName))) #if PCIX_TARGET_WORKAROUND @@ -3466,4 +3428,3 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_MemWrInd(pDevice, Offset, Value32) #endif /* TIGON3_H */ - |