diff options
| author | Bartlomiej Sieka <tur@semihalf.com> | 2007-05-27 16:53:43 +0200 |
|---|---|---|
| committer | Bartlomiej Sieka <tur@semihalf.com> | 2007-05-27 16:53:43 +0200 |
| commit | c99512d6bd3973f01ca2fc4896d829b46e68f150 (patch) | |
| tree | 9176361a99a43d6ed13690d6242be536379b0bc8 /include/configs/o2dnt.h | |
| parent | a11c0b85dc3664bb3c1e781137118730c8f619ab (diff) | |
MPC5xxx: Change names of defines related to IPB and PCI clocks.
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Diffstat (limited to 'include/configs/o2dnt.h')
| -rw-r--r-- | include/configs/o2dnt.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 5c05a745d..63d0da7d0 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -137,17 +137,17 @@ /* * IPB Bus clocking configuration. */ -#define CFG_IPBSPEED_133 /* define for 133MHz speed */ +#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ -#if defined(CFG_IPBSPEED_133) +#if defined(CFG_IPBCLK_EQUALS_XLBCLK) /* * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't - * been tested with a IPB Bus Clock of 66 MHz. + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ -#define CFG_PCISPEED_66 /* define for 66MHz speed */ +#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ #endif #endif @@ -276,7 +276,7 @@ #define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#ifdef CFG_PCISPEED_66 +#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* * For 66 MHz PCI clock additional Wait State is needed for CS0 (flash). */ |