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authorStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
committerStefan Roese <sr@denx.de>2008-10-21 11:43:08 +0200
commitf61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch)
treeab90f076f18e56b2b3e8c9375b95917daa78c1d9 /include/ppc4xx.h
parentec081c2c190148b374e86a795fb6b1c49caeb549 (diff)
parentf82642e33899766892499b163e60560fbbf87773 (diff)
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/ppc4xx.h')
-rw-r--r--include/ppc4xx.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index e216663a8..ce4b29a19 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -107,8 +107,8 @@
* Enable long long (%ll ...) printf format on 440 PPC's since most of
* them support 36bit physical addressing
*/
-#define CFG_64BIT_VSPRINTF
-#define CFG_64BIT_STRTOUL
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
#include <ppc440.h>
#else
#include <ppc405.h>
@@ -143,7 +143,7 @@
#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
#define RESET_VECTOR 0xfffffffc
-#define CACHELINE_MASK (CFG_CACHELINE_SIZE - 1) /* Address mask for cache
+#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache
line aligned data. */
#define CPR0_DCR_BASE 0x0C