diff options
| author | Grant Erickson <gerickson@nuovations.com> | 2008-07-08 08:35:00 -0700 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-07-11 13:18:13 +0200 |
| commit | 1740c1bf40e3c6d03ac16c29943fdd9fc1e87038 (patch) | |
| tree | b5a0baae4cc93b5d36e34dfaf42989eee3a704b6 /include | |
| parent | 2e2050842e731c823ce8d41fb0c15579eb70ced9 (diff) | |
ppc4xx: Add MII mode support to the EMAC RGMII Bridge
This patch adds support for placing the RGMII bridge on the
PPC405EX(r) into MII/GMII mode and allows a board-specific
configuration to specify the bridge mode at compile-time.
Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/kilauea.h | 1 | ||||
| -rw-r--r-- | include/configs/makalu.h | 1 | ||||
| -rw-r--r-- | include/ppc4xx_enet.h | 16 |
3 files changed, 17 insertions, 1 deletions
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index f3d048cb7..dc246fd23 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -375,6 +375,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/configs/makalu.h b/include/configs/makalu.h index 65b240e0f..ab92ae488 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -223,6 +223,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_M88E1111_PHY 1 #define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII #define CONFIG_PHY_ADDR 6 /* PHY address, See schematics */ #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 4c97b36c0..b74c6fcaf 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -153,6 +153,20 @@ typedef struct emac_4xx_hw_st { #define SDR0_PFC1_EM_1000 (0x00200000) #endif +/* + * XMII bridge configurations for those systems (e.g. 405EX(r)) that do + * not have a pin function control (PFC) register to otherwise determine + * the bridge configuration. + */ +#define EMAC_PHY_MODE_NONE 0 +#define EMAC_PHY_MODE_NONE_RGMII 1 +#define EMAC_PHY_MODE_RGMII_NONE 2 +#define EMAC_PHY_MODE_RGMII_RGMII 3 +#define EMAC_PHY_MODE_NONE_GMII 4 +#define EMAC_PHY_MODE_GMII_NONE 5 +#define EMAC_PHY_MODE_NONE_MII 6 +#define EMAC_PHY_MODE_MII_NONE 7 + /* ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -218,12 +232,12 @@ typedef struct emac_4xx_hw_st { #endif /* RGMII Function Enable (FER) Register Bit Definitions */ -/* Note: for EMAC 2 and 3 only, 440GX only */ #define RGMII_FER_DIS (0x00) #define RGMII_FER_RTBI (0x04) #define RGMII_FER_RGMII (0x05) #define RGMII_FER_TBI (0x06) #define RGMII_FER_GMII (0x07) +#define RGMII_FER_MII (RGMII_FER_GMII) #define RGMII_FER_V(__x) ((__x - 2) * 4) |