diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2009-02-06 08:08:06 -0600 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2009-02-10 00:47:18 +0100 |
| commit | bced7ccefa08512c54a6d146658ff7dbc33d5dfe (patch) | |
| tree | 0f87a4b5540da1d8f3f9c732960699a11cba0337 /lib_ppc/cache.c | |
| parent | 87c9063963561d3d01064be34d0c30855a56587b (diff) | |
ppc: Fix roll over bug in flush_cache()
If we call flush_cache(0xfffff000, 0x1000) it would never
terminate the loop since end = 0xffffffff and we'd roll over
our counter from 0xfffffe0 to 0 (assuming a 32-byte cache line)
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'lib_ppc/cache.c')
| -rw-r--r-- | lib_ppc/cache.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib_ppc/cache.c b/lib_ppc/cache.c index 1292b71e6..338b08bd7 100644 --- a/lib_ppc/cache.c +++ b/lib_ppc/cache.c @@ -33,14 +33,16 @@ void flush_cache(ulong start_addr, ulong size) start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1); end = start_addr + size - 1; - for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { + for (addr = start; (addr <= end) && (addr >= start); + addr += CONFIG_SYS_CACHELINE_SIZE) { asm volatile("dcbst 0,%0" : : "r" (addr) : "memory"); WATCHDOG_RESET(); } /* wait for all dcbst to complete on bus */ asm volatile("sync" : : : "memory"); - for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) { + for (addr = start; (addr <= end) && (addr >= start); + addr += CONFIG_SYS_CACHELINE_SIZE) { asm volatile("icbi 0,%0" : : "r" (addr) : "memory"); WATCHDOG_RESET(); } |