diff options
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 2 | ||||
| -rw-r--r-- | cpu/mpc85xx/spd_sdram.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index fce0c4805..e3240b519 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -272,7 +272,7 @@ int cpu_init_r(void) uint l2srbar; svr = get_svr(); - ver = SVR_VER(svr); + ver = SVR_SOC_VER(svr); asm("msync;isync"); cache_ctl = l2cache->l2ctl; diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c index abc63c414..435458a18 100644 --- a/cpu/mpc85xx/spd_sdram.c +++ b/cpu/mpc85xx/spd_sdram.c @@ -306,7 +306,7 @@ spd_sdram(void) * Adjust DDR II IO voltage biasing. * Only 8548 rev 1 needs the fix */ - if ((SVR_VER(get_svr()) == SVR_8548_E) && + if ((SVR_SOC_VER(get_svr()) == SVR_8548_E) && (SVR_MJREV(get_svr()) == 1) && (spd.mem_type == SPD_MEMTYPE_DDR2)) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); |