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-rw-r--r--board/amcc/bamboo/config.mk4
-rw-r--r--board/amcc/yellowstone/yellowstone.c4
-rw-r--r--board/amcc/yosemite/yosemite.c4
-rw-r--r--board/amcc/yucca/cmd_yucca.c2
-rw-r--r--board/amcc/yucca/flash.c2
-rw-r--r--board/amcc/yucca/init.S2
6 files changed, 9 insertions, 9 deletions
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index 35cb65584..9d7f4c310 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2002
+# (C) Copyright 2002-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0xFFF80000
+TEXT_BASE = 0xFFFA0000
PLATFORM_CPPFLAGS += -DCONFIG_440=1
diff --git a/board/amcc/yellowstone/yellowstone.c b/board/amcc/yellowstone/yellowstone.c
index 86d0db751..92dc9d4c0 100644
--- a/board/amcc/yellowstone/yellowstone.c
+++ b/board/amcc/yellowstone/yellowstone.c
@@ -313,13 +313,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
+ mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 674244155..7f2e71820 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -309,13 +309,13 @@ void sdram_init(void)
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
- mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
+ mtsdram(mem_cfg0, 0x30000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
- mtsdram(mem_cfg0, 0x84000000); /* Enable */
+ mtsdram(mem_cfg0, 0x80000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
diff --git a/board/amcc/yucca/cmd_yucca.c b/board/amcc/yucca/cmd_yucca.c
index 9c7afb263..e698b201f 100644
--- a/board/amcc/yucca/cmd_yucca.c
+++ b/board/amcc/yucca/cmd_yucca.c
@@ -30,7 +30,7 @@
#include <asm/byteorder.h>
extern void print_evb440spe_info(void);
-static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
+static int setBootStrapClock(cmd_tbl_t *cmdtp, int incrflag,
int flag, int argc, char *argv[]);
extern int cmd_get_data_size(char* arg, int default_size);
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index c5a2e31bf..15b8a462b 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -1004,7 +1004,7 @@ unsigned long flash_init(void)
}
} /*else if (index == 0) {*/
/* if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE)*/
-/* index = 8;*//* sram below op code flash -> new index 8*/
+/* index = 8;*/ /* sram below op code flash -> new index 8*/
/* }*/
DEBUGF("\n");
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index 48e2ec277..c9eca686b 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -118,7 +118,7 @@ tlbtabA:
/**************************************************************************
* TLB table for revB
*
- * Notice: revB of the 440SPe chip is very strict about PLB real addressess
+ * Notice: revB of the 440SPe chip is very strict about PLB real addresses
* and ranges to be mapped for config space: it seems to only work with
* d_nnnn_nnnn range (hangs the core upon config transaction attempts when
* set otherwise) while revA uses c_nnnn_nnnn.