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-rw-r--r--board/eric/Makefile2
-rw-r--r--board/eric/flash.c56
-rw-r--r--board/eric/init.S516
-rw-r--r--board/eric/u-boot.lds5
4 files changed, 291 insertions, 288 deletions
diff --git a/board/eric/Makefile b/board/eric/Makefile
index 7a9d25ac4..f55e7e2f8 100644
--- a/board/eric/Makefile
+++ b/board/eric/Makefile
@@ -29,7 +29,7 @@ OBJS = $(BOARD).o flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $^
+ $(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/eric/flash.c b/board/eric/flash.c
index 5dfb620c6..c08a76026 100644
--- a/board/eric/flash.c
+++ b/board/eric/flash.c
@@ -57,8 +57,8 @@ unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
- uint pbcr;
- unsigned long base_b0, base_b1;
+ uint pbcr;
+ unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
@@ -88,9 +88,9 @@ unsigned long flash_init (void)
&flash_info[0]);
#else
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
#endif
size_b1 = 0 ;
flash_info[0].size = size_b0;
@@ -137,9 +137,9 @@ unsigned long flash_init (void)
&flash_info[0]);
#else
(void)flash_protect(FLAG_PROTECT_SET,
- CFG_MONITOR_BASE,
- CFG_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE+monitor_flash_len-1,
+ &flash_info[0]);
#endif
if (size_b1) {
@@ -170,7 +170,6 @@ unsigned long flash_init (void)
}
-
/*-----------------------------------------------------------------------
*/
@@ -186,7 +185,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[i] = base + (i * info->size/info->sector_count);
}
} else if (info->flash_id & FLASH_BTYPE) {
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
#ifndef CFG_FLASH_16BIT
/* set sector offsets for bottom boot block type */
@@ -200,9 +199,9 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[7] = base + 0x0001C000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00020000) - 0x000E0000;
- }
- }
- else {
+ }
+ }
+ else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00008000;
@@ -224,9 +223,9 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[7] = base + 0x0000E000;
for (i = 8; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00070000;
- }
+ }
}
- else {
+ else {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
@@ -240,7 +239,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
- if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
#ifndef CFG_FLASH_16BIT
info->start[i--] = base + info->size - 0x00004000;
@@ -254,7 +253,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[i] = base + i * 0x00020000;
}
- } else {
+ } else {
info->start[i--] = base + info->size - 0x00008000;
info->start[i--] = base + info->size - 0x0000C000;
@@ -275,7 +274,7 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
info->start[i] = base + i * 0x00010000;
}
- } else {
+ } else {
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
@@ -408,8 +407,8 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
/*
* Note: if it is an AMD flash and the word at addr[0000]
- * is 0x00890089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
+ * is 0x00890089 this routine will think it is an Intel
+ * flash device and may(most likely) cause trouble.
*/
addr[0x0000] = 0x00900090;
@@ -421,8 +420,8 @@ ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
/*
* Note: if it is an AMD flash and the word at addr[0000]
- * is 0x0089 this routine will think it is an Intel
- * flash device and may(most likely) cause trouble.
+ * is 0x0089 this routine will think it is an Intel
+ * flash device and may(most likely) cause trouble.
*/
addr[0x0000] = 0x0090;
@@ -631,7 +630,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
if ((info->flash_id == FLASH_UNKNOWN) ||
((info->flash_id > FLASH_AMD_COMP) &&
- ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
+ ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
@@ -1035,13 +1034,13 @@ static int write_word (flash_info_t *info, ulong dest, ulong data)
if( barf ) {
barf >>=16;
} else {
- barf = addr[0] & 0x0000003A;
+ barf = addr[0] & 0x0000003A;
}
printf("\nFlash write error at address %lx\n",(unsigned long)dest);
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
- return(2);
+ return(2);
}
@@ -1074,7 +1073,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
addr[0x0555] = 0x00A0;
} else {
/* intel stuff */
- *addr = 0x00D0;
+ *addr = 0x00D0;
*addr = 0x0040;
}
*((vu_short *)dest) = data;
@@ -1087,7 +1086,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
start = get_timer (0);
if(info->flash_id < FLASH_AMD_COMP) {
- /* AMD stuff */
+ /* AMD stuff */
while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
@@ -1106,7 +1105,7 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
if(barf & 0x0002) printf("Block locked, not erased.\n");
if(barf & 0x0010) printf("Programming error.\n");
if(barf & 0x0008) printf("Vpp Low error.\n");
- return(2);
+ return(2);
}
*addr = 0x00B0;
*addr = 0x0070;
@@ -1127,4 +1126,3 @@ static int write_short (flash_info_t *info, ulong dest, ushort data)
/*-----------------------------------------------------------------------
*/
-
diff --git a/board/eric/init.S b/board/eric/init.S
index bdf90a5f2..9d4e7ff48 100644
--- a/board/eric/init.S
+++ b/board/eric/init.S
@@ -42,169 +42,169 @@
#include <asm/mmu.h>
- .globl ext_bus_cntlr_init
+ .globl ext_bus_cntlr_init
ext_bus_cntlr_init:
- mflr r4 /* save link register */
- bl ..getAddr
+ mflr r4 /* save link register */
+ bl ..getAddr
..getAddr:
- mflr r3 /* get address of ..getAddr */
- mtlr r4 /* restore link register */
- addi r4,0,14 /* set ctr to 10; used to prefetch */
- mtctr r4 /* 10 cache lines to fit this function */
- /* in cache (gives us 8x10=80 instrctns) */
+ mflr r3 /* get address of ..getAddr */
+ mtlr r4 /* restore link register */
+ addi r4,0,14 /* set ctr to 10; used to prefetch */
+ mtctr r4 /* 10 cache lines to fit this function */
+ /* in cache (gives us 8x10=80 instrctns) */
..ebcloop:
- icbt r0,r3 /* prefetch cache line for addr in r3 */
- addi r3,r3,32 /* move to next cache line */
- bdnz ..ebcloop /* continue for 10 cache lines */
+ icbt r0,r3 /* prefetch cache line for addr in r3 */
+ addi r3,r3,32 /* move to next cache line */
+ bdnz ..ebcloop /* continue for 10 cache lines */
- /*------------------------------------------------------------------- */
- /* Delay to ensure all accesses to ROM are complete before changing */
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure all accesses to ROM are complete before changing */
/* bank 0 timings. 200usec should be enough. */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*------------------------------------------------------------------- */
addis r3,0,0x0
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
..spinlp:
- bdnz ..spinlp /* spin loop */
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 0 (Flash) initialization (from openbios) */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb0ap
- mtdcr ebccfga,r4
- addis r4,0,CS0_AP@h
- ori r4,r4,CS0_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb0cr
- mtdcr ebccfga,r4
- addis r4,0,CS0_CR@h
- ori r4,r4,CS0_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 1 (NVRAM/RTC) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb1ap
- mtdcr ebccfga,r4
- addis r4,0,CS1_AP@h
- ori r4,r4,CS1_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb1cr
- mtdcr ebccfga,r4
- addis r4,0,CS1_CR@h
- ori r4,r4,CS1_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 2 (A/D converter) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb2ap
- mtdcr ebccfga,r4
- addis r4,0,CS2_AP@h
- ori r4,r4,CS2_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb2cr
- mtdcr ebccfga,r4
- addis r4,0,CS2_CR@h
- ori r4,r4,CS2_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 3 (Ethernet PHY Reset) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb3ap
- mtdcr ebccfga,r4
- addis r4,0,CS3_AP@h
- ori r4,r4,CS3_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb3cr
- mtdcr ebccfga,r4
- addis r4,0,CS3_CR@h
- ori r4,r4,CS3_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb4ap
- mtdcr ebccfga,r4
- addis r4,0,CS4_AP@h
- ori r4,r4,CS4_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb4cr
- mtdcr ebccfga,r4
- addis r4,0,CS4_CR@h
- ori r4,r4,CS4_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb5ap
- mtdcr ebccfga,r4
- addis r4,0,CS5_AP@h
- ori r4,r4,CS5_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb5cr
- mtdcr ebccfga,r4
- addis r4,0,CS5_CR@h
- ori r4,r4,CS5_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 6 (CPU LED0) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb6ap
- mtdcr ebccfga,r4
- addis r4,0,CS6_AP@h
- ori r4,r4,CS6_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb6cr
- mtdcr ebccfga,r4
- addis r4,0,CS6_CR@h
- ori r4,r4,CS5_CR@l
- mtdcr ebccfgd,r4
-
- /*----------------------------------------------------------------------- */
- /* Memory Bank 7 (CPU LED1) initialization */
- /*----------------------------------------------------------------------- */
-
- addi r4,0,pb7ap
- mtdcr ebccfga,r4
- addis r4,0,CS7_AP@h
- ori r4,r4,CS7_AP@l
- mtdcr ebccfgd,r4
-
- addi r4,0,pb7cr
- mtdcr ebccfga,r4
- addis r4,0,CS7_CR@h
- ori r4,r4,CS7_CR@l
- mtdcr ebccfgd,r4
+ bdnz ..spinlp /* spin loop */
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 0 (Flash) initialization (from openbios) */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb0ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS0_AP@h
+ ori r4,r4,CS0_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb0cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS0_CR@h
+ ori r4,r4,CS0_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 1 (NVRAM/RTC) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb1ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS1_AP@h
+ ori r4,r4,CS1_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb1cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS1_CR@h
+ ori r4,r4,CS1_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 2 (A/D converter) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb2ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS2_AP@h
+ ori r4,r4,CS2_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb2cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS2_CR@h
+ ori r4,r4,CS2_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 3 (Ethernet PHY Reset) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb3ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS3_AP@h
+ ori r4,r4,CS3_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb3cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS3_CR@h
+ ori r4,r4,CS3_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb4ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS4_AP@h
+ ori r4,r4,CS4_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb4cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS4_CR@h
+ ori r4,r4,CS4_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb5ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS5_AP@h
+ ori r4,r4,CS5_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb5cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS5_CR@h
+ ori r4,r4,CS5_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 6 (CPU LED0) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb6ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS6_AP@h
+ ori r4,r4,CS6_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb6cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS6_CR@h
+ ori r4,r4,CS5_CR@l
+ mtdcr ebccfgd,r4
+
+ /*----------------------------------------------------------------------- */
+ /* Memory Bank 7 (CPU LED1) initialization */
+ /*----------------------------------------------------------------------- */
+
+ addi r4,0,pb7ap
+ mtdcr ebccfga,r4
+ addis r4,0,CS7_AP@h
+ ori r4,r4,CS7_AP@l
+ mtdcr ebccfgd,r4
+
+ addi r4,0,pb7cr
+ mtdcr ebccfga,r4
+ addis r4,0,CS7_CR@h
+ ori r4,r4,CS7_CR@l
+ mtdcr ebccfgd,r4
/* addis r4,r0,FPGA_BRDC@h */
-/* ori r4,r4,FPGA_BRDC@l */
-/* lbz r3,0(r4) //get FPGA board control reg */
-/* eieio */
-/* ori r3,r3,0x01 //set UART1 control to select CTS/RTS */
+/* ori r4,r4,FPGA_BRDC@l */
+/* lbz r3,0(r4) /###*get FPGA board control reg */
+/* eieio */
+/* ori r3,r3,0x01 /###*set UART1 control to select CTS/RTS */
/* stb r3,0(r4) */
nop /* pass2 DCR errata #8 */
- blr
+ blr
/*----------------------------------------------------------------------------- */
/* Function: sdram_init */
@@ -213,56 +213,56 @@ ext_bus_cntlr_init:
/* If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
/* It is assumed that a 32MB 12x8(2) SDRAM is used. */
/*----------------------------------------------------------------------------- */
- .globl sdram_init
+ .globl sdram_init
sdram_init:
mflr r31
#ifdef CFG_SDRAM_MANUALLY
- /*------------------------------------------------------------------- */
- /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
- /*------------------------------------------------------------------- */
-
- addi r4,0,mem_mb0cf
- mtdcr memcfga,r4
- addis r4,0,MB0CF@h
- ori r4,r4,MB0CF@l
- mtdcr memcfgd,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
- /*------------------------------------------------------------------- */
-
- addi r4,0,mem_mb1cf
- mtdcr memcfga,r4
- addis r4,0,MB1CF@h
- ori r4,r4,MB1CF@l
- mtdcr memcfgd,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB2CF for bank 2. off */
- /*------------------------------------------------------------------- */
-
- addi r4,0,mem_mb2cf
- mtdcr memcfga,r4
- addis r4,0,MB2CF@h
- ori r4,r4,MB2CF@l
- mtdcr memcfgd,r4
-
- /*------------------------------------------------------------------- */
- /* Set MB3CF for bank 3. off */
- /*------------------------------------------------------------------- */
-
- addi r4,0,mem_mb3cf
- mtdcr memcfga,r4
- addis r4,0,MB3CF@h
- ori r4,r4,MB3CF@l
- mtdcr memcfgd,r4
-
- /*------------------------------------------------------------------- */
- /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
- /* To set the appropriate timings, we need to know the SDRAM speed. */
+ /*------------------------------------------------------------------- */
+ /* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
+ /*------------------------------------------------------------------- */
+
+ addi r4,0,mem_mb0cf
+ mtdcr memcfga,r4
+ addis r4,0,MB0CF@h
+ ori r4,r4,MB0CF@l
+ mtdcr memcfgd,r4
+
+ /*------------------------------------------------------------------- */
+ /* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
+ /*------------------------------------------------------------------- */
+
+ addi r4,0,mem_mb1cf
+ mtdcr memcfga,r4
+ addis r4,0,MB1CF@h
+ ori r4,r4,MB1CF@l
+ mtdcr memcfgd,r4
+
+ /*------------------------------------------------------------------- */
+ /* Set MB2CF for bank 2. off */
+ /*------------------------------------------------------------------- */
+
+ addi r4,0,mem_mb2cf
+ mtdcr memcfga,r4
+ addis r4,0,MB2CF@h
+ ori r4,r4,MB2CF@l
+ mtdcr memcfgd,r4
+
+ /*------------------------------------------------------------------- */
+ /* Set MB3CF for bank 3. off */
+ /*------------------------------------------------------------------- */
+
+ addi r4,0,mem_mb3cf
+ mtdcr memcfga,r4
+ addis r4,0,MB3CF@h
+ ori r4,r4,MB3CF@l
+ mtdcr memcfgd,r4
+
+ /*------------------------------------------------------------------- */
+ /* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
+ /* To set the appropriate timings, we need to know the SDRAM speed. */
/* We can use the PLB speed since the SDRAM speed is the same as */
/* the PLB speed. The PLB speed is the FBK divider times the */
/* 405GP reference clock, which on the Walnut board is 33Mhz. */
@@ -270,86 +270,86 @@ sdram_init:
/* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
/* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
/* maybe 133Mhz. */
- /*------------------------------------------------------------------- */
+ /*------------------------------------------------------------------- */
- mfdcr r5,strap /* determine FBK divider */
- /* via STRAP reg to calc PLB speed. */
- /* SDRAM speed is the same as the PLB */
- /* speed. */
- rlwinm r4,r5,4,0x3 /* get FBK divide bits */
+ mfdcr r5,strap /* determine FBK divider */
+ /* via STRAP reg to calc PLB speed. */
+ /* SDRAM speed is the same as the PLB */
+ /* speed. */
+ rlwinm r4,r5,4,0x3 /* get FBK divide bits */
..chk_66:
- cmpi %cr0,0,r4,0x1
- bne ..chk_100
+ cmpi %cr0,0,r4,0x1
+ bne ..chk_100
addis r6,0,SDTR_66@h /* SDTR1 value for 66Mhz */
ori r6,r6,SDTR_66@l
addis r7,0,RTR_66 /* RTR value for 66Mhz */
- b ..sdram_ok
+ b ..sdram_ok
..chk_100:
- cmpi %cr0,0,r4,0x2
- bne ..chk_133
- addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
- ori r6,r6,SDTR_100@l
- addis r7,0,RTR_100 /* RTR value for 100Mhz */
- b ..sdram_ok
+ cmpi %cr0,0,r4,0x2
+ bne ..chk_133
+ addis r6,0,SDTR_100@h /* SDTR1 value for 100Mhz */
+ ori r6,r6,SDTR_100@l
+ addis r7,0,RTR_100 /* RTR value for 100Mhz */
+ b ..sdram_ok
..chk_133:
- addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
- ori r6,r6,0x4015
- addis r7,0,0x07F0 /* RTR value for 133Mhz */
+ addis r6,0,0x0107 /* SDTR1 value for 133Mhz */
+ ori r6,r6,0x4015
+ addis r7,0,0x07F0 /* RTR value for 133Mhz */
..sdram_ok:
- /*------------------------------------------------------------------- */
- /* Set SDTR1 */
- /*------------------------------------------------------------------- */
- addi r4,0,mem_sdtr1
- mtdcr memcfga,r4
- mtdcr memcfgd,r6
-
- /*------------------------------------------------------------------- */
- /* Set RTR */
- /*------------------------------------------------------------------- */
- addi r4,0,mem_rtr
- mtdcr memcfga,r4
- mtdcr memcfgd,r7
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure 200usec have elapsed since reset. Assume worst */
- /* case that the core is running 200Mhz: */
- /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
- /*------------------------------------------------------------------- */
- addis r3,0,0x0000
- ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
- mtctr r3
+ /*------------------------------------------------------------------- */
+ /* Set SDTR1 */
+ /*------------------------------------------------------------------- */
+ addi r4,0,mem_sdtr1
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r6
+
+ /*------------------------------------------------------------------- */
+ /* Set RTR */
+ /*------------------------------------------------------------------- */
+ addi r4,0,mem_rtr
+ mtdcr memcfga,r4
+ mtdcr memcfgd,r7
+
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure 200usec have elapsed since reset. Assume worst */
+ /* case that the core is running 200Mhz: */
+ /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
+ /*------------------------------------------------------------------- */
+ addis r3,0,0x0000
+ ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
+ mtctr r3
..spinlp2:
- bdnz ..spinlp2 /* spin loop */
+ bdnz ..spinlp2 /* spin loop */
- /*------------------------------------------------------------------- */
- /* Set memory controller options reg, MCOPT1. */
+ /*------------------------------------------------------------------- */
+ /* Set memory controller options reg, MCOPT1. */
/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
/* read/prefetch. */
- /*------------------------------------------------------------------- */
- addi r4,0,mem_mcopt1
- mtdcr memcfga,r4
- addis r4,0,0x8080 /* set DC_EN=1 */
- ori r4,r4,0x0000
- mtdcr memcfgd,r4
-
- /*------------------------------------------------------------------- */
- /* Delay to ensure 10msec have elapsed since reset. This is */
- /* required for the MPC952 to stabalize. Assume worst */
- /* case that the core is running 200Mhz: */
- /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
- /* This delay should occur before accessing SDRAM. */
- /*------------------------------------------------------------------- */
- addis r3,0,0x001E
- ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
- mtctr r3
+ /*------------------------------------------------------------------- */
+ addi r4,0,mem_mcopt1
+ mtdcr memcfga,r4
+ addis r4,0,0x8080 /* set DC_EN=1 */
+ ori r4,r4,0x0000
+ mtdcr memcfgd,r4
+
+ /*------------------------------------------------------------------- */
+ /* Delay to ensure 10msec have elapsed since reset. This is */
+ /* required for the MPC952 to stabalize. Assume worst */
+ /* case that the core is running 200Mhz: */
+ /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
+ /* This delay should occur before accessing SDRAM. */
+ /*------------------------------------------------------------------- */
+ addis r3,0,0x001E
+ ori r3,r3,0x8480 /* ensure 10msec have passed since reset */
+ mtctr r3
..spinlp3:
- bdnz ..spinlp3 /* spin loop */
+ bdnz ..spinlp3 /* spin loop */
#else
/*fixme: do SDRAM Autoconfig from EEPROM here */
#endif
- mtlr r31 /* restore lr */
- blr
+ mtlr r31 /* restore lr */
+ blr
diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds
index e1373fdc8..10f57d849 100644
--- a/board/eric/u-boot.lds
+++ b/board/eric/u-boot.lds
@@ -121,6 +121,11 @@ SECTIONS
_edata = .;
PROVIDE (edata = .);
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 11:22:12 +0000