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-rw-r--r--board/davinci/dm6467evm/dm6467evm.c1
-rw-r--r--board/ep8248/ep8248.c1
-rw-r--r--board/espt/lowlevel_init.S10
-rw-r--r--board/freescale/mpc8569mds/bcsr.h8
-rw-r--r--board/freescale/mpc8569mds/law.c1
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c210
-rw-r--r--board/freescale/mpc8569mds/tlb.c30
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c6
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c20
-rw-r--r--board/freescale/p1_p2_rdb/pci.c4
-rw-r--r--board/freescale/p2020ds/p2020ds.c6
-rw-r--r--board/logicpd/imx27lite/Makefile1
-rw-r--r--board/renesas/sh7785lcr/lowlevel_init.S107
-rw-r--r--board/sbc8548/sbc8548.c4
-rw-r--r--board/xes/xpedite5370/tlb.c13
15 files changed, 312 insertions, 110 deletions
diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c
index 960581824..ac3b28299 100644
--- a/board/davinci/dm6467evm/dm6467evm.c
+++ b/board/davinci/dm6467evm/dm6467evm.c
@@ -28,4 +28,3 @@ int board_init(void)
return 0;
}
-
diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c
index 57d39aa7e..590894371 100644
--- a/board/ep8248/ep8248.c
+++ b/board/ep8248/ep8248.c
@@ -268,4 +268,3 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup( blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
-
diff --git a/board/espt/lowlevel_init.S b/board/espt/lowlevel_init.S
index 7d5d72e12..7f0686c53 100644
--- a/board/espt/lowlevel_init.S
+++ b/board/espt/lowlevel_init.S
@@ -72,15 +72,7 @@ lowlevel_init:
/* set DDR-SDRAM dummy read */
write32 MMSEL_A, MMSEL_D
- mov.l MMSEL_A, r0
- synco
- mov.l @r0, r1
- synco
-
- mov.l CS0_A, r0
- synco
- mov.l @r0, r1
- synco
+ write32 MMSEL_A, CS0_A
/* set DDR-SDRAM bus/endian etc */
write32 MIM_U_A, MIM_U_D
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
index c4738d734..091b69c8d 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -33,7 +33,8 @@
#define BCSR6_UPC1_POS_EN 0x40
#define BCSR6_UPC1_ADDR_EN 0x20
#define BCSR6_UPC1_DEV2 0x10
-#define BCSR6_SD_ENABLE 0x04
+#define BCSR6_SD_CARD_1BIT 0x08
+#define BCSR6_SD_CARD_4BITS 0x04
#define BCSR6_TDM2G_EN 0x02
#define BCSR6_UCC7_RMII_EN 0x01
@@ -67,9 +68,14 @@
#define BCSR15_SMII6_DIS 0x08
#define BCSR15_SMII8_DIS 0x04
+#define BCSR15_QEUART_EN 0x01
#define BCSR16_UPC1_DEV2 0x02
+#define BCSR17_nUSBEN 0x80
+#define BCSR17_nUSBLOWSPD 0x40
+#define BCSR17_USBVCC 0x20
+#define BCSR17_USBMODE 0x10
#define BCSR17_FLASH_nWP 0x01
/*BCSR Utils functions*/
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
index e7381aae6..60eea45a8 100644
--- a/board/freescale/mpc8569mds/law.c
+++ b/board/freescale/mpc8569mds/law.c
@@ -54,6 +54,7 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_SRIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index cc8873117..cdd781301 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -23,6 +23,7 @@
*/
#include <common.h>
+#include <hwconfig.h>
#include <pci.h>
#include <asm/processor.h>
#include <asm/mmu.h>
@@ -35,6 +36,7 @@
#include <ioports.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <fsl_esdhc.h>
#include "bcsr.h"
@@ -152,6 +154,27 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{5, 10, 2, 0, 3}, /* UART1_CTS_B */
{5, 11, 1, 0, 2}, /* UART1_RTS_B */
+ /* QE UART */
+ {0, 19, 1, 0, 2}, /* QEUART_TX */
+ {1, 17, 2, 0, 3}, /* QEUART_RX */
+ {0, 25, 1, 0, 1}, /* QEUART_RTS */
+ {1, 23, 2, 0, 1}, /* QEUART_CTS */
+
+ /* QE USB */
+ {5, 3, 1, 0, 1}, /* USB_OE */
+ {5, 4, 1, 0, 2}, /* USB_TP */
+ {5, 5, 1, 0, 2}, /* USB_TN */
+ {5, 6, 2, 0, 2}, /* USB_RP */
+ {5, 7, 2, 0, 1}, /* USB_RX */
+ {5, 8, 2, 0, 1}, /* USB_RN */
+ {2, 4, 2, 0, 2}, /* CLK5 */
+
+ /* SPI Flash, M25P40 */
+ {4, 27, 3, 0, 1}, /* SPI_MOSI */
+ {4, 28, 3, 0, 1}, /* SPI_MISO */
+ {4, 29, 3, 0, 1}, /* SPI_CLK */
+ {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
+
{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
};
@@ -303,6 +326,190 @@ local_bus_init(void)
out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
}
+static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
+{
+ const char *status = "disabled";
+ int off;
+ int err;
+
+ off = fdt_path_offset(blob, alias);
+ if (off < 0) {
+ printf("WARNING: could not find %s alias: %s.\n", alias,
+ fdt_strerror(off));
+ return;
+ }
+
+ err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
+ if (err) {
+ printf("WARNING: could not set status for serial0: %s.\n",
+ fdt_strerror(err));
+ return;
+ }
+}
+
+/*
+ * Because of an erratum in prototype boards it is impossible to use eSDHC
+ * without disabling UART0 (which makes it quite easy to 'brick' the board
+ * by simply issung 'setenv hwconfig esdhc', and not able to interact with
+ * U-Boot anylonger).
+ *
+ * So, but default we assume that the board is a prototype, which is a most
+ * safe assumption. There is no way to determine board revision from a
+ * register, so we use hwconfig.
+ */
+
+static int prototype_board(void)
+{
+ if (hwconfig_subarg("board", "rev", NULL))
+ return hwconfig_subarg_cmp("board", "rev", "prototype");
+ return 1;
+}
+
+static int esdhc_disables_uart0(void)
+{
+ return prototype_board() ||
+ hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
+}
+
+static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ const char *devtype = "serial";
+ const char *compat = "ucc_uart";
+ const char *clk = "brg9";
+ u32 portnum = 0;
+ int off = -1;
+
+ if (!hwconfig("qe_uart"))
+ return;
+
+ if (hwconfig("esdhc") && esdhc_disables_uart0()) {
+ printf("QE UART: won't enable with esdhc.\n");
+ return;
+ }
+
+ fdt_board_disable_serial(blob, bd, "serial1");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
+ if (off < 0) {
+ printf("WARNING: unable to fixup device tree for "
+ "QE UART\n");
+ return;
+ }
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
+ continue;
+ break;
+ }
+
+ fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
+ fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
+ fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
+ fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
+
+ setbits_8(&bcsr[15], BCSR15_QEUART_EN);
+}
+
+#ifdef CONFIG_FSL_ESDHC
+
+int board_mmc_init(bd_t *bd)
+{
+ struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+ u8 bcsr6 = BCSR6_SD_CARD_1BIT;
+
+ if (!hwconfig("esdhc"))
+ return 0;
+
+ printf("Enabling eSDHC...\n"
+ " For eSDHC to function, I2C2 ");
+ if (esdhc_disables_uart0()) {
+ printf("and UART0 should be disabled.\n");
+ printf(" Redirecting stderr, stdout and stdin to UART1...\n");
+ console_assign(stderr, "eserial1");
+ console_assign(stdout, "eserial1");
+ console_assign(stdin, "eserial1");
+ printf("Switched to UART1 (initial log has been printed to "
+ "UART0).\n");
+ bcsr6 |= BCSR6_SD_CARD_4BITS;
+ } else {
+ printf("should be disabled.\n");
+ }
+
+ /* Assign I2C2 signals to eSDHC. */
+ clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
+ PLPPAR1_ESDHC_VAL);
+ clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
+ PLPDIR1_ESDHC_VAL);
+
+ /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
+ setbits_8(&bcsr[6], bcsr6);
+
+ return fsl_esdhc_mmc_init(bd);
+}
+
+static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
+{
+ const char *status = "disabled";
+ int off = -1;
+
+ if (!hwconfig("esdhc"))
+ return;
+
+ if (esdhc_disables_uart0())
+ fdt_board_disable_serial(blob, bd, "serial0");
+
+ while (1) {
+ const u32 *idx;
+ int len;
+
+ off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
+ if (off < 0)
+ break;
+
+ idx = fdt_getprop(blob, off, "cell-index", &len);
+ if (!idx || len != sizeof(*idx))
+ continue;
+
+ if (*idx == 1) {
+ fdt_setprop(blob, off, "status", status,
+ strlen(status) + 1);
+ break;
+ }
+ }
+}
+#else
+static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif
+
+static void fdt_board_fixup_qe_usb(void *blob, bd_t *bd)
+{
+ u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
+
+ if (hwconfig_subarg_cmp("qe_usb", "speed", "low"))
+ clrbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+ else
+ setbits_8(&bcsr[17], BCSR17_nUSBLOWSPD);
+
+ if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) {
+ clrbits_8(&bcsr[17], BCSR17_USBVCC);
+ clrbits_8(&bcsr[17], BCSR17_USBMODE);
+ do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode",
+ "peripheral", sizeof("peripheral"), 1);
+ } else {
+ setbits_8(&bcsr[17], BCSR17_USBVCC);
+ setbits_8(&bcsr[17], BCSR17_USBMODE);
+ }
+
+ clrbits_8(&bcsr[17], BCSR17_nUSBEN);
+}
+
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif /* CONFIG_PCIE1 */
@@ -444,5 +651,8 @@ void ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_PCIE1
ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
#endif
+ fdt_board_fixup_esdhc(blob, bd);
+ fdt_board_fixup_qe_uart(blob, bd);
+ fdt_board_fixup_qe_usb(blob, bd);
}
#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
index d3b251e79..3b8ee050d 100644
--- a/board/freescale/mpc8569mds/tlb.c
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -46,22 +46,24 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 1 Initializations */
/*
- * TLBe 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH (upper half)
+ * TLBe 0: 64M Non-cacheable, guarded
* Out of reset this entry is only 4K.
+ * 0xfc000000 256K NAND FLASH (CS3)
+ * 0xfe000000 32M NOR FLASH (CS0)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
- CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 0, BOOKE_PAGESZ_16M, 1),
+ 0, 0, BOOKE_PAGESZ_64M, 1),
/*
- * TLBe 1: 16M Non-cacheable, guarded
- * 0xfe000000 16M FLASH (lower half)
+ * TLBe 1: 256KB Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_16M, 1),
+ 0, 1, BOOKE_PAGESZ_256K, 1),
/*
* TLBe 2: 256M Non-cacheable, guarded
@@ -88,16 +90,6 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_64M, 1),
-
- /*
- * TLBe 5: 256K Non-cacheable, guarded
- * 0xf8000000 32K BCSR
- * 0xf8008000 32K PIB (CS4)
- * 0xf8010000 32K PIB (CS5)
- */
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256K, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 933dd127e..2b3223453 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -199,7 +199,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
/*
* Activate ULI1575 legacy chip by performing a fake
* memory access. Needed to make ULI RTC work.
@@ -231,7 +231,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@@ -251,7 +251,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 37c4b0a3b..fccc4f8f5 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -85,8 +85,8 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
-#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
-#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
+#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02800000
+#define CONFIG_SYS_DDR_MODE_1_800 0x00040852
#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
@@ -206,7 +206,7 @@ phys_size_t fixed_sdram (void)
{
sys_info_t sysinfo;
char buf[32];
- fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
+ fsl_ddr_cfg_regs_t ddr_cfg_regs;
size_t ddr_size;
struct cpu_type *cpu;
@@ -215,13 +215,13 @@ phys_size_t fixed_sdram (void)
strmhz(buf, sysinfo.freqDDRBus));
if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_400;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_400, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_533;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_533, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_667;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_667, sizeof(ddr_cfg_regs));
else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
- ddr_cfg_regs = &ddr_cfg_regs_800;
+ memcpy(&ddr_cfg_regs, &ddr_cfg_regs_800, sizeof(ddr_cfg_regs));
else
panic("Unsupported DDR data rate %s MT/s data rate\n",
strmhz(buf, sysinfo.freqDDRBus));
@@ -230,14 +230,14 @@ phys_size_t fixed_sdram (void)
/* P1020 and it's derivatives support max 32bit DDR width */
if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
- ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
- ddr_cfg_regs->cs[0].bnds = 0x0000001F;
+ ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE;
+ ddr_cfg_regs.cs[0].bnds = 0x0000001F;
ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
}
else
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
- fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
+ fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
return ddr_size;
}
diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c
index 4c08f9efa..773659673 100644
--- a/board/freescale/p1_p2_rdb/pci.c
+++ b/board/freescale/p1_p2_rdb/pci.c
@@ -71,7 +71,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE2: disabled\n");
}
@@ -90,7 +90,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf (" PCIE1: disabled\n");
}
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index e38c0145e..9878fba10 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -227,7 +227,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie2_hose, first_free_busno);
+ &pcie2_hose, first_free_busno, pcie_ep);
/*
* The workaround doesn't work on p2020 because the location
@@ -267,7 +267,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie3_hose, first_free_busno);
+ &pcie3_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE3: disabled\n");
}
@@ -286,7 +286,7 @@ void pci_init_board(void)
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, pcie_ep);
} else {
printf(" PCIE1: disabled\n");
}
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
index c404cef58..04dc8ae1f 100644
--- a/board/logicpd/imx27lite/Makefile
+++ b/board/logicpd/imx27lite/Makefile
@@ -48,4 +48,3 @@ include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
-
diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S
index 7faad95ff..40d9b08c7 100644
--- a/board/renesas/sh7785lcr/lowlevel_init.S
+++ b/board/renesas/sh7785lcr/lowlevel_init.S
@@ -178,60 +178,6 @@ lbsc_end:
.align 4
-/*------- LBSC -------*/
-MMSELR_A: .long 0xfc400020
-#if defined(CONFIG_SH_32BIT)
-MMSELR_D: .long 0xa5a50005
-#else
-MMSELR_D: .long 0xa5a50002
-#endif
-
-/*------- DBSC2 -------*/
-#define DBSC2_BASE 0xfe800000
-DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
-DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
-DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
-DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
-DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
-DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
-DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
-DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
-DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
-DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
-DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
-DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
-DBSC2_DBDICODTOCD_A: .long DBSC2_BASE + 0x54
-DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
-DDR_DUMMY_ACCESS_A: .long 0x40000000
-
-DBSC2_DBCONF_D: .long 0x00630002
-DBSC2_DBTR0_D: .long 0x050b1f04
-DBSC2_DBTR1_D: .long 0x00040204
-DBSC2_DBTR2_D: .long 0x02100308
-DBSC2_DBFREQ_D1: .long 0x00000000
-DBSC2_DBFREQ_D2: .long 0x00000100
-DBSC2_DBDICODTOCD_D: .long 0x000f0907
-
-DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
-DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
-DBSC2_DBCMDCNT_D_REF: .long 0x00000004
-
-DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
-DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
-DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
-DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
-DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
-DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
-
-DBSC2_DBEN_D: .long 0x00000001
-
-DBSC2_DBPDCNT0_D3: .long 0x00000080
-DBSC2_DBRFCNT1_D: .long 0x00000926
-DBSC2_DBRFCNT2_D: .long 0x00fe00fe
-DBSC2_DBRFCNT0_D: .long 0x00010000
-
-WAIT_200US: .long 33333
-
/*------- GPIO -------*/
PACR_D: .long 0x0000
PBCR_D: .long 0x0000
@@ -291,6 +237,59 @@ PPUPR2_A: .long GPIO_BASE + 0x62
P1MSELR_A: .long GPIO_BASE + 0x80
P2MSELR_A: .long GPIO_BASE + 0x82
+MMSELR_A: .long 0xfc400020
+#if defined(CONFIG_SH_32BIT)
+MMSELR_D: .long 0xa5a50005
+#else
+MMSELR_D: .long 0xa5a50002
+#endif
+
+/*------- DBSC2 -------*/
+#define DBSC2_BASE 0xfe800000
+DBSC2_DBSTATE_A: .long DBSC2_BASE + 0x0c
+DBSC2_DBEN_A: .long DBSC2_BASE + 0x10
+DBSC2_DBCMDCNT_A: .long DBSC2_BASE + 0x14
+DBSC2_DBCONF_A: .long DBSC2_BASE + 0x20
+DBSC2_DBTR0_A: .long DBSC2_BASE + 0x30
+DBSC2_DBTR1_A: .long DBSC2_BASE + 0x34
+DBSC2_DBTR2_A: .long DBSC2_BASE + 0x38
+DBSC2_DBRFCNT0_A: .long DBSC2_BASE + 0x40
+DBSC2_DBRFCNT1_A: .long DBSC2_BASE + 0x44
+DBSC2_DBRFCNT2_A: .long DBSC2_BASE + 0x48
+DBSC2_DBRFSTS_A: .long DBSC2_BASE + 0x4c
+DBSC2_DBFREQ_A: .long DBSC2_BASE + 0x50
+DBSC2_DBDICODTOCD_A:.long DBSC2_BASE + 0x54
+DBSC2_DBMRCNT_A: .long DBSC2_BASE + 0x60
+DDR_DUMMY_ACCESS_A: .long 0x40000000
+
+DBSC2_DBCONF_D: .long 0x00630002
+DBSC2_DBTR0_D: .long 0x050b1f04
+DBSC2_DBTR1_D: .long 0x00040204
+DBSC2_DBTR2_D: .long 0x02100308
+DBSC2_DBFREQ_D1: .long 0x00000000
+DBSC2_DBFREQ_D2: .long 0x00000100
+DBSC2_DBDICODTOCD_D:.long 0x000f0907
+
+DBSC2_DBCMDCNT_D_CKE_H: .long 0x00000003
+DBSC2_DBCMDCNT_D_PALL: .long 0x00000002
+DBSC2_DBCMDCNT_D_REF: .long 0x00000004
+
+DBSC2_DBMRCNT_D_EMRS2: .long 0x00020000
+DBSC2_DBMRCNT_D_EMRS3: .long 0x00030000
+DBSC2_DBMRCNT_D_EMRS1_1: .long 0x00010006
+DBSC2_DBMRCNT_D_EMRS1_2: .long 0x00010386
+DBSC2_DBMRCNT_D_MRS_1: .long 0x00000952
+DBSC2_DBMRCNT_D_MRS_2: .long 0x00000852
+
+DBSC2_DBEN_D: .long 0x00000001
+
+DBSC2_DBPDCNT0_D3: .long 0x00000080
+DBSC2_DBRFCNT1_D: .long 0x00000926
+DBSC2_DBRFCNT2_D: .long 0x00fe00fe
+DBSC2_DBRFCNT0_D: .long 0x00010000
+
+WAIT_200US: .long 33333
+
/*------- LBSC -------*/
PASCR_A: .long 0xff000070
PASCR_32BIT_MODE: .long 0x80000000 /* check booting mode */
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 194f6ab96..5e3e17658 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -359,7 +359,7 @@ pci_init_board(void)
SET_STD_PCI_INFO(pci_info[num], 1);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pci1_hose, first_free_busno);
+ &pci1_hose, first_free_busno, 0);
} else {
printf (" PCI: disabled\n");
}
@@ -378,7 +378,7 @@ pci_init_board(void)
SET_STD_PCIE_INFO(pci_info[num], 1);
printf (" PCIE at base address %lx\n", pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
- &pcie1_hose, first_free_busno);
+ &pcie1_hose, first_free_busno, 0);
} else {
printf (" PCIE: disabled\n");
}
diff --git a/board/xes/xpedite5370/tlb.c b/board/xes/xpedite5370/tlb.c
index caafa3011..a465ce386 100644
--- a/board/xes/xpedite5370/tlb.c
+++ b/board/xes/xpedite5370/tlb.c
@@ -61,32 +61,37 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
+ /* **M** - Boot page for secondary processors */
+ SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
+ 0, 3, BOOKE_PAGESZ_4K, 1),
+
#ifdef CONFIG_PCIE1
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_1G, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_PCIE2
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 4, BOOKE_PAGESZ_256M, 1),
+ 0, 5, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE3
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_256M, 1),
+ 0, 6, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ 0, 7, BOOKE_PAGESZ_64M, 1),
#endif
};
generated by cgit v1.2.3 (git 2.39.1) at 2024-06-24 11:51:49 +0000