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-rw-r--r--cpu/arm920t/s3c24x0/interrupts.c4
-rw-r--r--cpu/arm920t/s3c24x0/speed.c42
-rw-r--r--cpu/arm920t/s3c24x0/timer.c110
-rw-r--r--cpu/arm920t/s3c24x0/usb.c30
-rw-r--r--cpu/arm920t/s3c24x0/usb_ohci.c1323
-rw-r--r--cpu/arm920t/s3c24x0/usb_ohci.h209
-rw-r--r--cpu/arm920t/start.S63
-rw-r--r--cpu/arm926ejs/start.S1
-rw-r--r--cpu/arm_cortexa8/omap3/mem.c18
-rw-r--r--cpu/arm_cortexa8/omap3/sys_info.c2
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/Makefile53
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/cache.c43
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/clock.c308
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/cpu_info.c57
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/reset.S47
-rw-r--r--cpu/arm_cortexa8/s5pc1xx/timer.c195
-rw-r--r--cpu/mpc83xx/fdt.c39
-rw-r--r--cpu/ppc4xx/cpu.c9
-rw-r--r--cpu/ppc4xx/cpu_init.c69
-rw-r--r--cpu/ppc4xx/fdt.c10
20 files changed, 1775 insertions, 857 deletions
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
index 11ec95e12..914894613 100644
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ b/cpu/arm920t/s3c24x0/interrupts.c
@@ -40,7 +40,7 @@
void do_irq (struct pt_regs *pt_regs)
{
- S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
- u_int32_t intpnd = irq->INTPND;
+ struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+ u_int32_t intpnd = readl(&irq->INTPND);
}
diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c
index e0dca6256..136c7794a 100644
--- a/cpu/arm920t/s3c24x0/speed.c
+++ b/cpu/arm920t/s3c24x0/speed.c
@@ -32,6 +32,8 @@
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#include <asm/io.h>
+
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
@@ -53,49 +55,51 @@
static ulong get_PLLCLK(int pllreg)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- ulong r, m, p, s;
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ ulong r, m, p, s;
- if (pllreg == MPLL)
- r = clk_power->MPLLCON;
- else if (pllreg == UPLL)
- r = clk_power->UPLLCON;
- else
- hang();
+ if (pllreg == MPLL)
+ r = readl(&clk_power->MPLLCON);
+ else if (pllreg == UPLL)
+ r = readl(&clk_power->UPLLCON);
+ else
+ hang();
- m = ((r & 0xFF000) >> 12) + 8;
- p = ((r & 0x003F0) >> 4) + 2;
- s = r & 0x3;
+ m = ((r & 0xFF000) >> 12) + 8;
+ p = ((r & 0x003F0) >> 4) + 2;
+ s = r & 0x3;
- return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
+ return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
- return(get_PLLCLK(MPLL));
+ return get_PLLCLK(MPLL);
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+ return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
+ return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
- return(get_PLLCLK(UPLL));
+ return get_PLLCLK(UPLL);
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index c8c7cdb52..20cedd463 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -30,7 +30,11 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || \
+ defined(CONFIG_S3C2410) || \
+ defined(CONFIG_TRAB)
+
+#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
@@ -39,40 +43,45 @@
#endif
int timer_load_val = 0;
+static ulong timer_clk;
/* macro to read the 16 bit timer */
static inline ulong READ_TIMER(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return (timers->TCNTO4 & 0xffff);
+ return readl(&timers->TCNTO4) & 0xffff;
}
static ulong timestamp;
static ulong lastdec;
-int timer_init (void)
+int timer_init(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+ ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- timers->TCFG0 = 0x0f00;
- if (timer_load_val == 0)
- {
+ writel(0x0f00, &timers->TCFG0);
+ if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- timer_load_val = get_PCLK()/(2 * 16 * 100);
+ timer_load_val = get_PCLK() / (2 * 16 * 100);
+ timer_clk = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
+ lastdec = timer_load_val;
+ writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+ tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+ tmr = (tmr & ~0x0700000) | 0x0500000;
+ writel(tmr, &timers->TCON);
timestamp = 0;
return (0);
@@ -82,58 +91,49 @@ int timer_init (void)
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
- ulong start = get_timer(0);
+ ulong start = get_ticks();
tmo = usec / 1000;
tmo *= (timer_load_val * 100);
tmo /= 1000;
- while ((ulong)(get_timer_masked () - start) < tmo)
+ while ((ulong) (get_ticks() - start) < tmo)
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER();
timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
- ulong now = READ_TIMER();
+ ulong tmr = get_ticks();
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
-
- return timestamp;
+ return tmr / (timer_clk / CONFIG_SYS_HZ);
}
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
@@ -145,13 +145,13 @@ void udelay_masked (unsigned long usec)
tmo /= 1000;
} else {
tmo = usec * (timer_load_val * 100);
- tmo /= (1000*1000);
+ tmo /= (1000 * 1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_ticks() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_ticks();
diff = endtime - now;
} while (diff >= 0);
}
@@ -162,14 +162,25 @@ void udelay_masked (unsigned long usec)
*/
unsigned long long get_ticks(void)
{
- return get_timer(0);
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + timer_load_val - now;
+ }
+ lastdec = now;
+
+ return timestamp;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
@@ -189,30 +200,31 @@ ulong get_tbclk (void)
/*
* reset the cpu by setting up the watchdog timer and let him time out
*/
-void reset_cpu (ulong ignored)
+void reset_cpu(ulong ignored)
{
- volatile S3C24X0_WATCHDOG * watchdog;
+ struct s3c24x0_watchdog *watchdog;
#ifdef CONFIG_TRAB
- extern void disable_vfd (void);
-
disable_vfd();
#endif
- watchdog = S3C24X0_GetBase_WATCHDOG();
+ watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- watchdog->WTCON = 0x0000;
+ writel(0x0000, &watchdog->WTCON);
/* Initialize watchdog timer count register */
- watchdog->WTCNT = 0x0001;
+ writel(0x0001, &watchdog->WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- watchdog->WTCON = 0x0021;
+ writel(0x0021, &watchdog->WTCON);
- while(1); /* loop forever and wait for reset to happen */
+ while (1)
+ /* loop forever and wait for reset to happen */;
/*NOTREACHED*/
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index 9ccf57596..b5ba8c4f3 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -32,41 +32,43 @@
# include <s3c2410.h>
#endif
-int usb_cpu_init (void)
-{
+#include <asm/io.h>
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+int usb_cpu_init(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+ /* 1 = use pads related USB for USB host */
+ writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
/*
* Enable USB host clock.
*/
- clk_power->CLKCON |= (1 << 4);
+ writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_stop (void)
+int usb_cpu_stop(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_init_fail (void)
+int usb_cpu_init_fail(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- clk_power->CLKCON &= ~(1 << 4);
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
+# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index 7838014bd..7672e4ce1 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -44,6 +44,7 @@
#include <s3c2410.h>
#endif
+#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
#include "usb_ohci.h"
@@ -56,10 +57,8 @@
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define readl(a) (*((volatile u32 *)(a)))
-#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+#define min_t(type, x, y) \
+ ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
#undef DEBUG
#ifdef DEBUG
@@ -78,8 +77,8 @@
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
-/* global ohci_t */
-static ohci_t gohci;
+/* global struct ohci */
+static struct ohci gohci;
/* this must be aligned to a 256 byte boundary */
struct ohci_hcca ghcca[1];
/* a pointer to the aligned storage */
@@ -87,7 +86,7 @@ struct ohci_hcca *phcca;
/* this allocates EDs for all possible endpoints */
struct ohci_device ohci_dev;
/* urb_priv */
-urb_priv_t urb_priv;
+struct urb_priv urb_priv;
/* RHSC flag */
int got_rhsc;
/* device which was disconnected */
@@ -109,21 +108,29 @@ int urb_finished = 0;
temp = readl (&hc->regs->roothub.register); \
temp; })
-static u32 roothub_a (struct ohci *hc)
- { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
- { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
- { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
- { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
+static u32 roothub_a(struct ohci *hc)
+{
+ return read_roothub(hc, a, 0xfc0fe000);
+}
+static inline u32 roothub_b(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.b);
+}
+static inline u32 roothub_status(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.status);
+}
+static u32 roothub_portstatus(struct ohci *hc, int i)
+{
+ return read_roothub(hc, portstatus[i], 0xffe0fce0);
+}
/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+static int hc_interrupt(void);
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval);
/*-------------------------------------------------------------------------*
* URB support functions
@@ -131,11 +138,11 @@ td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
/* free HCD-private data associated with this URB */
-static void urb_free_priv (urb_priv_t * urb)
+static void urb_free_priv(struct urb_priv *urb)
{
- int i;
- int last;
- struct td * td;
+ int i;
+ int last;
+ struct td *td;
last = urb->length - 1;
if (last >= 0) {
@@ -152,227 +159,219 @@ static void urb_free_priv (urb_priv_t * urb)
/*-------------------------------------------------------------------------*/
#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
+static int sohci_get_current_frame_number(struct usb_device *dev);
/* debug| print the main components of an URB
* small: 0) header + data packets 1) just header */
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, char * str, int small)
+static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, char *str,
+ int small)
{
- urb_priv_t * purb = &urb_priv;
+ struct urb_priv *purb = &urb_priv;
dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
- str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
+ str,
+ sohci_get_current_frame_number(dev),
+ usb_pipedevice(pipe),
+ usb_pipeendpoint(pipe),
+ usb_pipeout(pipe) ? 'O' : 'I',
+ usb_pipetype(pipe) < 2 ?
+ (usb_pipeint(pipe) ? "INTR" : "ISOC") :
+ (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
+ purb->actual_length, transfer_len, dev->status);
#ifdef OHCI_VERBOSE_DEBUG
if (!small) {
int i, len;
- if (usb_pipecontrol (pipe)) {
- printf (__FILE__ ": cmd(8):");
- for (i = 0; i < 8 ; i++)
- printf (" %02x", ((__u8 *) setup) [i]);
- printf ("\n");
+ if (usb_pipecontrol(pipe)) {
+ printf(__FILE__ ": cmd(8):");
+ for (i = 0; i < 8; i++)
+ printf(" %02x", ((__u8 *) setup)[i]);
+ printf("\n");
}
if (transfer_len > 0 && buffer) {
- printf (__FILE__ ": data(%d/%d):",
- purb->actual_length,
- transfer_len);
- len = usb_pipeout (pipe)?
- transfer_len: purb->actual_length;
+ printf(__FILE__ ": data(%d/%d):",
+ purb->actual_length, transfer_len);
+ len = usb_pipeout(pipe) ?
+ transfer_len : purb->actual_length;
for (i = 0; i < 16 && i < len; i++)
- printf (" %02x", ((__u8 *) buffer) [i]);
- printf ("%s\n", i < len? "...": "");
+ printf(" %02x", ((__u8 *) buffer)[i]);
+ printf("%s\n", i < len ? "..." : "");
}
}
#endif
}
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
+/* just for debugging; prints non-empty branches of the
+ int ed tree inclusive iso eds*/
+void ep_print_int_eds(struct ohci *ohci, char *str)
+{
int i, j;
- __u32 * ed_p;
- for (i= 0; i < 32; i++) {
+ __u32 *ed_p;
+ for (i = 0; i < 32; i++) {
j = 5;
- ed_p = &(ohci->hcca->int_table [i]);
+ ed_p = &(ohci->hcca->int_table[i]);
if (*ed_p == 0)
- continue;
- printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ continue;
+ printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
while (*ed_p != 0 && j--) {
- ed_t *ed = (ed_t *)m32_swap(ed_p);
- printf (" ed: %4x;", ed->hwINFO);
+ struct ed *ed = (struct ed *) m32_swap(ed_p);
+ printf(" ed: %4x;", ed->hwINFO);
ed_p = &ed->hwNextED;
}
- printf ("\n");
+ printf("\n");
}
}
-static void ohci_dump_intr_mask (char *label, __u32 mask)
+static void ohci_dump_intr_mask(char *label, __u32 mask)
{
- dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
- label,
- mask,
- (mask & OHCI_INTR_MIE) ? " MIE" : "",
- (mask & OHCI_INTR_OC) ? " OC" : "",
- (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
- (mask & OHCI_INTR_FNO) ? " FNO" : "",
- (mask & OHCI_INTR_UE) ? " UE" : "",
- (mask & OHCI_INTR_RD) ? " RD" : "",
- (mask & OHCI_INTR_SF) ? " SF" : "",
- (mask & OHCI_INTR_WDH) ? " WDH" : "",
- (mask & OHCI_INTR_SO) ? " SO" : ""
- );
+ dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : "");
}
-static void maybe_print_eds (char *label, __u32 value)
+static void maybe_print_eds(char *label, __u32 value)
{
- ed_t *edp = (ed_t *)value;
+ struct ed *edp = (struct ed *) value;
if (value) {
- dbg ("%s %08x", label, value);
- dbg ("%08x", edp->hwINFO);
- dbg ("%08x", edp->hwTailP);
- dbg ("%08x", edp->hwHeadP);
- dbg ("%08x", edp->hwNextED);
+ dbg("%s %08x", label, value);
+ dbg("%08x", edp->hwINFO);
+ dbg("%08x", edp->hwTailP);
+ dbg("%08x", edp->hwHeadP);
+ dbg("%08x", edp->hwNextED);
}
}
-static char * hcfs2string (int state)
+static char *hcfs2string(int state)
{
switch (state) {
- case OHCI_USB_RESET: return "reset";
- case OHCI_USB_RESUME: return "resume";
- case OHCI_USB_OPER: return "operational";
- case OHCI_USB_SUSPEND: return "suspend";
+ case OHCI_USB_RESET:
+ return "reset";
+ case OHCI_USB_RESUME:
+ return "resume";
+ case OHCI_USB_OPER:
+ return "operational";
+ case OHCI_USB_SUSPEND:
+ return "suspend";
}
return "?";
}
/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
+static void ohci_dump_status(struct ohci *controller)
{
- struct ohci_regs *regs = controller->regs;
- __u32 temp;
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
- temp = readl (&regs->revision) & 0xff;
+ temp = readl(&regs->revision) & 0xff;
if (temp != 0x10)
- dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
- temp = readl (&regs->control);
- dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
- (temp & OHCI_CTRL_RWE) ? " RWE" : "",
- (temp & OHCI_CTRL_RWC) ? " RWC" : "",
- (temp & OHCI_CTRL_IR) ? " IR" : "",
- hcfs2string (temp & OHCI_CTRL_HCFS),
- (temp & OHCI_CTRL_BLE) ? " BLE" : "",
- (temp & OHCI_CTRL_CLE) ? " CLE" : "",
- (temp & OHCI_CTRL_IE) ? " IE" : "",
- (temp & OHCI_CTRL_PLE) ? " PLE" : "",
- temp & OHCI_CTRL_CBSR
- );
-
- temp = readl (&regs->cmdstatus);
- dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
- (temp & OHCI_SOC) >> 16,
- (temp & OHCI_OCR) ? " OCR" : "",
- (temp & OHCI_BLF) ? " BLF" : "",
- (temp & OHCI_CLF) ? " CLF" : "",
- (temp & OHCI_HCR) ? " HCR" : ""
- );
-
- ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
- ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
-
- maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
-
- maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
- maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
-
- maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
- maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
-
- maybe_print_eds ("donehead", readl (&regs->donehead));
+ dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl(&regs->control);
+ dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string(temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
+
+ temp = readl(&regs->cmdstatus);
+ dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
+
+ ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
+ ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
+
+ maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
+
+ maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
+ maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
+
+ maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
+ maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
+
+ maybe_print_eds("donehead", readl(&regs->donehead));
}
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
+static void ohci_dump_roothub(struct ohci *controller, int verbose)
{
- __u32 temp, ndp, i;
+ __u32 temp, ndp, i;
- temp = roothub_a (controller);
+ temp = roothub_a(controller);
ndp = (temp & RH_A_NDP);
if (verbose) {
- dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
- ((temp & RH_A_POTPGT) >> 24) & 0xff,
- (temp & RH_A_NOCP) ? " NOCP" : "",
- (temp & RH_A_OCPM) ? " OCPM" : "",
- (temp & RH_A_DT) ? " DT" : "",
- (temp & RH_A_NPS) ? " NPS" : "",
- (temp & RH_A_PSM) ? " PSM" : "",
- ndp
- );
- temp = roothub_b (controller);
- dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
- temp,
- (temp & RH_B_PPCM) >> 16,
- (temp & RH_B_DR)
- );
- temp = roothub_status (controller);
- dbg ("roothub.status: %08x%s%s%s%s%s%s",
- temp,
- (temp & RH_HS_CRWE) ? " CRWE" : "",
- (temp & RH_HS_OCIC) ? " OCIC" : "",
- (temp & RH_HS_LPSC) ? " LPSC" : "",
- (temp & RH_HS_DRWE) ? " DRWE" : "",
- (temp & RH_HS_OCI) ? " OCI" : "",
- (temp & RH_HS_LPS) ? " LPS" : ""
- );
+ dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "", ndp);
+ temp = roothub_b(controller);
+ dbg("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
+ );
+ temp = roothub_status(controller);
+ dbg("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : "");
}
for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
- i,
- temp,
- (temp & RH_PS_PRSC) ? " PRSC" : "",
- (temp & RH_PS_OCIC) ? " OCIC" : "",
- (temp & RH_PS_PSSC) ? " PSSC" : "",
- (temp & RH_PS_PESC) ? " PESC" : "",
- (temp & RH_PS_CSC) ? " CSC" : "",
-
- (temp & RH_PS_LSDA) ? " LSDA" : "",
- (temp & RH_PS_PPS) ? " PPS" : "",
- (temp & RH_PS_PRS) ? " PRS" : "",
- (temp & RH_PS_POCI) ? " POCI" : "",
- (temp & RH_PS_PSS) ? " PSS" : "",
-
- (temp & RH_PS_PES) ? " PES" : "",
- (temp & RH_PS_CCS) ? " CCS" : ""
- );
+ temp = roothub_portstatus(controller, i);
+ dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : "");
}
}
-static void ohci_dump (ohci_t *controller, int verbose)
+static void ohci_dump(struct ohci *controller, int verbose)
{
- dbg ("OHCI controller usb-%s state", controller->slot_name);
+ dbg("OHCI controller usb-%s state", controller->slot_name);
/* dumps some of the state we know about */
- ohci_dump_status (controller);
+ ohci_dump_status(controller);
if (verbose)
- ep_print_int_eds (controller, "hcca");
- dbg ("hcca frame #%04x", controller->hcca->frame_no);
- ohci_dump_roothub (controller, 1);
+ ep_print_int_eds(controller, "hcca");
+ dbg("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub(controller, 1);
}
-
#endif /* DEBUG */
/*-------------------------------------------------------------------------*
@@ -382,11 +381,11 @@ static void ohci_dump (ohci_t *controller, int verbose)
/* get a transfer request */
int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
+ int transfer_len, struct devrequest *setup, int interval)
{
- ohci_t *ohci;
- ed_t * ed;
- urb_priv_t *purb_priv;
+ struct ohci *ohci;
+ struct ed *ed;
+ struct urb_priv *purb_priv;
int i, size = 0;
ohci = &gohci;
@@ -405,24 +404,27 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
err("sohci_submit_job: URB NOT FINISHED");
return -1;
}
- /* we're about to begin a new transaction here so mark the URB unfinished */
+ /* we're about to begin a new transaction here
+ so mark the URB unfinished */
urb_finished = 0;
/* every endpoint has a ed, locate and fill it */
- if (!(ed = ep_add_ed (dev, pipe))) {
+ ed = ep_add_ed(dev, pipe);
+ if (!ed) {
err("sohci_submit_job: ENOMEM");
return -1;
}
/* for the private part of the URB we need the number of TDs (size) */
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK: /* one TD for every 4096 Byte */
- size = (transfer_len - 1) / 4096 + 1;
- break;
- case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
- size = (transfer_len == 0)? 2:
- (transfer_len - 1) / 4096 + 3;
- break;
+ switch (usb_pipetype(pipe)) {
+ case PIPE_BULK:
+ /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL:
+ /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
+ break;
}
if (size >= (N_URB_TD - 1)) {
@@ -440,27 +442,28 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
/* allocate the TDs */
/* note that td[0] was allocated in ep_add_ed */
for (i = 0; i < size; i++) {
- purb_priv->td[i] = td_alloc (dev);
+ purb_priv->td[i] = td_alloc(dev);
if (!purb_priv->td[i]) {
purb_priv->length = i;
- urb_free_priv (purb_priv);
+ urb_free_priv(purb_priv);
err("sohci_submit_job: ENOMEM");
return -1;
}
}
if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
- urb_free_priv (purb_priv);
+ urb_free_priv(purb_priv);
err("sohci_submit_job: EINVAL");
return -1;
}
/* link the ed into a chain if is not already */
if (ed->state != ED_OPER)
- ep_link (ohci, ed);
+ ep_link(ohci, ed);
/* fill the TDs and link it to the ed */
- td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
+ interval);
return 0;
}
@@ -470,11 +473,11 @@ int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
#ifdef DEBUG
/* tell us the current USB frame number */
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+static int sohci_get_current_frame_number(struct usb_device *usb_dev)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
- return m16_swap (ohci->hcca->frame_no);
+ return m16_swap(ohci->hcca->frame_no);
}
#endif
@@ -484,9 +487,9 @@ static int sohci_get_current_frame_number (struct usb_device *usb_dev)
/* link an ed into one of the HC chains */
-static int ep_link (ohci_t *ohci, ed_t *edi)
+static int ep_link(struct ohci *ohci, struct ed *edi)
{
- volatile ed_t *ed = edi;
+ struct ed *ed = edi;
ed->state = ED_OPER;
@@ -494,15 +497,15 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
case PIPE_CONTROL:
ed->hwNextED = 0;
if (ohci->ed_controltail == NULL) {
- writel (ed, &ohci->regs->ed_controlhead);
+ writel((u32)ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
+ ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
ohci->hc_control |= OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
ohci->ed_controltail = edi;
break;
@@ -510,15 +513,15 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
case PIPE_BULK:
ed->hwNextED = 0;
if (ohci->ed_bulktail == NULL) {
- writel (ed, &ohci->regs->ed_bulkhead);
+ writel((u32)ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
+ ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
ohci->hc_control |= OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
ohci->ed_bulktail = edi;
break;
@@ -533,25 +536,28 @@ static int ep_link (ohci_t *ohci, ed_t *edi)
* the link from the ed still points to another operational ed or 0
* so the HC can eventually finish the processing of the unlinked ed */
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
+static int ep_unlink(struct ohci *ohci, struct ed *ed)
{
- ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+ struct ed *next;
+ ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
switch (ed->type) {
case PIPE_CONTROL:
if (ed->ed_prev == NULL) {
if (!ed->hwNextED) {
ohci->hc_control &= ~OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_controlhead);
} else {
ed->ed_prev->hwNextED = ed->hwNextED;
}
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
}
break;
@@ -559,16 +565,18 @@ static int ep_unlink (ohci_t *ohci, ed_t *ed)
if (ed->ed_prev == NULL) {
if (!ed->hwNextED) {
ohci->hc_control &= ~OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_bulkhead);
} else {
ed->ed_prev->hwNextED = ed->hwNextED;
}
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
}
break;
}
@@ -576,23 +584,24 @@ static int ep_unlink (ohci_t *ohci, ed_t *ed)
return 0;
}
-
/*-------------------------------------------------------------------------*/
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration
+ * command, but the USB stack is a little bit stateless so we do it at every
+ * transaction. If the state of the ed is ED_NEW then a dummy td is added and
+ * the state is changed to ED_UNLINK. In all other cases the state is left
+ * unchanged. The ed info fields are setted anyway even though most of them
+ * should not change */
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
{
- td_t *td;
- ed_t *ed_ret;
- volatile ed_t *ed;
+ struct td *td;
+ struct ed *ed_ret;
+ struct ed *ed;
- ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
- (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
+ (usb_pipecontrol(pipe) ? 0 :
+ usb_pipeout(pipe))];
if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
err("ep_add_ed: pending delete");
@@ -601,22 +610,23 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
}
if (ed->state == ED_NEW) {
- ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
- td = td_alloc (usb_dev);
- ed->hwTailP = (__u32)m32_swap (td);
+ td = td_alloc(usb_dev);
+ ed->hwTailP = (__u32) m32_swap(td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
- ed->type = usb_pipetype (pipe);
+ ed->type = usb_pipetype(pipe);
ohci_dev.ed_cnt++;
}
- ed->hwINFO = m32_swap (usb_pipedevice (pipe)
- | usb_pipeendpoint (pipe) << 7
- | (usb_pipeisoc (pipe)? 0x8000: 0)
- | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
- | usb_pipeslow (pipe) << 13
- | usb_maxpacket (usb_dev, pipe) << 16);
+ ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+ | usb_pipeendpoint(pipe) << 7
+ | (usb_pipeisoc(pipe) ? 0x8000 : 0)
+ | (usb_pipecontrol(pipe) ? 0 :
+ (usb_pipeout(pipe) ? 0x800 : 0x1000))
+ | usb_pipeslow(pipe) << 13 |
+ usb_maxpacket(usb_dev, pipe) << 16);
return ed_ret;
}
@@ -627,11 +637,11 @@ static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-static void td_fill (ohci_t *ohci, unsigned int info,
- void *data, int len,
- struct usb_device *dev, int index, urb_priv_t *urb_priv)
+static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
+ struct usb_device *dev, int index,
+ struct urb_priv *urb_priv)
{
- volatile td_t *td, *td_pt;
+ struct td *td, *td_pt;
#ifdef OHCI_FILL_TRACE
int i;
#endif
@@ -641,33 +651,35 @@ static void td_fill (ohci_t *ohci, unsigned int info,
return;
}
/* use this td as the next dummy */
- td_pt = urb_priv->td [index];
+ td_pt = urb_priv->td[index];
td_pt->hwNextTD = 0;
/* fill the old dummy TD */
- td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+ td = urb_priv->td[index] =
+ (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
- td->data = (__u32)data;
+ td->data = (__u32) data;
#ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
- printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+ printf("td->data[%d] %#2x ", i,
+ ((unsigned char *)td->data)[i]);
printf("\n");
}
#endif
if (!len)
data = 0;
- td->hwINFO = (__u32)m32_swap (info);
- td->hwCBP = (__u32)m32_swap (data);
+ td->hwINFO = (__u32) m32_swap(info);
+ td->hwCBP = (__u32) m32_swap(data);
if (data)
- td->hwBE = (__u32)m32_swap (data + len - 1);
+ td->hwBE = (__u32) m32_swap(data + len - 1);
else
td->hwBE = 0;
- td->hwNextTD = (__u32)m32_swap (td_pt);
+ td->hwNextTD = (__u32) m32_swap(td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
@@ -677,22 +689,26 @@ static void td_fill (ohci_t *ohci, unsigned int info,
/* prepare all TDs of a transfer */
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
int data_len = transfer_len;
void *data;
int cnt = 0;
__u32 info = 0;
unsigned int toggle = 0;
- /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ /* OHCI handles the DATA-toggles itself, we just
+ use the USB-toggle bits for reseting */
+ if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
toggle = TD_T_DATA0;
- usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
+ 1);
}
urb->td_cnt = 0;
if (data_len)
@@ -700,37 +716,45 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
else
data = 0;
- switch (usb_pipetype (pipe)) {
+ switch (usb_pipetype(pipe)) {
case PIPE_BULK:
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
- while(data_len > 4096) {
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
- data += 4096; data_len -= 4096; cnt++;
+ info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
+ while (data_len > 4096) {
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ 4096, dev, cnt, urb);
+ data += 4096;
+ data_len -= 4096;
+ cnt++;
}
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_OUT :
+ TD_CC | TD_R | TD_DP_IN;
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ data_len, dev, cnt, urb);
cnt++;
if (!ohci->sleeping)
- writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ /* start bulk list */
+ writel(OHCI_BLF, &ohci->regs->cmdstatus);
break;
case PIPE_CONTROL:
info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
- td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+ td_fill(ohci, info, setup, 8, dev, cnt++, urb);
if (data_len > 0) {
- info = usb_pipeout (pipe)?
- TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
+ TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
/* NOTE: mishandles transfers >8K, some >4K */
- td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ td_fill(ohci, info, data, data_len, dev, cnt++, urb);
}
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
- td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_IN | TD_T_DATA1 :
+ TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill(ohci, info, data, 0, dev, cnt++, urb);
if (!ohci->sleeping)
- writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ /* start Control list */
+ writel(OHCI_CLF, &ohci->regs->cmdstatus);
break;
}
if (urb->length != cnt)
@@ -744,18 +768,17 @@ static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buf
/* calculate the transfer length and update the urb */
-static void dl_transfer_length(td_t * td)
+static void dl_transfer_length(struct td *td)
{
__u32 tdINFO, tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
-
- tdINFO = m32_swap (td->hwINFO);
- tdBE = m32_swap (td->hwBE);
- tdCBP = m32_swap (td->hwCBP);
+ struct urb_priv *lurb_priv = &urb_priv;
+ tdINFO = m32_swap(td->hwINFO);
+ tdBE = m32_swap(td->hwBE);
+ tdCBP = m32_swap(td->hwCBP);
if (!(usb_pipecontrol(lurb_priv->pipe) &&
- ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
lurb_priv->actual_length += tdBE - td->data + 1;
@@ -770,37 +793,44 @@ static void dl_transfer_length(td_t * td)
/* replies to the request have to be on a FIFO basis so
* we reverse the reversed done-list */
-static td_t * dl_reverse_done_list (ohci_t *ohci)
+static struct td *dl_reverse_done_list(struct ohci *ohci)
{
__u32 td_list_hc;
- td_t *td_rev = NULL;
- td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
+ __u32 tmp;
+ struct td *td_rev = NULL;
+ struct td *td_list = NULL;
+ struct urb_priv *lurb_priv = NULL;
- td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
ohci->hcca->done_head = 0;
while (td_list_hc) {
- td_list = (td_t *)td_list_hc;
+ td_list = (struct td *) td_list_hc;
- if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
lurb_priv = &urb_priv;
dbg(" USB-error/status: %x : %p",
- TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & m32_swap (0x1)) {
- if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap(0x1)) {
+ if (lurb_priv &&
+ ((td_list->index+1) < lurb_priv->length)) {
+ tmp = lurb_priv->length - 1;
td_list->ed->hwHeadP =
- (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
- (td_list->ed->hwHeadP & m32_swap (0x2));
- lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ (lurb_priv->td[tmp]->hwNextTD &
+ m32_swap(0xfffffff0)) |
+ (td_list->ed->hwHeadP &
+ m32_swap(0x2));
+ lurb_priv->td_cnt += lurb_priv->length -
+ td_list->index - 1;
} else
- td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ td_list->ed->hwHeadP &=
+ m32_swap(0xfffffff2);
}
}
td_list->next_dl_td = td_rev;
td_rev = td_list;
- td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
}
return td_list;
@@ -809,28 +839,28 @@ static td_t * dl_reverse_done_list (ohci_t *ohci)
/*-------------------------------------------------------------------------*/
/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
+static int dl_done_list(struct ohci *ohci, struct td *td_list)
{
- td_t *td_list_next = NULL;
- ed_t *ed;
+ struct td *td_list_next = NULL;
+ struct ed *ed;
int cc = 0;
int stat = 0;
/* urb_t *urb; */
- urb_priv_t *lurb_priv;
+ struct urb_priv *lurb_priv;
__u32 tdINFO, edHeadP, edTailP;
while (td_list) {
td_list_next = td_list->next_dl_td;
lurb_priv = &urb_priv;
- tdINFO = m32_swap (td_list->hwINFO);
+ tdINFO = m32_swap(td_list->hwINFO);
ed = td_list->ed;
dl_transfer_length(td_list);
/* error code of transfer */
- cc = TD_CC_GET (tdINFO);
+ cc = TD_CC_GET(tdINFO);
if (cc != 0) {
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
@@ -842,18 +872,19 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
if ((ed->state & (ED_OPER | ED_UNLINK)))
urb_finished = 1;
else
- dbg("dl_done_list: strange.., ED state %x, ed->state\n");
+ dbg("dl_done_list: strange.., ED state %x, "
+ "ed->state\n");
} else
- dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
- lurb_priv->length);
+ dbg("dl_done_list: processing TD %x, len %x\n",
+ lurb_priv->td_cnt, lurb_priv->length);
if (ed->state != ED_NEW) {
- edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap (ed->hwTailP);
+ edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap(ed->hwTailP);
/* unlink eds if they are not busy */
if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
+ ep_unlink(ohci, ed);
}
td_list = td_list_next;
@@ -866,102 +897,98 @@ static int dl_done_list (ohci_t *ohci, td_t *td_list)
*-------------------------------------------------------------------------*/
/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
+static __u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
0x00,
- 0x00, /* __u16 idProduct; */
+ 0x00, /* __u16 idProduct; */
0x00,
- 0x00, /* __u16 bcdDevice; */
+ 0x00, /* __u16 bcdDevice; */
0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
};
-
/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
+static __u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered,
+ 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
/* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
/* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
+ 0xff /* __u8 ep_bInterval; 255 ms */
};
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
};
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
+static unsigned char root_hub_str_index1[] = {
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
};
/* Hub class-specific descriptor is constructed dynamically */
@@ -971,31 +998,40 @@ static unsigned char root_hub_str_index1[] =
#define OK(x) len = (x); break
#ifdef DEBUG
-#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#define WR_RH_STAT(x) \
+{ \
+ info("WR:status %#8x", (x)); \
+ writel((x), &gohci.regs->roothub.status); \
+}
+#define WR_RH_PORTSTAT(x) \
+{ \
+ info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
+}
#else
-#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#define WR_RH_STAT(x) \
+ writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)\
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
#endif
-#define RD_RH_STAT roothub_status(&gohci)
-#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
/* request to virtual root hub */
-int rh_check_port_status(ohci_t *controller)
+int rh_check_port_status(struct ohci *controller)
{
__u32 temp, ndp, i;
int res;
res = -1;
- temp = roothub_a (controller);
+ temp = roothub_a(controller);
ndp = (temp & RH_A_NDP);
for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
+ temp = roothub_portstatus(controller, i);
/* check for a device disconnect */
if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) &&
- ((temp & RH_PS_CCS) == 0)) {
+ (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
res = i;
break;
}
@@ -1004,22 +1040,24 @@ int rh_check_port_status(ohci_t *controller)
}
static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
+ void *buffer, int transfer_len,
+ struct devrequest *cmd)
{
- void * data = buffer;
+ void *data = buffer;
int leni = transfer_len;
int len = 0;
int stat = 0;
__u32 datab[4];
- __u8 *data_buf = (__u8 *)datab;
+ __u8 *data_buf = (__u8 *) datab;
__u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
@@ -1028,189 +1066,216 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
return 0;
}
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = m16_swap (cmd->value);
- wIndex = m16_swap (cmd->index);
- wLength = m16_swap (cmd->length);
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap(cmd->value);
+ wIndex = m16_swap(cmd->index);
+ wLength = m16_swap(cmd->length);
info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
- dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
case RH_GET_STATUS:
- *(__u16 *) data_buf = m16_swap (1); OK (2);
+ *(__u16 *) data_buf = m16_swap(1);
+ OK(2);
case RH_GET_STATUS | RH_INTERFACE:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
+ *(__u16 *) data_buf = m16_swap(0);
+ OK(2);
case RH_GET_STATUS | RH_ENDPOINT:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
+ *(__u16 *) data_buf = m16_swap(0);
+ OK(2);
case RH_GET_STATUS | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (
- RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
- OK (4);
+ *(__u32 *) data_buf =
+ m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK(4);
case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+ *(__u32 *) data_buf = m32_swap(RD_RH_PORTSTAT);
+ OK(4);
case RH_CLEAR_FEATURE | RH_ENDPOINT:
switch (wValue) {
- case (RH_ENDPOINT_STALL): OK (0);
+ case (RH_ENDPOINT_STALL):
+ OK(0);
}
break;
case RH_CLEAR_FEATURE | RH_CLASS:
switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- OK(0);
- case (RH_C_HUB_OVER_CURRENT):
- WR_RH_STAT(RH_HS_OCIC); OK (0);
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC);
+ OK(0);
}
break;
case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
- case (RH_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
- case (RH_C_PORT_CONNECTION):
- WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
- case (RH_C_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
- case (RH_C_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
- case (RH_C_PORT_OVER_CURRENT):
- WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
- case (RH_C_PORT_RESET):
- WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_CCS);
+ OK(0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_POCI);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_LSDA);
+ OK(0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT(RH_PS_CSC);
+ OK(0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_PESC);
+ OK(0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSSC);
+ OK(0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT(RH_PS_OCIC);
+ OK(0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT(RH_PS_PRSC);
+ OK(0);
}
break;
case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
- case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PRS);
- OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
- case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PES );
- OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSS);
+ OK(0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PRS);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_PPS);
+ OK(0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PES);
+ OK(0);
}
break;
- case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+ case RH_SET_ADDRESS:
+ gohci.rh.devnum = wValue;
+ OK(0);
case RH_GET_DESCRIPTOR:
switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_dev_des), wLength));
+ data_buf = root_hub_dev_des;
+ OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des;
+ OK(len);
+ case (0x03): /* string descriptors */
+ if (wValue == 0x0300) {
len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des; OK(len);
- case (0x02): /* configuration descriptor */
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if (wValue == 0x0301) {
len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des; OK(len);
- case (0x03): /* string descriptors */
- if(wValue==0x0300) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- OK(len);
- }
- if(wValue==0x0301) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- OK(len);
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
}
- default:
- stat = USB_ST_STALLED;
+ default:
+ stat = USB_ST_STALLED;
}
break;
case RH_GET_DESCRIPTOR | RH_CLASS:
- {
- __u32 temp = roothub_a (&gohci);
-
- data_buf [0] = 9; /* min length; */
- data_buf [1] = 0x29;
- data_buf [2] = temp & RH_A_NDP;
- data_buf [3] = 0;
- if (temp & RH_A_PSM) /* per-port power switching? */
- data_buf [3] |= 0x1;
- if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf [3] |= 0x10;
- else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
- data_buf [3] |= 0x8;
-
- /* corresponds to data_buf[4-7] */
- datab [1] = 0;
- data_buf [5] = (temp & RH_A_POTPGT) >> 24;
- temp = roothub_b (&gohci);
- data_buf [7] = temp & RH_B_DR;
- if (data_buf [2] < 7) {
- data_buf [8] = 0xff;
- } else {
- data_buf [0] += 2;
- data_buf [8] = (temp & RH_B_DR) >> 8;
- data_buf [10] = data_buf [9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf [0], wLength));
- OK (len);
+ {
+ __u32 temp = roothub_a(&gohci);
+
+ data_buf[0] = 9; /* min length; */
+ data_buf[1] = 0x29;
+ data_buf[2] = temp & RH_A_NDP;
+ data_buf[3] = 0;
+ if (temp & RH_A_PSM)
+ /* per-port power switching? */
+ data_buf[3] |= 0x1;
+ if (temp & RH_A_NOCP)
+ /* no overcurrent reporting? */
+ data_buf[3] |= 0x10;
+ else if (temp & RH_A_OCPM)
+ /* per-port overcurrent reporting? */
+ data_buf[3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab[1] = 0;
+ data_buf[5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b(&gohci);
+ data_buf[7] = temp & RH_B_DR;
+ if (data_buf[2] < 7) {
+ data_buf[8] = 0xff;
+ } else {
+ data_buf[0] += 2;
+ data_buf[8] = (temp & RH_B_DR) >> 8;
+ data_buf[10] = data_buf[9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf[0], wLength));
+ OK(len);
}
- case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+ case RH_GET_CONFIGURATION:
+ *(__u8 *) data_buf = 0x01;
+ OK(1);
- case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+ case RH_SET_CONFIGURATION:
+ WR_RH_STAT(0x10000);
+ OK(0);
default:
- dbg ("unsupported root hub command");
+ dbg("unsupported root hub command");
stat = USB_ST_STALLED;
}
#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
+ ohci_dump_roothub(&gohci, 1);
#else
wait_ms(1);
#endif
len = min_t(int, len, leni);
if (data != data_buf)
- memcpy (data, data_buf, len);
+ memcpy(data, data_buf, len);
dev->act_len = len;
dev->status = stat;
#ifdef DEBUG
if (transfer_len)
urb_priv.actual_length = transfer_len;
- pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
+ 0 /*usb_pipein(pipe) */);
#else
wait_ms(1);
#endif
@@ -1223,7 +1288,7 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
/* common code for handling submit messages - used for all but root hub */
/* accesses. */
int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
+ int transfer_len, struct devrequest *setup, int interval)
{
int stat = 0;
int maxsize = usb_maxpacket(dev, pipe);
@@ -1234,20 +1299,21 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
dev->status = USB_ST_CRC_ERR;
return 0;
}
-
#ifdef DEBUG
urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
if (!maxsize) {
err("submit_common_message: pipesize for pipe %lx is zero",
- pipe);
+ pipe);
return -1;
}
- if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
+ 0) {
err("sohci_submit_job failed");
return -1;
}
@@ -1256,7 +1322,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* ohci_dump_status(&gohci); */
/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
+#define BULK_TO 5000 /* timeout in milliseconds */
if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
@@ -1304,13 +1370,14 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* we got an Root Hub Status Change interrupt */
if (got_rhsc) {
#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
+ ohci_dump_roothub(&gohci, 1);
#endif
got_rhsc = 0;
/* abuse timeout */
timeout = rh_check_port_status(&gohci);
if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
+#if 0 /* this does nothing useful, but leave it here
+ in case that changes */
/* the called routine adds 1 to the passed value */
usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
#endif
@@ -1328,53 +1395,55 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
dev->act_len = transfer_len;
#ifdef DEBUG
- pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
/* free TDs in urb_priv */
- urb_free_priv (&urb_priv);
+ urb_free_priv(&urb_priv);
return 0;
}
/* submit routines called from usb.c */
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
+ int transfer_len)
{
info("submit_bulk_msg");
return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
}
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
+ int transfer_len, struct devrequest *setup)
{
int maxsize = usb_maxpacket(dev, pipe);
info("submit_control_msg");
#ifdef DEBUG
urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
if (!maxsize) {
err("submit_control_message: pipesize for pipe %lx is zero",
- pipe);
+ pipe);
return -1;
}
if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
gohci.rh.dev = dev;
/* root hub - redirect */
return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
+ setup);
}
return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
+ int transfer_len, int interval)
{
info("submit_int_msg");
return -1;
@@ -1386,16 +1455,17 @@ int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
/* reset the HC and BUS */
-static int hc_reset (ohci_t *ohci)
+static int hc_reset(struct ohci *ohci)
{
int timeout = 30;
- int smm_timeout = 50; /* 0,5 sec */
+ int smm_timeout = 50; /* 0,5 sec */
- if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
- writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ /* SMM owns the HC - request ownership */
+ writel(OHCI_OCR, &ohci->regs->cmdstatus);
info("USB HC TakeOver from SMM");
- while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
- wait_ms (10);
+ while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms(10);
if (--smm_timeout == 0) {
err("USB HC TakeOver failed!");
return -1;
@@ -1404,23 +1474,22 @@ static int hc_reset (ohci_t *ohci)
}
/* Disable HC interrupts */
- writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+ writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
- ohci->slot_name,
- readl (&ohci->regs->control));
+ ohci->slot_name, readl(&ohci->regs->control));
/* Reset USB (needed by some controllers) */
- writel (0, &ohci->regs->control);
+ writel(0, &ohci->regs->control);
/* HC Reset requires max 10 us delay */
- writel (OHCI_HCR, &ohci->regs->cmdstatus);
- while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ writel(OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
if (--timeout == 0) {
err("USB HC reset timed out!");
return -1;
}
- udelay (1);
+ udelay(1);
}
return 0;
}
@@ -1431,7 +1500,7 @@ static int hc_reset (ohci_t *ohci)
* enable interrupts
* connect the virtual root hub */
-static int hc_start (ohci_t * ohci)
+static int hc_start(struct ohci *ohci)
{
__u32 mask;
unsigned int fminterval;
@@ -1441,44 +1510,45 @@ static int hc_start (ohci_t * ohci)
/* Tell the controller where the control and bulk lists are
* The lists are empty now. */
- writel (0, &ohci->regs->ed_controlhead);
- writel (0, &ohci->regs->ed_bulkhead);
+ writel(0, &ohci->regs->ed_controlhead);
+ writel(0, &ohci->regs->ed_bulkhead);
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+ /* a reset clears this */
+ writel((__u32) ohci->hcca, &ohci->regs->hcca);
fminterval = 0x2edf;
- writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
- writel (fminterval, &ohci->regs->fminterval);
- writel (0x628, &ohci->regs->lsthresh);
+ writel(fminterval, &ohci->regs->fminterval);
+ writel(0x628, &ohci->regs->lsthresh);
/* start controller operations */
ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
/* disable all interrupts */
mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
- OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
- OHCI_INTR_OC | OHCI_INTR_MIE);
- writel (mask, &ohci->regs->intrdisable);
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel(mask, &ohci->regs->intrdisable);
/* clear all interrupts */
mask &= ~OHCI_INTR_MIE;
- writel (mask, &ohci->regs->intrstatus);
+ writel(mask, &ohci->regs->intrstatus);
/* Choose the interrupts we care about now - but w/o MIE */
mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
- writel (mask, &ohci->regs->intrenable);
+ writel(mask, &ohci->regs->intrenable);
#ifdef OHCI_USE_NPS
/* required for AMD-756 and some Mac platforms */
- writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
- &ohci->regs->roothub.a);
- writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
+ writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
/* POTPGT delay is bits 24-31, in 2 ms units. */
- mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+ mdelay((roothub_a(ohci) >> 23) & 0x1fe);
/* connect the virtual root hub */
ohci->rh.devnum = 0;
@@ -1490,30 +1560,34 @@ static int hc_start (ohci_t * ohci)
/* an interrupt happens */
-static int
-hc_interrupt (void)
+static int hc_interrupt(void)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
struct ohci_regs *regs = ohci->regs;
int ints;
int stat = -1;
if ((ohci->hcca->done_head != 0) &&
- !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ !(m32_swap(ohci->hcca->done_head) & 0x01)) {
- ints = OHCI_INTR_WDH;
+ ints = OHCI_INTR_WDH;
- } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
- ohci->disabled++;
- err ("%s device removed!", ohci->slot_name);
- return -1;
-
- } else if ((ints &= readl (&regs->intrenable)) == 0) {
- dbg("hc_interrupt: returning..\n");
- return 0xff;
+ } else {
+ ints = readl(&regs->intrstatus);
+ if (ints == ~(u32) 0) {
+ ohci->disabled++;
+ err("%s device removed!", ohci->slot_name);
+ return -1;
+ }
+ ints &= readl(&regs->intrenable);
+ if (ints == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
+ }
}
- /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+ /* dbg("Interrupt: %x frame: %x", ints,
+ le16_to_cpu(ohci->hcca->frame_no)); */
if (ints & OHCI_INTR_RHSC) {
got_rhsc = 1;
@@ -1522,48 +1596,48 @@ hc_interrupt (void)
if (ints & OHCI_INTR_UE) {
ohci->disabled++;
- err ("OHCI Unrecoverable Error, controller usb-%s disabled",
- ohci->slot_name);
+ err("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
/* e.g. due to PCI Master/Target Abort */
#ifdef DEBUG
- ohci_dump (ohci, 1);
+ ohci_dump(ohci, 1);
#else
- wait_ms(1);
+ wait_ms(1);
#endif
/* FIXME: be optimistic, hope that bug won't repeat often. */
/* Make some non-interrupt context restart the controller. */
/* Count and limit the retries though; either hardware or */
/* software errors can go forever... */
- hc_reset (ohci);
+ hc_reset(ohci);
return -1;
}
if (ints & OHCI_INTR_WDH) {
wait_ms(1);
- writel (OHCI_INTR_WDH, &regs->intrdisable);
- stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
- writel (OHCI_INTR_WDH, &regs->intrenable);
+ writel(OHCI_INTR_WDH, &regs->intrdisable);
+ stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
+ writel(OHCI_INTR_WDH, &regs->intrenable);
}
if (ints & OHCI_INTR_SO) {
dbg("USB Schedule overrun\n");
- writel (OHCI_INTR_SO, &regs->intrenable);
+ writel(OHCI_INTR_SO, &regs->intrenable);
stat = -1;
}
/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
if (ints & OHCI_INTR_SF) {
- unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
wait_ms(1);
- writel (OHCI_INTR_SF, &regs->intrdisable);
+ writel(OHCI_INTR_SF, &regs->intrdisable);
if (ohci->ed_rm_list[frame] != NULL)
- writel (OHCI_INTR_SF, &regs->intrenable);
+ writel(OHCI_INTR_SF, &regs->intrenable);
stat = 0xff;
}
- writel (ints, &regs->intrstatus);
+ writel(ints, &regs->intrstatus);
return stat;
}
@@ -1573,12 +1647,12 @@ hc_interrupt (void)
/* De-allocate all resources.. */
-static void hc_release_ohci (ohci_t *ohci)
+static void hc_release_ohci(struct ohci *ohci)
{
- dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+ dbg("USB HC release ohci usb-%s", ohci->slot_name);
if (!ohci->disabled)
- hc_reset (ohci);
+ hc_reset(ohci);
}
/*-------------------------------------------------------------------------*/
@@ -1590,44 +1664,44 @@ static char ohci_inited = 0;
int usb_lowlevel_init(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
- memset (&gohci, 0, sizeof (ohci_t));
- memset (&urb_priv, 0, sizeof (urb_priv_t));
+ memset(&gohci, 0, sizeof(struct ohci));
+ memset(&urb_priv, 0, sizeof(struct urb_priv));
/* align the storage */
- if ((__u32)&ghcca[0] & 0xff) {
+ if ((__u32) &ghcca[0] & 0xff) {
err("HCCA not aligned!!");
return -1;
}
phcca = &ghcca[0];
info("aligned ghcca %p", phcca);
memset(&ohci_dev, 0, sizeof(struct ohci_device));
- if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ if ((__u32) &ohci_dev.ed[0] & 0x7) {
err("EDs not aligned!!");
return -1;
}
- memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
- if ((__u32)gtd & 0x7) {
+ memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
+ if ((__u32) gtd & 0x7) {
err("TDs not aligned!!");
return -1;
}
ptd = gtd;
gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
+ memset(phcca, 0, sizeof(struct ohci_hcca));
gohci.disabled = 1;
gohci.sleeping = 0;
@@ -1637,8 +1711,8 @@ int usb_lowlevel_init(void)
gohci.flags = 0;
gohci.slot_name = "s3c2400";
- if (hc_reset (&gohci) < 0) {
- hc_release_ohci (&gohci);
+ if (hc_reset(&gohci) < 0) {
+ hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
@@ -1646,19 +1720,18 @@ int usb_lowlevel_init(void)
/* FIXME this is a second HC reset; why?? */
gohci.hc_control = OHCI_USB_RESET;
- writel (gohci.hc_control, &gohci.regs->control);
- wait_ms (10);
+ writel(gohci.hc_control, &gohci.regs->control);
+ wait_ms(10);
- if (hc_start (&gohci) < 0) {
- err ("can't start usb-%s", gohci.slot_name);
- hc_release_ohci (&gohci);
+ if (hc_start(&gohci) < 0) {
+ err("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
}
-
#ifdef DEBUG
- ohci_dump (&gohci, 1);
+ ohci_dump(&gohci, 1);
#else
wait_ms(1);
#endif
@@ -1670,7 +1743,7 @@ int usb_lowlevel_init(void)
int usb_lowlevel_stop(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* this gets called really early - before the controller has */
/* even been initialized! */
@@ -1678,7 +1751,7 @@ int usb_lowlevel_stop(void)
return 0;
/* TODO release any interrupts, etc. */
/* call hc_release_ohci() here ? */
- hc_reset (&gohci);
+ hc_reset(&gohci);
/* may not want to do this */
clk_power->CLKCON &= ~(1 << 4);
return 0;
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.h b/cpu/arm920t/s3c24x0/usb_ohci.h
index 8e093fbfc..f272d7885 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.h
+++ b/cpu/arm920t/s3c24x0/usb_ohci.h
@@ -11,22 +11,22 @@
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
- /* No Error */ 0,
- /* CRC Error */ USB_ST_CRC_ERR,
- /* Bit Stuff */ USB_ST_BIT_ERR,
- /* Data Togg */ USB_ST_CRC_ERR,
- /* Stall */ USB_ST_STALLED,
- /* DevNotResp */ -1,
- /* PIDCheck */ USB_ST_BIT_ERR,
- /* UnExpPID */ USB_ST_BIT_ERR,
- /* DataOver */ USB_ST_BUF_ERR,
- /* DataUnder */ USB_ST_BUF_ERR,
- /* reservd */ -1,
- /* reservd */ -1,
- /* BufferOver */ USB_ST_BUF_ERR,
- /* BuffUnder */ USB_ST_BUF_ERR,
- /* Not Access */ -1,
- /* Not Access */ -1
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
};
/* ED States */
@@ -55,14 +55,13 @@ struct ed {
struct usb_device *usb_dev;
__u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
+} __attribute__ ((aligned(16)));
/* TD info field */
#define TD_CC 0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
+#define TD_CC_SET(td_p, cc) \
+ {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
@@ -112,8 +111,7 @@ struct td {
__u32 data;
__u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
+} __attribute__ ((aligned(32)));
#define OHCI_ED_SKIP (1 << 14)
@@ -123,15 +121,14 @@ typedef struct td td_t;
* told the base address of. It must be 256-byte aligned.
*/
-#define NUM_INTS 32 /* part of the OHCI standard */
+#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
- __u32 int_table[NUM_INTS]; /* Interrupt ED table */
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
- __u32 done_head; /* info returned for an interrupt */
- u8 reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute__ ((aligned(256)));
/*
* Maximum number of root hub ports.
@@ -145,35 +142,34 @@ struct ohci_hcca {
*/
struct ohci_regs {
/* control and status registers */
- __u32 revision;
- __u32 control;
- __u32 cmdstatus;
- __u32 intrstatus;
- __u32 intrenable;
- __u32 intrdisable;
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
/* memory pointers */
- __u32 hcca;
- __u32 ed_periodcurrent;
- __u32 ed_controlhead;
- __u32 ed_controlcurrent;
- __u32 ed_bulkhead;
- __u32 ed_bulkcurrent;
- __u32 donehead;
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
/* frame counters */
- __u32 fminterval;
- __u32 fmremaining;
- __u32 fmnumber;
- __u32 periodicstart;
- __u32 lsthresh;
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
/* Root hub ports */
- struct ohci_roothub_regs {
- __u32 a;
- __u32 b;
- __u32 status;
- __u32 portstatus[MAX_ROOT_PORTS];
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
} roothub;
-} __attribute__((aligned(32)));
-
+} __attribute__ ((aligned(32)));
/* OHCI CONTROL AND STATUS REGISTER MASKS */
@@ -221,11 +217,10 @@ struct ohci_regs {
#define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
/* Virtual Root HUB */
struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- void *dev; /* was urb */
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
void *int_addr;
int send;
int interval;
@@ -288,52 +283,52 @@ struct virt_root_hub {
/* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */
-#define RH_PS_CCS 0x00000001 /* current connect status */
-#define RH_PS_PES 0x00000002 /* port enable status*/
-#define RH_PS_PSS 0x00000004 /* port suspend status */
-#define RH_PS_POCI 0x00000008 /* port over current indicator */
-#define RH_PS_PRS 0x00000010 /* port reset status */
-#define RH_PS_PPS 0x00000100 /* port power status */
-#define RH_PS_LSDA 0x00000200 /* low speed device attached */
-#define RH_PS_CSC 0x00010000 /* connect status change */
-#define RH_PS_PESC 0x00020000 /* port enable status change */
-#define RH_PS_PSSC 0x00040000 /* port suspend status change */
-#define RH_PS_OCIC 0x00080000 /* over current indicator change */
-#define RH_PS_PRSC 0x00100000 /* port reset status change */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status */
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */
-#define RH_HS_LPS 0x00000001 /* local power status */
-#define RH_HS_OCI 0x00000002 /* over current indicator */
-#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC 0x00010000 /* local power status change */
-#define RH_HS_OCIC 0x00020000 /* over current indicator change */
-#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */
-#define RH_B_DR 0x0000ffff /* device removable flags */
-#define RH_B_PPCM 0xffff0000 /* port power control mask */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */
-#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
-#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
/* urb */
#define N_URB_TD 48
-typedef struct
-{
- ed_t *ed;
- __u16 length; /* number of tds associated with this request */
- __u16 td_cnt; /* number of tds already serviced */
- int state;
+struct urb_priv {
+ struct ed *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
unsigned long pipe;
int actual_length;
- td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
+ struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs
+ associated with this request */
+};
#define URB_DEL 1
/*
@@ -344,7 +339,7 @@ typedef struct
*/
-typedef struct ohci {
+struct ohci {
struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma; */
@@ -355,29 +350,29 @@ typedef struct ohci {
struct ohci_regs *regs; /* OHCI controller's memory */
- ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
- ed_t *ed_bulktail; /* last endpoint of bulk list */
- ed_t *ed_controltail; /* last endpoint of control list */
+ struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ struct ed *ed_bulktail; /* last endpoint of bulk list */
+ struct ed *ed_controltail; /* last endpoint of control list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_device *dev[32];
struct virt_root_hub rh;
const char *slot_name;
-} ohci_t;
+};
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device {
- ed_t ed[NUM_EDS];
+ struct ed ed[NUM_EDS];
int ed_cnt;
};
/* hcd */
/* endpoint */
-static int ep_link (ohci_t * ohci, ed_t * ed);
-static int ep_unlink (ohci_t * ohci, ed_t * ed);
-static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
+static int ep_link(struct ohci *ohci, struct ed *ed);
+static int ep_unlink(struct ohci *ohci, struct ed *ed);
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
/*-------------------------------------------------------------------------*/
@@ -385,13 +380,13 @@ static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
#define NUM_TD 64
/* +1 so we can align the storage */
-td_t gtd[NUM_TD + 1];
+struct td gtd[NUM_TD + 1];
/* pointers to aligned storage */
-td_t *ptd;
+struct td *ptd;
/* TDs ... */
-static inline struct td *td_alloc (struct usb_device *usb_dev)
+static inline struct td *td_alloc(struct usb_device *usb_dev)
{
int i;
struct td *td;
@@ -408,7 +403,7 @@ static inline struct td *td_alloc (struct usb_device *usb_dev)
return td;
}
-static inline void ed_free (struct ed *ed)
+static inline void ed_free(struct ed *ed)
{
ed->usb_dev = NULL;
}
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 27f38b808..114427a16 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -37,7 +37,7 @@
.globl _start
-_start: b start_code
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
@@ -109,13 +109,13 @@ start_code:
/*
* set the cpu to SVC32 mode
*/
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
+ mrs r0, cpsr
+ bic r0, r0, #0x1f
+ orr r0, r0, #0xd3
+ msr cpsr, r0
- bl coloured_LED_init
- bl red_LED_on
+ bl coloured_LED_init
+ bl red_LED_on
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
@@ -135,19 +135,19 @@ copyex:
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
@@ -180,8 +180,8 @@ copyex:
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
@@ -198,8 +198,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -297,8 +297,8 @@ cpu_init_crit:
#define S_R1 4
#define S_R0 0
-#define MODE_SVC 0x13
-#define I_BIT 0x80
+#define MODE_SVC 0x13
+#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
@@ -311,7 +311,8 @@ cpu_init_crit:
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ /* set base 2 words into abort stack */
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
@@ -324,12 +325,12 @@ cpu_init_crit:
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
- add r7, sp, #S_PC
- stmdb r7, {sp, lr}^ @ Calling SP, LR
- str lr, [r7, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r7, #4] @ Save CPSR
- str r0, [r7, #8] @ Save OLD_R0
+ add r7, sp, #S_PC
+ stmdb r7, {sp, lr}^ @ Calling SP, LR
+ str lr, [r7, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r7, #4] @ Save CPSR
+ str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm
@@ -338,18 +339,20 @@ cpu_init_crit:
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ /* return & move spsr_svc into cpsr */
+ subs pc, lr, #4
.endm
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ /* reserve a couple spots in abort stack */
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
- str lr, [r13, #4]
+ str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S
index 804332258..4421b6a99 100644
--- a/cpu/arm926ejs/start.S
+++ b/cpu/arm926ejs/start.S
@@ -172,6 +172,7 @@ stack_setup:
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
sub sp, r0, #12 /* leave 3 words for abort-stack */
+ bic sp, r0, #7 /* 8-byte align stack for ABI compliance */
clear_bss:
ldr r0, _bss_start /* find start of bss segment */
diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c
index 079c84870..8b8cd6d61 100644
--- a/cpu/arm_cortexa8/omap3/mem.c
+++ b/cpu/arm_cortexa8/omap3/mem.c
@@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr;
struct gpmc *gpmc_cfg;
#if defined(CONFIG_CMD_NAND)
-static u32 gpmc_m_nand[GPMC_MAX_REG] = {
+static const u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG1,
M_NAND_GPMC_CONFIG2,
M_NAND_GPMC_CONFIG3,
@@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
#endif
#if defined(CONFIG_CMD_ONENAND)
-static u32 gpmc_onenand[GPMC_MAX_REG] = {
+static const u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG1,
ONENAND_GPMC_CONFIG2,
ONENAND_GPMC_CONFIG3,
@@ -92,7 +92,7 @@ void make_cs1_contiguous(void)
u32 size, a_add_low, a_add_high;
size = get_sdr_cs_size(CS0);
- size /= SZ_32M; /* find size to offset CS1 */
+ size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
a_add_high = (size & 3) << 8; /* set up low field */
a_add_low = (size & 0x3C) >> 2; /* set up high field */
writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
@@ -192,7 +192,7 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
-void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
+void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &cs->config7);
@@ -218,12 +218,16 @@ void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
void gpmc_init(void)
{
/* putting a blanket check on GPMC based on ZeBu for now */
- u32 *gpmc_config = NULL;
gpmc_cfg = (struct gpmc *)GPMC_BASE;
+#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND)
+ const u32 *gpmc_config = NULL;
u32 base = 0;
u32 size = 0;
+#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND)
u32 f_off = CONFIG_SYS_MONITOR_LEN;
u32 f_sec = 0;
+#endif
+#endif
u32 config = 0;
/* global settings */
@@ -249,7 +253,7 @@ void gpmc_init(void)
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_NAND)
f_off = SMNAND_ENV_OFFSET;
- f_sec = SZ_128K;
+ f_sec = (128 << 10); /* 128 KiB */
/* env setup */
boot_flash_base = base;
boot_flash_off = f_off;
@@ -265,7 +269,7 @@ void gpmc_init(void)
enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_ONENAND)
f_off = ONENAND_ENV_OFFSET;
- f_sec = SZ_128K;
+ f_sec = (128 << 10); /* 128 KiB */
/* env setup */
boot_flash_base = base;
boot_flash_off = f_off;
diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c
index 765aaf2b3..31b20033c 100644
--- a/cpu/arm_cortexa8/omap3/sys_info.c
+++ b/cpu/arm_cortexa8/omap3/sys_info.c
@@ -124,7 +124,7 @@ u32 get_sdr_cs_size(u32 cs)
/* get ram size field */
size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
size &= 0x3FF; /* remove unwanted bits */
- size *= SZ_2M; /* find size in MB */
+ size <<= 21; /* multiply by 2 MiB to find size in MB */
return size;
}
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile b/cpu/arm_cortexa8/s5pc1xx/Makefile
new file mode 100644
index 000000000..e08d9d87b
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS = reset.o
+
+COBJS += cache.o
+COBJS += clock.o
+COBJS += cpu_info.o
+COBJS += timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/cpu/arm_cortexa8/s5pc1xx/cache.c b/cpu/arm_cortexa8/s5pc1xx/cache.c
new file mode 100644
index 000000000..8652a45ff
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/cache.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+void l2_cache_enable(void)
+{
+ unsigned long i;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+}
+
+void l2_cache_disable(void)
+{
+ unsigned long i;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+}
diff --git a/cpu/arm_cortexa8/s5pc1xx/clock.c b/cpu/arm_cortexa8/s5pc1xx/clock.c
new file mode 100644
index 000000000..a9e78dd79
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/clock.c
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
+#define CLK_M 0
+#define CLK_D 1
+#define CLK_P 2
+
+#ifndef CONFIG_SYS_CLK_FREQ_C100
+#define CONFIG_SYS_CLK_FREQ_C100 12000000
+#endif
+#ifndef CONFIG_SYS_CLK_FREQ_C110
+#define CONFIG_SYS_CLK_FREQ_C110 24000000
+#endif
+
+unsigned long (*get_pclk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+/* s5pc110: return pll clock frequency */
+static unsigned long s5pc100_get_pll_clk(int pllreg)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case HPLL:
+ r = readl(&clk->hpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [23:16]
+ * EPLL_CON: MIDV [23:16]
+ * HPLL_CON: MIDV [23:16]
+ */
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x0ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ freq = CONFIG_SYS_CLK_FREQ_C100;
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc100: return pll clock frequency */
+static unsigned long s5pc110_get_pll_clk(int pllreg)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C110;
+ if (pllreg == APLL) {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ } else
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc110: return ARM clock frequency */
+static unsigned long s5pc110_get_arm_clk(void)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div0);
+
+ /* APLL_RATIO: [2:0] */
+ apll_ratio = div & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll;
+
+ return armclk;
+}
+
+/* s5pc100: return ARM clock frequency */
+static unsigned long s5pc100_get_arm_clk(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio, arm_ratio;
+
+ div = readl(&clk->div0);
+
+ /* ARM_RATIO: [6:4] */
+ arm_ratio = (div >> 4) & 0x7;
+ /* APLL_RATIO: [0] */
+ apll_ratio = div & 0x1;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll / (arm_ratio + 1);
+
+ return armclk;
+}
+
+/* s5pc100: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = readl(&clk->div0);
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* s5pc100: return PCLKD1 frequency */
+static unsigned long get_pclkd1(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long d1_bus, pclkd1;
+ uint div, d1_bus_ratio, pclkd1_ratio;
+
+ div = readl(&clk->div0);
+ /* D1_BUS_RATIO: [14:12] */
+ d1_bus_ratio = (div >> 12) & 0x7;
+ /* PCLKD1_RATIO: [18:16] */
+ pclkd1_ratio = (div >> 16) & 0x7;
+
+ /* ASYNC Mode */
+ d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
+ pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+ return pclkd1;
+}
+
+/* s5pc110: return HCLKs frequency */
+static unsigned long get_hclk_sys(int dom)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long hclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int hclk_sys_ratio;
+
+ if (dom == CLK_M)
+ return get_hclk();
+
+ div = readl(&clk->div0);
+
+ /*
+ * HCLK_MSYS_RATIO: [10:8]
+ * HCLK_DSYS_RATIO: [19:16]
+ * HCLK_PSYS_RATIO: [27:24]
+ */
+ offset = 8 + (dom << 0x3);
+
+ hclk_sys_ratio = (div >> offset) & 0xf;
+
+ hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+ return hclk;
+}
+
+/* s5pc110: return PCLKs frequency */
+static unsigned long get_pclk_sys(int dom)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int pclk_sys_ratio;
+
+ div = readl(&clk->div0);
+
+ /*
+ * PCLK_MSYS_RATIO: [14:12]
+ * PCLK_DSYS_RATIO: [22:20]
+ * PCLK_PSYS_RATIO: [30:28]
+ */
+ offset = 12 + (dom << 0x3);
+
+ pclk_sys_ratio = (div >> offset) & 0x7;
+
+ pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
+
+ return pclk;
+}
+
+/* s5pc110: return peripheral clock frequency */
+static unsigned long s5pc110_get_pclk(void)
+{
+ return get_pclk_sys(CLK_P);
+}
+
+/* s5pc100: return peripheral clock frequency */
+static unsigned long s5pc100_get_pclk(void)
+{
+ return get_pclkd1();
+}
+
+void s5pc1xx_clock_init(void)
+{
+ if (cpu_is_s5pc110()) {
+ get_pll_clk = s5pc110_get_pll_clk;
+ get_arm_clk = s5pc110_get_arm_clk;
+ get_pclk = s5pc110_get_pclk;
+ } else {
+ get_pll_clk = s5pc100_get_pll_clk;
+ get_arm_clk = s5pc100_get_arm_clk;
+ get_pclk = s5pc100_get_pclk;
+ }
+}
diff --git a/cpu/arm_cortexa8/s5pc1xx/cpu_info.c b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
new file mode 100644
index 000000000..f16c0ff13
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/cpu_info.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+/* Default is s5pc100 */
+unsigned int s5pc1xx_cpu_id = 0xC100;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID);
+ s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12);
+
+ s5pc1xx_clock_init();
+
+ return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+ return s5pc1xx_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ printf("CPU:\tS5P%X@%sMHz\n",
+ s5pc1xx_cpu_id, strmhz(buf, get_arm_clk()));
+
+ return 0;
+}
+#endif
diff --git a/cpu/arm_cortexa8/s5pc1xx/reset.S b/cpu/arm_cortexa8/s5pc1xx/reset.S
new file mode 100644
index 000000000..7f6ff9c35
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/reset.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/cpu.h>
+
+#define S5PC100_SWRESET 0xE0200000
+#define S5PC110_SWRESET 0xE0102000
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, =S5PC1XX_PRO_ID
+ ldr r2, [r1]
+ ldr r4, =0x00010000
+ and r4, r2, r4
+ cmp r4, #0
+ bne 110f
+ /* S5PC100 */
+ ldr r1, =S5PC100_SWRESET
+ ldr r2, =0xC100
+ b 200f
+110: /* S5PC110 */
+ ldr r1, =S5PC110_SWRESET
+ mov r2, #1
+200:
+ str r2, [r1]
+_loop_forever:
+ b _loop_forever
diff --git a/cpu/arm_cortexa8/s5pc1xx/timer.c b/cpu/arm_cortexa8/s5pc1xx/timer.c
new file mode 100644
index 000000000..cdba5d934
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/timer.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/clk.h>
+
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+#define MUX4_DIV_SHIFT 16
+
+#define TCON_TIMER4_SHIFT 20
+
+static unsigned long count_value;
+
+/* Internal tick units */
+static unsigned long long timestamp; /* Monotonic incrementing timer */
+static unsigned long lastdec; /* Last decremneter snapshot */
+
+/* macro to read the 16 bit timer */
+static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void)
+{
+ if (cpu_is_s5pc110())
+ return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE;
+ else
+ return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE;
+}
+
+int timer_init(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+ u32 val;
+
+ /*
+ * @ PWM Timer 4
+ * Timer Freq(HZ) =
+ * PCLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ /* set prescaler : 16 */
+ /* set divider : 2 */
+ writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
+ writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
+
+ if (count_value == 0) {
+ /* reset initial value */
+ /* count_value = 2085937.5(HZ) (per 1 sec)*/
+ count_value = get_pclk() / ((PRESCALER_1 + 1) *
+ (MUX_DIV_2 + 1));
+
+ /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
+ count_value = count_value / 100;
+ }
+
+ /* set count value */
+ writel(count_value, &timer->tcntb4);
+ lastdec = count_value;
+
+ val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) |
+ S5PC1XX_TCON4_AUTO_RELOAD;
+
+ /* auto reload & manual update */
+ writel(val | S5PC1XX_TCON4_UPDATE, &timer->tcon);
+
+ /* start PWM timer 4 */
+ writel(val | S5PC1XX_TCON4_START, &timer->tcon);
+
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(unsigned long t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+ unsigned long tmo, tmp;
+
+ if (usec >= 1000) {
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value / 10);
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ * count_value / 10;
+ tmo /= (1000 * 1000);
+ }
+
+ /* get current timestamp */
+ tmp = get_timer(0);
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastdec value */
+ /* else, set advancing stamp wake up time */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ /* loop till event */
+ while (get_timer_masked() < tmo)
+ ; /* nop */
+}
+
+void reset_timer_masked(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+
+ /* reset time */
+ lastdec = readl(&timer->tcnto4);
+ timestamp = 0;
+}
+
+unsigned long get_timer_masked(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+ unsigned long now = readl(&timer->tcnto4);
+
+ if (lastdec >= now)
+ timestamp += lastdec - now;
+ else
+ timestamp += lastdec + count_value - now;
+
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c
index 13443cbd8..daf73a6e5 100644
--- a/cpu/mpc83xx/fdt.c
+++ b/cpu/mpc83xx/fdt.c
@@ -69,6 +69,45 @@ void ft_cpu_setup(void *blob, bd_t *bd)
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
fdt_fixup_ethernet(blob);
+#ifdef CONFIG_MPC8313
+ /*
+ * mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
+ * h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
+ * so if on Rev. 2 (and higher) h/w, we fix them up here
+ */
+ if (REVID_MAJOR(immr->sysconf.spridr) >= 2) {
+ int nodeoffset, path;
+ const char *prop;
+
+ nodeoffset = fdt_path_offset(blob, "/aliases");
+ if (nodeoffset >= 0) {
+#if defined(CONFIG_HAS_ETH0)
+ prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
+ if (prop) {
+ u32 tmp[] = { 32, 0x8, 33, 0x8, 34, 0x8 };
+
+ path = fdt_path_offset(blob, prop);
+ prop = fdt_getprop(blob, path, "interrupts", 0);
+ if (prop)
+ fdt_setprop(blob, path, "interrupts",
+ &tmp, sizeof(tmp));
+ }
+#endif
+#if defined(CONFIG_HAS_ETH1)
+ prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
+ if (prop) {
+ u32 tmp[] = { 35, 0x8, 36, 0x8, 37, 0x8 };
+
+ path = fdt_path_offset(blob, prop);
+ prop = fdt_getprop(blob, path, "interrupts", 0);
+ if (prop)
+ fdt_setprop(blob, path, "interrupts",
+ &tmp, sizeof(tmp));
+ }
+#endif
+ }
+ }
+#endif
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a9a0ac345..e1b00a74c 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -608,10 +608,17 @@ int checkcpu (void)
break;
}
- printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock),
+ printf (" at %s MHz (PLB=%lu OPB=%lu EBC=%lu",
+ strmhz(buf, clock),
sys_info.freqPLB / 1000000,
get_OPB_freq() / 1000000,
sys_info.freqEBC / 1000000);
+#if defined(CONFIG_PCI) && \
+ (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+ printf(" PCI=%lu MHz", sys_info.freqPCI / 1000000);
+#endif
+ printf(")\n");
if (addstr[0] != 0)
printf(" %s\n", addstr);
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index a00da408c..ccd999367 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -330,3 +330,72 @@ int cpu_init_r (void)
return 0;
}
+
+#if defined(CONFIG_PCI) && \
+ (defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
+ defined(CONFIG_440GR) || defined(CONFIG_440GRX))
+/*
+ * 440EP(x)/GR(x) PCI async/sync clocking restriction:
+ *
+ * In asynchronous PCI mode, the synchronous PCI clock must meet
+ * certain requirements. The following equation describes the
+ * relationship that must be maintained between the asynchronous PCI
+ * clock and synchronous PCI clock. Select an appropriate PCI:PLB
+ * ratio to maintain the relationship:
+ *
+ * AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
+ */
+static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
+{
+ if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
+ return 0;
+ else
+ return 1;
+}
+
+int ppc4xx_pci_sync_clock_config(u32 async)
+{
+ sys_info_t sys_info;
+ u32 sync;
+ int div;
+ u32 reg;
+ u32 spcid_val[] = {
+ CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
+ CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
+
+ get_sys_info(&sys_info);
+ sync = sys_info.freqPCI;
+
+ /*
+ * First check if the equation above is met
+ */
+ if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
+ /*
+ * Reconfigure PCI sync clock to meet the equation.
+ * Start with highest possible PCI sync frequency
+ * (divider 1).
+ */
+ for (div = 1; div <= 4; div++) {
+ sync = sys_info.freqPLB / div;
+ if (ppc4xx_pci_sync_clock_ok(sync, async))
+ break;
+ }
+
+ if (div <= 4) {
+ mtcpr(CPR0_SPCID, spcid_val[div]);
+
+ mfcpr(CPR0_ICFG, reg);
+ reg |= CPR0_ICFG_RLI_MASK;
+ mtcpr(CPR0_ICFG, reg);
+
+ /* do chip reset */
+ mtspr(SPRN_DBCR0, 0x20000000);
+ } else {
+ /* Impossible to configure the PCI sync clock */
+ return -1;
+ }
+ }
+
+ return 0;
+}
+#endif
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index 496e0285b..15a184b5c 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -42,7 +42,7 @@ void __ft_board_setup(void *blob, bd_t *bd)
u32 bxcr;
u32 ranges[EBC_NUM_BANKS * 4];
u32 *p = ranges;
- char *ebc_path = "/plb/opb/ebc";
+ char ebc_path[] = "/plb/opb/ebc";
ft_cpu_setup(blob, bd);
@@ -59,11 +59,17 @@ void __ft_board_setup(void *blob, bd_t *bd)
*p++ = 0;
*p++ = bxcr & EBC_BXCR_BAS_MASK;
*p++ = EBC_BXCR_BANK_SIZE(bxcr);
+
+#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
+ /* Try to update reg property in nor flash node too */
+ fdt_fixup_nor_flash_size(blob, i,
+ EBC_BXCR_BANK_SIZE(bxcr));
+#endif
}
}
/* Some 405 PPC's have EBC as direct PLB child in the dts */
- if (fdt_path_offset(blob, "/plb/opb/ebc") < 0)
+ if (fdt_path_offset(blob, ebc_path) < 0)
strcpy(ebc_path, "/plb/ebc");
rc = fdt_find_and_setprop(blob, ebc_path, "ranges", ranges,
(p - ranges) * sizeof(u32), 1);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 07:25:40 +0000