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-rw-r--r--drivers/qe/qe.c23
-rw-r--r--drivers/qe/qe.h18
-rw-r--r--drivers/qe/uec.c224
-rw-r--r--drivers/qe/uec.h56
4 files changed, 138 insertions, 183 deletions
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f114fe06a..8882c4f62 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@@ -108,14 +108,23 @@ static void qe_sdma_init(void)
out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
}
-static u8 thread_snum[QE_NUM_OF_SNUM] = {
+/* This table is a list of the serial numbers of the Threads, taken from the
+ * "SNUM Table" chart in the QE Reference Manual. The order is not important,
+ * we just need to know what the SNUMs are for the threads.
+ */
+static u8 thread_snum[] = {
0x04, 0x05, 0x0c, 0x0d,
0x14, 0x15, 0x1c, 0x1d,
0x24, 0x25, 0x2c, 0x2d,
0x34, 0x35, 0x88, 0x89,
0x98, 0x99, 0xa8, 0xa9,
0xb8, 0xb9, 0xc8, 0xc9,
- 0xd8, 0xd9, 0xe8, 0xe9
+ 0xd8, 0xd9, 0xe8, 0xe9,
+ 0x08, 0x09, 0x18, 0x19,
+ 0x28, 0x29, 0x38, 0x39,
+ 0x48, 0x49, 0x58, 0x59,
+ 0x68, 0x69, 0x78, 0x79,
+ 0x80, 0x81
};
static void qe_snums_init(void)
@@ -258,9 +267,6 @@ int qe_set_mii_clk_src(int ucc_num)
return 0;
}
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC 2
-
/* Firmware information stored here for qe_get_firmware_info() */
static struct qe_firmware_info qe_firmware_info;
@@ -473,5 +479,6 @@ U_BOOT_CMD(
qe, 4, 0, qe_cmd,
"QUICC Engine commands",
"fw <addr> [<length>] - Upload firmware binary at address <addr> to "
- "the QE,\n\twith optional length <length> verification.\n"
- );
+ "the QE,\n"
+ "\twith optional length <length> verification."
+);
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba23..faad43c2f 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@@ -25,7 +25,6 @@
#include "common.h"
-#define QE_NUM_OF_SNUM 28
#define QE_NUM_OF_BRGS 16
#define UCC_MAX_NUM 8
@@ -46,11 +45,16 @@ typedef struct qe_snum {
/* QE RISC allocation
*/
-typedef enum qe_risc_allocation {
- QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
- QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
- QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
+#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
+#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
+#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2)
+#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
+ QE_RISC_ALLOCATION_RISC2 | \
+ QE_RISC_ALLOCATION_RISC3 | \
+ QE_RISC_ALLOCATION_RISC4)
/* QE CECR commands for UCC fast.
*/
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index bba3ef2c6..3686575a0 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
*
@@ -31,146 +31,34 @@
#include "uec_phy.h"
#include "miiphy.h"
+static uec_info_t uec_info[] = {
#ifdef CONFIG_UEC_ETH1
-static uec_info_t eth1_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC1_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC1_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC1_TX_CLK,
- .eth_type = CONFIG_SYS_UEC1_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC1_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC1_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC1_INTERFACE_MODE,
-};
+ STD_UEC_INFO(1), /* UEC1 */
#endif
#ifdef CONFIG_UEC_ETH2
-static uec_info_t eth2_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC2_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC2_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC2_TX_CLK,
- .eth_type = CONFIG_SYS_UEC2_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC2_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC2_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC2_INTERFACE_MODE,
-};
+ STD_UEC_INFO(2), /* UEC2 */
#endif
#ifdef CONFIG_UEC_ETH3
-static uec_info_t eth3_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC3_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC3_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC3_TX_CLK,
- .eth_type = CONFIG_SYS_UEC3_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC3_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC3_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC3_INTERFACE_MODE,
-};
+ STD_UEC_INFO(3), /* UEC3 */
#endif
#ifdef CONFIG_UEC_ETH4
-static uec_info_t eth4_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC4_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC4_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC4_TX_CLK,
- .eth_type = CONFIG_SYS_UEC4_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC4_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC4_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC4_INTERFACE_MODE,
-};
+ STD_UEC_INFO(4), /* UEC4 */
#endif
#ifdef CONFIG_UEC_ETH5
-static uec_info_t eth5_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC5_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC5_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC5_TX_CLK,
- .eth_type = CONFIG_SYS_UEC5_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC5_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
-#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC5_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC5_INTERFACE_MODE,
-};
+ STD_UEC_INFO(5), /* UEC5 */
#endif
#ifdef CONFIG_UEC_ETH6
-static uec_info_t eth6_uec_info = {
- .uf_info = {
- .ucc_num = CONFIG_SYS_UEC6_UCC_NUM,
- .rx_clock = CONFIG_SYS_UEC6_RX_CLK,
- .tx_clock = CONFIG_SYS_UEC6_TX_CLK,
- .eth_type = CONFIG_SYS_UEC6_ETH_TYPE,
- },
-#if (CONFIG_SYS_UEC6_ETH_TYPE == FAST_ETH)
- .num_threads_tx = UEC_NUM_OF_THREADS_1,
- .num_threads_rx = UEC_NUM_OF_THREADS_1,
-#else
- .num_threads_tx = UEC_NUM_OF_THREADS_4,
- .num_threads_rx = UEC_NUM_OF_THREADS_4,
+ STD_UEC_INFO(6), /* UEC6 */
#endif
- .riscTx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .riscRx = QE_RISC_ALLOCATION_RISC1_AND_RISC2,
- .tx_bd_ring_len = 16,
- .rx_bd_ring_len = 16,
- .phy_address = CONFIG_SYS_UEC6_PHY_ADDR,
- .enet_interface = CONFIG_SYS_UEC6_INTERFACE_MODE,
-};
+#ifdef CONFIG_UEC_ETH7
+ STD_UEC_INFO(7), /* UEC7 */
#endif
+#ifdef CONFIG_UEC_ETH8
+ STD_UEC_INFO(8), /* UEC8 */
+#endif
+};
-#define MAXCONTROLLERS (6)
+#define MAXCONTROLLERS (8)
static struct eth_device *devlist[MAXCONTROLLERS];
@@ -491,6 +379,10 @@ static int uec_set_mac_if_mode(uec_private_t *uec, enet_interface_e if_mode)
maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
upsmr |= (UPSMR_R10M | UPSMR_RMM);
break;
+ case ENET_1000_SGMII:
+ maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
+ upsmr |= UPSMR_SGMM;
+ break;
default:
return -EINVAL;
break;
@@ -1020,7 +912,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
/* Init Rx global parameter pointer */
p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
- (u32)uec_info->riscRx;
+ (u32)uec_info->risc_rx;
/* Init Rx threads */
for (i = 0; i < (thread_rx + 1); i++) {
@@ -1038,13 +930,13 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
}
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- init_enet_offset | (u32)uec_info->riscRx;
+ init_enet_offset | (u32)uec_info->risc_rx;
p_init_enet_param->rxthread[i] = entry_val;
}
/* Init Tx global parameter pointer */
p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
- (u32)uec_info->riscTx;
+ (u32)uec_info->risc_tx;
/* Init Tx threads */
for (i = 0; i < thread_tx; i++) {
@@ -1057,7 +949,7 @@ static int uec_issue_init_enet_rxtx_cmd(uec_private_t *uec,
UEC_THREAD_TX_PRAM_ALIGNMENT);
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
- init_enet_offset | (u32)uec_info->riscTx;
+ init_enet_offset | (u32)uec_info->risc_tx;
p_init_enet_param->txthread[i] = entry_val;
}
@@ -1190,6 +1082,18 @@ static int uec_startup(uec_private_t *uec)
out_be32(&uec_regs->utbipar, utbipar);
+ /* Configure the TBI for SGMII operation */
+ if (uec->uec_info->enet_interface == ENET_1000_SGMII) {
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_ANA, TBIANA_SETTINGS);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_TBICON, TBICON_CLK_SELECT);
+
+ uec_write_phy_reg(uec->dev, uec_regs->utbipar,
+ ENET_TBI_MII_CR, TBICR_SETTINGS);
+ }
+
/* Allocate Tx BDs */
length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
@@ -1417,12 +1321,11 @@ static int uec_recv(struct eth_device* dev)
return 1;
}
-int uec_initialize(int index)
+int uec_initialize(bd_t *bis, uec_info_t *uec_info)
{
struct eth_device *dev;
int i;
uec_private_t *uec;
- uec_info_t *uec_info;
int err;
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
@@ -1437,42 +1340,18 @@ int uec_initialize(int index)
}
memset(uec, 0, sizeof(uec_private_t));
- /* Init UEC private struct, they come from board.h */
- uec_info = NULL;
- if (index == 0) {
-#ifdef CONFIG_UEC_ETH1
- uec_info = &eth1_uec_info;
-#endif
- } else if (index == 1) {
-#ifdef CONFIG_UEC_ETH2
- uec_info = &eth2_uec_info;
-#endif
- } else if (index == 2) {
-#ifdef CONFIG_UEC_ETH3
- uec_info = &eth3_uec_info;
-#endif
- } else if (index == 3) {
-#ifdef CONFIG_UEC_ETH4
- uec_info = &eth4_uec_info;
+ /* Adjust uec_info */
+#if (MAX_QE_RISC == 4)
+ uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
+ uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
#endif
- } else if (index == 4) {
-#ifdef CONFIG_UEC_ETH5
- uec_info = &eth5_uec_info;
-#endif
- } else if (index == 5) {
-#ifdef CONFIG_UEC_ETH6
- uec_info = &eth6_uec_info;
-#endif
- } else {
- printf("%s: index is illegal.\n", __FUNCTION__);
- return -EINVAL;
- }
- devlist[index] = dev;
+ devlist[uec_info->uf_info.ucc_num] = dev;
uec->uec_info = uec_info;
+ uec->dev = dev;
- sprintf(dev->name, "FSL UEC%d", index);
+ sprintf(dev->name, "FSL UEC%d", uec_info->uf_info.ucc_num);
dev->iobase = 0;
dev->priv = (void *)uec;
dev->init = uec_init;
@@ -1499,3 +1378,20 @@ int uec_initialize(int index)
return 1;
}
+
+int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num)
+{
+ int i;
+
+ for (i = 0; i < num; i++)
+ uec_initialize(bis, &uecs[i]);
+
+ return 0;
+}
+
+int uec_standard_init(bd_t *bis)
+{
+ return uec_eth_init(bis, uec_info, ARRAY_SIZE(uec_info));
+}
+
+
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 0b644996b..156831009 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
@@ -47,6 +47,7 @@
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
#define UPSMR_BRO 0x00000200 /* Broadcast Address */
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
+#define UPSMR_SGMM 0x00000020 /* SGMII mode */
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
@@ -621,6 +622,31 @@ typedef enum enet_tbi_mii_reg {
ENET_TBI_MII_TBICON = 0x11
} enet_tbi_mii_reg_e;
+/* TBI MDIO register bit fields*/
+#define TBICON_CLK_SELECT 0x0020
+#define TBIANA_ASYMMETRIC_PAUSE 0x0100
+#define TBIANA_SYMMETRIC_PAUSE 0x0080
+#define TBIANA_HALF_DUPLEX 0x0040
+#define TBIANA_FULL_DUPLEX 0x0020
+#define TBICR_PHY_RESET 0x8000
+#define TBICR_ANEG_ENABLE 0x1000
+#define TBICR_RESTART_ANEG 0x0200
+#define TBICR_FULL_DUPLEX 0x0100
+#define TBICR_SPEED1_SET 0x0040
+
+#define TBIANA_SETTINGS ( \
+ TBIANA_ASYMMETRIC_PAUSE \
+ | TBIANA_SYMMETRIC_PAUSE \
+ | TBIANA_FULL_DUPLEX \
+ )
+
+#define TBICR_SETTINGS ( \
+ TBICR_PHY_RESET \
+ | TBICR_ANEG_ENABLE \
+ | TBICR_FULL_DUPLEX \
+ | TBICR_SPEED1_SET \
+ )
+
/* UEC number of threads
*/
typedef enum uec_num_of_threads {
@@ -645,17 +671,36 @@ typedef enum enet_interface {
ENET_1000_RGMII_ID,
ENET_1000_RGMII_RXID,
ENET_1000_TBI,
- ENET_1000_RTBI
+ ENET_1000_RTBI,
+ ENET_1000_SGMII
} enet_interface_e;
/* UEC initialization info struct
*/
+#define STD_UEC_INFO(num) \
+{ \
+ .uf_info = { \
+ .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\
+ .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \
+ .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \
+ .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\
+ }, \
+ .num_threads_tx = UEC_NUM_OF_THREADS_1, \
+ .num_threads_rx = UEC_NUM_OF_THREADS_1, \
+ .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
+ .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
+ .tx_bd_ring_len = 16, \
+ .rx_bd_ring_len = 16, \
+ .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \
+ .enet_interface = CONFIG_SYS_UEC##num##_INTERFACE_MODE, \
+}
+
typedef struct uec_info {
ucc_fast_info_t uf_info;
uec_num_of_threads_e num_threads_tx;
uec_num_of_threads_e num_threads_rx;
- qe_risc_allocation_e riscTx;
- qe_risc_allocation_e riscRx;
+ unsigned int risc_tx;
+ unsigned int risc_rx;
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;
@@ -716,4 +761,7 @@ typedef struct uec_private {
int oldlink;
} uec_private_t;
+int uec_initialize(bd_t *bis, uec_info_t *uec_info);
+int uec_eth_init(bd_t *bis, uec_info_t *uecs, int num);
+int uec_standard_init(bd_t *bis);
#endif /* __UEC_H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 16:19:42 +0000