diff options
Diffstat (limited to 'include/configs')
135 files changed, 2600 insertions, 296 deletions
diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 9f1926957..73e34bdab 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -71,6 +71,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/B2.h b/include/configs/B2.h index 35fad5c55..e5439f3b5 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -39,6 +39,7 @@ #define CONFIG_ARM_THUMB 1 /* this is an ARM7TDMI */ #undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #define CONFIG_SYS_NO_CP15_CACHE +#define CONFIG_ARCH_CPU_INIT #define CONFIG_S3C44B0_CLOCK_SPEED 75 /* we have a 75Mhz S3C44B0*/ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 9934f29b7..8c5a74229 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -347,6 +347,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM5200-0" #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ "1408k(kernel)," \ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 40fef88f9..ae8494d57 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -80,8 +80,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ #define CONFIG_CMD_ELF #define CONFIG_CMD_NAND #define CONFIG_CMD_I2C @@ -167,31 +165,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -222,21 +195,16 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CONFIG_SYS_RAMBOOT 1 @@ -291,8 +259,7 @@ /*----------------------------------------------------------------------- * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ @@ -356,17 +323,7 @@ * Default speed selection (cpu_plb_opb_ebc) in mhz. * This value will be set if iic boot eprom is disabled. */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8494faac2..d516c3cb8 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -76,7 +76,8 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_AUTO_COMPLETE 1 +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Define which ETH port will be used for connecting the network */ #define CONFIG_SYS_ETH_PORT ETH_0 @@ -626,4 +627,6 @@ #define CONFIG_SYS_BOARD_ASM_INIT 1 +#define CPCI750_SLAVE_TEST (((in8(0xf0300000) & 0x80) == 0) ? 0 : 1) + #endif /* __CONFIG_H */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 326371253..b2679e587 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -54,6 +54,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 150bd29e0..96bf161aa 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -45,6 +45,7 @@ #define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */ #define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ +#define CONFIG_NET_MULTI /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 187547d2a..49ecb6f36 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -52,39 +52,20 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_PPC4xx_EMAC -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - /* * Command line configuration. */ #include <config_cmd_default.h> #define CONFIG_CMD_BSP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IRQ #define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE #define CONFIG_CMD_I2C #define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_NET #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ - #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ #define CONFIG_PRAM 2 /* reserve 2 kB "protected RAM" */ @@ -134,33 +115,6 @@ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ - -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -191,21 +145,16 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CONFIG_SYS_RAMBOOT 1 @@ -221,9 +170,6 @@ #define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ - /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ @@ -245,18 +191,11 @@ */ #define CAN_BA 0xF0000000 /* CAN Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x92015480 #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ -#if 0 /* test-only */ -/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */ -#endif - /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */ #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ @@ -264,9 +203,6 @@ /*----------------------------------------------------------------------- * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ - /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ @@ -312,7 +248,7 @@ #define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ #define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ +#define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ /* * Internal Definitions @@ -326,17 +262,7 @@ * Default speed selection (cpu_plb_opb_ebc) in mhz. * This value will be set if iic boot eprom is disabled. */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index d1edd244b..cfb302331 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -211,7 +211,6 @@ /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC08) for environment */ -#define CONFIG_I2C_CMD_TREE 1 #define CONFIG_HARD_I2C /* I2c with hardware support */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/DU440.h b/include/configs/DU440.h index e6abbdc5f..e9ea1bf7d 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -170,7 +170,6 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_I2C_CMD_TREE 1 #define CONFIG_I2C_MULTI_BUS 1 #define CONFIG_SYS_SPD_BUS_NUM 0 diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 201e62aa0..023f33e1e 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -96,6 +96,7 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index 4729464f2..4d0824339 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -81,6 +81,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index f152230da..aceecd86d 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -217,6 +217,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index 5eaed842b..4a61d7c75 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -217,6 +217,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 0e7d2c010..ea502d42c 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -60,6 +60,7 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 8aca1f941..80c70e488 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -135,6 +135,7 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index a3869c874..8315cfe62 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -341,6 +341,7 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ #define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ +#define CONFIG_NET_MULTI /************************************************************ * RTC ***********************************************************/ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 21aedee87..230856869 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -30,8 +30,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83XX 1 -#define CONFIG_MPC831X 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_MPC8313ERDB 1 @@ -321,7 +321,6 @@ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 9fa91f4f6..e03a1077f 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * @@ -29,8 +29,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83XX 1 /* MPC83xx family */ -#define CONFIG_MPC831X 1 /* MPC831x CPU family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC831x 1 /* MPC831x CPU family */ #define CONFIG_MPC8315 1 /* MPC8315 CPU specific */ #define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */ @@ -345,6 +345,14 @@ #endif #define CONFIG_HAS_FSL_DR_USB +#define CONFIG_SYS_SCCR_USBDRCM 3 + +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_PHY_TYPE "utmi" +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* * TSEC @@ -569,6 +577,7 @@ "ramdiskfile=ramfs.83xx\0" \ "fdtaddr=400000\0" \ "fdtfile=mpc8315erdb.dtb\0" \ + "usb_phy_type=utmi\0" \ "" #define CONFIG_NFSBOOTCOMMAND \ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 9b8b0333e..24f37e7cb 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -14,8 +14,8 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83xx family */ -#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_PCI 1 #define CONFIG_83XX_GENERIC_PCI 1 diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index c82cda2dd..669577ef1 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -25,8 +25,8 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83xx family */ -#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC832x 1 /* MPC832x CPU specific */ #define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ #undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 2d2799e11..ea5fbff30 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -33,8 +33,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ @@ -315,7 +315,6 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index ab6fe55c4..f2e574b73 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -63,7 +63,7 @@ /* * High Level Configuration Options */ -#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ +#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ #define CONFIG_MPC8349 /* MPC8349 specific */ #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ @@ -95,7 +95,6 @@ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 4b09de17f..3497ba07e 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -27,7 +27,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 477a1c582..f5844356d 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -22,7 +22,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ @@ -265,7 +265,6 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0x52}} /* Don't probe these addrs */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a62d805a9..4befcab41 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -25,8 +25,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 8d0c93b71..2b7d62954 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -26,8 +26,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC837X 1 /* MPC837X CPU specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ #define CONFIG_MPC837XERDB 1 #define CONFIG_PCI 1 diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index bbb448d55..9e00b8986 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -337,7 +337,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ @@ -463,6 +462,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -628,7 +636,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); "ramdiskfile=8536ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ "fdtfile=8536ds/mpc8536ds.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "usb_phy_type=ulpi\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 77224d98e..ac3404737 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -287,7 +287,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 0ee40c618..27044f7bb 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -239,7 +239,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ @@ -283,6 +282,8 @@ extern unsigned long get_clock_freq(void); /* * QE UEC ethernet configuration */ +#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ +#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) #define CONFIG_UEC_ETH @@ -295,11 +296,18 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH1 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH1 */ #define CONFIG_UEC_ETH2 /* GETH2 */ #define CONFIG_HAS_ETH1 @@ -307,11 +315,80 @@ extern unsigned long get_clock_freq(void); #ifdef CONFIG_UEC_ETH2 #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID -#endif +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ +#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH2 */ + +#define CONFIG_UEC_ETH3 /* GETH3 */ +#define CONFIG_HAS_ETH2 + +#ifdef CONFIG_UEC_ETH3 +#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ +#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) +#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 +#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC3_PHY_ADDR 2 +#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ +#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ +#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH3 */ + +#define CONFIG_UEC_ETH4 /* GETH4 */ +#define CONFIG_HAS_ETH3 + +#ifdef CONFIG_UEC_ETH4 +#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE +#if defined(CONFIG_SYS_UCC_RGMII_MODE) +#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC4_PHY_ADDR 3 +#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID +#elif defined(CONFIG_SYS_UCC_RMII_MODE) +#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ +#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ +#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII +#endif /* CONFIG_SYS_UCC_RGMII_MODE */ +#endif /* CONFIG_UEC_ETH4 */ + +#undef CONFIG_UEC_ETH6 /* GETH6 */ +#define CONFIG_HAS_ETH5 + +#ifdef CONFIG_UEC_ETH6 +#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ +#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC6_PHY_ADDR 4 +#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH6 */ + +#undef CONFIG_UEC_ETH8 /* GETH8 */ +#define CONFIG_HAS_ETH7 + +#ifdef CONFIG_UEC_ETH8 +#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ +#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE +#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH +#define CONFIG_SYS_UEC8_PHY_ADDR 6 +#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII +#endif /* CONFIG_UEC_ETH8 */ #endif /* CONFIG_QE */ diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index b60b3641f..2aba68966 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -378,7 +378,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 #define CONFIG_SYS_I2C_SLAVE 0x7F diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 8f741f58b..967520587 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -33,8 +33,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83XX 1 -#define CONFIG_MPC834X 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC834x 1 #define CONFIG_MPC8343 1 #define CONFIG_SYS_IMMR 0xE0000000 @@ -53,7 +53,6 @@ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 2591f1ded..860ec5292 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -54,6 +54,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 13d6e0496..b2e2d41f2 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -54,6 +54,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_NET_MULTI /* diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h new file mode 100644 index 000000000..a39ff26a7 --- /dev/null +++ b/include/configs/P2020DS.h @@ -0,0 +1,741 @@ +/* + * Copyright 2007-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * p2020ds board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_P2020 1 +#define CONFIG_P2020DS 1 +#define CONFIG_MP 1 /* support multiple processors */ +#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ + +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ +#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_ENV_OVERWRITE + +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash associated with the CDS board. + * This allows booting from a promjet. + */ +#define CONFIG_ASSUME_AMD_FLASH + +#ifndef __ASSEMBLY__ +extern unsigned long calculate_board_sys_clk(unsigned long dummy); +extern unsigned long calculate_board_ddr_clk(unsigned long dummy); +/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ +/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ +#endif +#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ +#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq + from ICS307 instead of switches */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS 1 + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) + +/* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 +#define CONFIG_VERY_BIG_RAM +#define CONFIG_FSL_DDR3 1 +#undef CONFIG_FSL_DDR_INTERACTIVE + +// #define CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 + +/* I2C addresses of SPD EEPROMs */ +#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ +#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ + +/* These are used when DDR doesn't use SPD. */ +//#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ +#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ + +/* Default settings for "stable" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0 0x00330804 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6b4846 +#define CONFIG_SYS_DDR_TIMING_2 0x0fa890d4 +#define CONFIG_SYS_DDR_MODE_1 0x00421422 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_MODE_CTRL 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x61800100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400 +#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 +#define CONFIG_SYS_DDR_WRLVL_CNTL 0x8655A608 +#define CONFIG_SYS_DDR_CONTROL 0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */ +#define CONFIG_SYS_DDR_CONTROL2 0x24400011 +#define CONFIG_SYS_DDR_CDR1 0x00040000 +#define CONFIG_SYS_DDR_CDR2 0x00000000 + +#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d +#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 +#define CONFIG_SYS_DDR_SBE 0x00010000 + +/* Settings that differ for "performance" mode */ +#define CONFIG_SYS_DDR_CS0_BNDS_PERF 0x0000007F /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_BNDS_PERF 0x00000000 /* Interleaving Enabled */ +#define CONFIG_SYS_DDR_CS1_CONFIG_PERF 0x80014202 +#define CONFIG_SYS_DDR_TIMING_1_PERF 0x5d5b4543 +#define CONFIG_SYS_DDR_TIMING_2_PERF 0x0fa890ce +#define CONFIG_SYS_DDR_CONTROL_PERF 0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */ + +/* + * The following set of values were tested for DDR2 + * with a DDR3 to DDR2 interposer + * +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 +#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 +#define CONFIG_SYS_DDR_MODE_1 0x00480432 +#define CONFIG_SYS_DDR_MODE_2 0x00000000 +#define CONFIG_SYS_DDR_INTERVAL 0x06180100 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 +#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 +#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 +#define CONFIG_SYS_DDR_CONTROL2 0x04400010 + * + */ + +#undef CONFIG_CLOCKS_IN_MHZ + +/* + * Memory map + * + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable + * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable + * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable + * + * Localbus cacheable (TBD) + * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable + * + * Localbus non-cacheable + * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable + * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable + * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable + * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable + */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ + +#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_ID 0x0 /* Board ID at offset 0 */ +#define PIXIS_VER 0x1 /* Board version at offset 1 */ +#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ +#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ +#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ +#define PIXIS_PWR 0x5 /* PIXIS Power status register */ +#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ +#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ +#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ +#define PIXIS_VCTL 0x10 /* VELA Control Register */ +#define PIXIS_VSTAT 0x11 /* VELA Status Register */ +#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ +#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ +#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ +#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ +#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ +#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ +#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ +#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ +#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ +#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ +#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ +#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ + +#define PIXIS_VWATCH 0x24 /* Watchdog Register */ +#define PIXIS_LED 0x25 /* LED Register */ + +/* old pixis referenced names */ +#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ +#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ +#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 +#define PIXIS_VSPEED2_TSEC1SER 0x8 +#define PIXIS_VSPEED2_TSEC2SER 0x4 +#define PIXIS_VSPEED2_TSEC3SER 0x2 +#define PIXIS_VSPEED2_TSEC4SER 0x1 +#define PIXIS_VCFGEN1_TSEC1SER 0x20 +#define PIXIS_VCFGEN1_TSEC2SER 0x20 +#define PIXIS_VCFGEN1_TSEC3SER 0x20 +#define PIXIS_VCFGEN1_TSEC4SER 0x20 +#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ + | PIXIS_VSPEED2_TSEC2SER \ + | PIXIS_VSPEED2_TSEC3SER \ + | PIXIS_VSPEED2_TSEC4SER) +#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ + | PIXIS_VCFGEN1_TSEC2SER \ + | PIXIS_VCFGEN1_TSEC3SER \ + | PIXIS_VCFGEN1_TSEC4SER) + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ + CONFIG_SYS_NAND_BASE + 0x40000, \ + CONFIG_SYS_NAND_BASE + 0x80000,\ + CONFIG_SYS_NAND_BASE + 0xC0000} +#define CONFIG_SYS_MAX_NAND_DEVICE 4 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* new uImage format support */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * I2C2 EEPROM + */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +#if defined(CONFIG_PCI) + +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP +#define CONFIG_RTL8139 + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#define _IO_BASE 0x00000000 +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SCSI_AHCI + +#ifdef CONFIG_SCSI_AHCI +#define CONFIG_SATA_ULI5288 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 +#define CONFIG_SYS_SCSI_MAX_LUN 1 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE +#endif /* SCSI */ + +#endif /* CONFIG_PCI */ + + +#if defined(CONFIG_TSEC_ENET) + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define CONFIG_PIXIS_SGMII_CMD +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ +#endif + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_NET +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_EXT2 +#endif + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +/* The mac addresses for all ethernet interface */ +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:02:00:FD +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD +#define CONFIG_HAS_ETH2 +#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD +#define CONFIG_HAS_ETH3 +#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD +#endif + +#define CONFIG_IPADDR 192.168.1.254 + +#define CONFIG_HOSTNAME unknown +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "perf_mode=stable\0" \ + "memctl_intlv_ctl=2\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2020ds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2020ds/p2020ds.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#endif /* __CONFIG_H */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 5c4d69b20..e214d70a5 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -281,6 +281,7 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_NET_MULTI /************************************************************ * RTC ***********************************************************/ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index c598d00cf..a9e71346e 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -282,9 +282,6 @@ /* * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */ - /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index fc48bc1db..012ae798d 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -230,7 +230,6 @@ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_I2C_CMD_TREE 1 #define CONFIG_I2C_MULTI_BUS 1 #define CONFIG_SYS_I2C_MULTI_EEPROMS diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 79582e16c..72fe11588 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -32,8 +32,8 @@ #define CONFIG_NAND_U_BOOT #define CONFIG_E300 1 -#define CONFIG_MPC83XX 1 -#define CONFIG_MPC831X 1 +#define CONFIG_MPC83xx 1 +#define CONFIG_MPC831x 1 #define CONFIG_MPC8313 1 #define CONFIG_PCI @@ -190,6 +190,7 @@ /* mtdparts command line support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand0" #define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" @@ -223,7 +224,6 @@ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index 05f6d9fc1..adb6ac52e 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -30,8 +30,6 @@ * If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_INIT_CRITICAL /* undef for developing */ - #undef CONFIG_SKIP_LOWLEVEL_INIT #undef CONFIG_SKIP_RELOCATE_UBOOT diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 92b4fa503..3438abaea 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -276,6 +276,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM5200-0" #if defined(CONFIG_TQM5200_B) #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index fe1d10290..a4336a750 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -408,6 +408,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM5200-0" #ifdef CONFIG_STK52XX diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 87e5a650d..1f816f35a 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -232,6 +232,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index f6664437d..42dcbfc2a 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -228,6 +228,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 551073025..efade69ca 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -32,8 +32,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X specific */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC834x 1 /* MPC834x specific */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ @@ -78,13 +78,12 @@ * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ - -/* buffered writes in the AMD chip set is not supported yet */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* * FLASH bank number detection @@ -146,9 +145,9 @@ extern int tqm834x_num_flash_banks; #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT +# define CONFIG_SYS_RAMBOOT #else -#undef CONFIG_SYS_RAMBOOT +# undef CONFIG_SYS_RAMBOOT #endif #define CONFIG_SYS_INIT_RAM_LOCK 1 @@ -159,8 +158,8 @@ extern int tqm834x_num_flash_banks; #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ /* * Serial Port @@ -275,22 +274,15 @@ extern int tqm834x_num_flash_banks; /* * Environment */ -#define CONFIG_ENV_OVERWRITE - -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ - #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* * BOOTP options @@ -306,14 +298,18 @@ extern int tqm834x_num_flash_banks; */ #include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP #define CONFIG_CMD_DTT #define CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -350,6 +346,11 @@ extern int tqm834x_num_flash_banks; #undef CONFIG_WATCHDOG /* watchdog disabled */ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -494,20 +495,35 @@ extern int tqm834x_num_flash_banks; "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ + "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs_old=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self_old=run ramargs addip addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs_old=tftp 400000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addcons; " \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/tqm834x/uImage\0" \ - "kernel_addr=80060000\0" \ - "ramdisk_addr=80160000\0" \ - "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \ - "update=protect off 80000000 8003ffff; " \ - "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ + "bootfile=tqm834x/uImage\0" \ + "fdtfile=tqm834x/tqm834x.dtb\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=600000\0" \ + "ramdisk_addr_r=800000\0" \ + "kernel_addr=800C0000\0" \ + "fdt_addr=800A0000\0" \ + "ramdisk_addr=80300000\0" \ + "u-boot=tqm834x/u-boot.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 80000000 +${filesize};" \ + "era 80000000 +${filesize};" \ + "cp.b 200000 80000000 ${filesize}\0" \ "upd=run load update\0" \ "" @@ -518,6 +534,8 @@ extern int tqm834x_num_flash_banks; */ /* mtdparts command line support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM834x-0" /* default mtd partition table */ diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index dc80b4746..290e211ad 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -217,6 +217,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 22894432c..2170df5dc 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -217,6 +217,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 999bdaadc..3d7dc4233 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -222,6 +222,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index b54967dae..35cfa0882 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -257,6 +257,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 08465010e..6f13c63f5 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -567,6 +567,8 @@ #define CONFIG_JFFS2_NAND 1 #ifdef CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nand0=TQM85xx-nand" #define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" #else diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 2e2a165b8..4ac485d32 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -221,6 +221,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 1148f2e4e..39da0bbd6 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -222,6 +222,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 577f982c5..1f79b170d 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -225,6 +225,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 69070e645..86d5b0163 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -226,6 +226,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index bb6861470..04f538ce5 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -266,6 +266,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxM-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \ diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index db00c652f..4717869dd 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -177,10 +177,10 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CONFIG_SYS_RAMBOOT 1 @@ -231,8 +231,7 @@ /* * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ @@ -293,17 +292,7 @@ * Default speed selection (cpu_plb_opb_ebc) in mhz. * This value will be set if iic boot eprom is disabled. */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif #endif /* __CONFIG_H */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index ceef76eea..553845d6d 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -68,6 +68,7 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 11e063010..73d6d24b6 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -68,6 +68,7 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 99188bc34..5c281a1a6 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -58,6 +58,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_NET_MULTI #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index 370aae1c4..89ab69272 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -226,7 +226,6 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE /* I2C EEPROM */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index a353a14e7..536e06338 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -244,7 +244,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C2_OFFSET 0x3100 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE /* PEX8518 slave I2C interface */ #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index d3dc3e533..3b733c03e 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -76,6 +76,17 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO +#if defined(CONFIG_SYS_RAMBOOT) +/* + * Disable NOR FLASH commands on RAM-booting version. One main reason for this + * RAM-booting version is boards with NAND and without NOR. This image can + * be used for initial NAND programming. + */ +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/apollon.h b/include/configs/apollon.h index 925079d0c..fa5a7a9e2 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -124,6 +124,7 @@ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBI #define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS #endif diff --git a/include/configs/aria.h b/include/configs/aria.h new file mode 100644 index 000000000..58f67a4f0 --- /dev/null +++ b/include/configs/aria.h @@ -0,0 +1,554 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009, DAVE Srl <www.dave.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Aria board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARIA 1 +/* + * Memory map for the ARIA board: + * + * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) + * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 + * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 + * 0x8000_0000-0x803F_FFFF IMMR (4 MB) + * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) + * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) + * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) + * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ +#define CONFIG_FSL_DIU_LOGO_BMP 1 /* Don't include FSL DIU binary bmp */ + +/* video */ +#undef CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#endif + +/* CONFIG_PCI is defined at config time */ + +#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* DDR Controller Configuration + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ +#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 +/*#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 */ + #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 +/*#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 */ + #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 + +#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E +/*#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E */ +#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E + +#define CONFIG_SYS_MICRON_NOP 0x01380000 +#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EM2 0x01020000 +#define CONFIG_SYS_MICRON_EM3 0x01030000 +#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 +#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 +#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the CFI code */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ + +#undef CONFIG_SYS_FLASH_CHECKSUM + +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ + +#define CONFIG_SYS_ARIA_SRAM_BASE 0x30020000 +#define CONFIG_SYS_ARIA_SRAM_SIZE 0x20000 /* 128 KB */ + +#define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ + CONFIG_SYS_ARIA_SRAM_SIZE) +#define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ + +#define CONFIG_SYS_CS0_CFG 0x05059150 +#define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ + (5 << 16) | \ + (1 << 15) | \ + (0 << 14) | \ + (0 << 13) | \ + (1 << 12) | \ + (0 << 10) | \ + (3 << 8) | /* 32 bit */ \ + (0 << 7) | \ + (1 << 6) | \ + (1 << 4) | \ + (0 << 3) | \ + (0 << 2) | \ + (0 << 1) | \ + (0 << 0) \ + ) +#define CONFIG_SYS_CS6_CFG 0x05059150 + +/* Use alternative CS timing for CS0 and CS2 */ +#define CONFIG_SYS_CS_ALETIMING 0x00000005 + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) + +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) +#else +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) +#endif + +/* FPGA */ +#define CONFIG_ARIA_FPGA 1 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif + +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* command line history */ +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * PCI + */ +#ifdef CONFIG_PCI + +#define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE +#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ + CONFIG_SYS_PCI_MEM_SIZE) +#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE +#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI_IO_PHYS 0x84000000 +#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#if 0 +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#endif + +/* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + +/* + * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: + * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x17 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the flash sector size */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_CMD_IDE) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + +/* + * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE + * is set to 0xFFFF, watchdog timeouts after about 64s. For details + * refer to chapter 36 of the MPC5121e Reference Manual. + */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ICE) +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME aria +#define CONFIG_BOOTFILE aria/uImage +#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx + +#define CONFIG_LOADADDR 400000 /* default load addr */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=600000\0" \ + "fdt_addr_r=880000\0" \ + "ramdisk_addr_r=900000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FFC40000\0" \ + "fdt_addr=FFEC0000\0" \ + "ramdisk_addr=FC040000\0" \ + "ramdiskfile=aria/uRamdisk\0" \ + "u-boot=aria/u-boot.bin\0" \ + "fdtfile=aria/aria.dtb\0" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for IDE not supported */ + +#define CONFIG_IDE_RESET /* reset for IDE supported */ +#define CONFIG_IDE_PREINIT + +#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() + +/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define ATA_BASE_ADDR get_pata_base() + +/* + * Control register bit definitions + */ +#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 +#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 +#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 +#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 +#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 +#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 +#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 +#define FSL_ATA_CTRL_IORDY_EN 0x01000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 7ba5e174e..f7eec2768 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -34,7 +34,7 @@ * If we are developing, we might want to start armboot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -/*#define CONFIG_INIT_CRITICAL*/ /* undef for developing */ +#undef CONFIG_SKIP_LOWLEVEL_INIT /* * High Level Configuration Options diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index b2e6d7d02..526cd60ae 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -28,7 +28,6 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91CAP9" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index a018873fd..c898c7304 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -266,7 +266,6 @@ #ifdef CONFIG_HARD_I2C #define CONFIG_CMD_I2C -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 0 /* not used */ #define CONFIG_SYS_I2C_SLAVE 0 /* not used */ #endif diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index e46c9d6ae..1828c63af 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -34,10 +34,8 @@ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #ifdef CONFIG_AT91SAM9G20EK -#define AT91_CPU_NAME "AT91SAM9G20" #define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/ #else -#define AT91_CPU_NAME "AT91SAM9260" #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 9621b7cb3..4f6b64011 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -28,7 +28,6 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9261" #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d03ecee3f..c212d11d0 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -28,7 +28,6 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9263" #define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 846d1658e..c4668236c 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -28,7 +28,6 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9RL" #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ #define CONFIG_SYS_HZ 1000 diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index bfe53762c..e0be07b47 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -91,7 +91,7 @@ */ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_DEBUG_DUMP 1 -#define CONFIG_DEBUG_DUMP_SYMS 1 +#define CONFIG_KALLSYMS 1 #define CONFIG_PANIC_HANG 1 /* diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index dcf5b6de0..627060a75 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -134,7 +134,7 @@ */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #if defined(CONFIG_CMD_EEPROM) diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 82d140146..b924758dc 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -60,6 +60,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on CERF PXA */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 54cf40d67..72cf941ab 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -223,6 +223,8 @@ * MTD configuration */ #define CONFIG_CMD_MTDPARTS 1 +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=cm5200-0" #define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ "384k(uboot),128k(env)," \ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 75c5f9bb3..b150c221a 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -57,6 +57,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index ed1845009..12bab4702 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -53,6 +53,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 204aea0e8..aed6f50f9 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -184,6 +184,7 @@ #define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ +#define CONFIG_NET_MULTI /* * RTC configuration diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 9b3a11c1a..24b961f3e 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -183,6 +183,7 @@ #define CONFIG_PHY_CMD_DELAY 40 /* PHY COMMAND delay */ /* 32usec min. for LXT971A */ #define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */ +#define CONFIG_NET_MULTI /* * RTC configuration diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h new file mode 100644 index 000000000..9a7df083f --- /dev/null +++ b/include/configs/davinci_dm355evm.h @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2009 David Brownell + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* Spectrum Digital TMS320DM355 EVM board */ +#define DAVINCI_DM355EVM + +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_DISPLAY_CPUINFO + +/* SoC Configuration */ +#define CONFIG_ARM926EJS /* arm926ejs CPU */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM355 + +/* Memory Info */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE SZ_128M + +/* Serial Driver info: UART0 for console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Ethernet: external DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x04014000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 2) + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ + +/* NAND: socketed, two chipselects, normally 2 GBytes */ +/* NYET -- #define CONFIG_NAND_DAVINCI */ +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } +/* socket has two chipselects, nCE0 gated by address BIT(14) */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 2 + +/* USB: OTG connector */ +/* NYET -- #define CONFIG_USB_DAVINCI */ + +/* U-Boot command configuration */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES + +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#endif + +/* TEMPORARY -- no safe place to save env, yet */ +#define CONFIG_ENV_IS_NOWHERE +#undef CONFIG_CMD_SAVEENV + +#ifdef CONFIG_USB_DAVINCI +#define CONFIG_MUSB_HCD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#else +#undef CONFIG_MUSB_HCD +#undef CONFIG_CMD_USB +#undef CONFIG_USB_STORAGE +#endif + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* U-Boot general configuration */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM355 EVM # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP + +#define CONFIG_ENV_SIZE SZ_16K + +/* NYET -- #define CONFIG_BOOTDELAY 5 */ +#define CONFIG_BOOTCOMMAND \ + "dhcp;bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200n8 " \ + "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +#define CONFIG_NET_RETRY_COUNT 10 + +/* U-Boot memory configuration */ +#define CONFIG_STACKSIZE SZ_256K /* regular stack */ +#define CONFIG_SYS_MALLOC_LEN SZ_512K /* malloc() arena */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ +#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ +#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ + + +/* NAND configuration ... socketed with two chipselects. It normally comes + * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other + * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC. (MLC + * pretty much demands the 4-bit ECC support.) You can of course swap in + * other parts, including small page ones. + * + * This presents a single read-only partition for all bootloader stuff. + * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and + * some extra space to help cope with bad blocks in that data. Linux + * shouldn't care about its detailed layout, and will probably want to use + * UBI/UBFS for the rest (except maybe on smallpage chips). It's easy to + * override this default partitioning using MTDPARTS and cmdlinepart. + */ +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" + +#ifdef CONFIG_SYS_NAND_LARGEPAGE +/* Use same layout for 128K/256K blocks; allow some bad blocks */ +#define PART_BOOT "2m(bootloader)ro," +#else +/* Assume 16K erase blocks; allow a few bad ones. */ +#define PART_BOOT "512k(bootloader)ro," +#endif + +#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ +#define PART_REST "-(filesystem)" + +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST + +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 9fe4072b4..6c5d06508 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -52,6 +52,7 @@ #define DV_EVM #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ @@ -59,6 +60,7 @@ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM644X /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ @@ -118,6 +120,12 @@ #ifdef CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_ENV_SECT_SIZE 512 /* Env sector Size */ #define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT \ + "nand0=davinci_nand.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)" #else #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE SZ_128K @@ -125,6 +133,7 @@ #define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ #define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ #define CONFIG_SYS_NAND_BASE 0x02000000 +#define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index a16ac391b..6612cb3cb 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -27,6 +27,7 @@ #define SCHMOOGIE #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ @@ -34,6 +35,7 @@ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM644X /*=============*/ /* Memory Info */ /*=============*/ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index c2ebd97db..6c1dc117d 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -28,13 +28,14 @@ #define SFFSDR #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_USE_NAND -#define CONFIG_SYS_USE_DSPLINK /* This is to prevent U-Boot from - * powering ON the DSP. */ +#define CONFIG_SYS_USE_DSPLINK /* don't power up the DSP. */ +#define CONFIG_DISPLAY_CPUINFO /* SoC Configuration */ #define CONFIG_ARM926EJS /* arm926ejs CPU core */ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM644X /* EEPROM definitions for Atmel 24LC64 EEPROM chip */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 0fc6012ba..893729c6f 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -52,6 +52,7 @@ #define SONATA_BOARD #define CONFIG_SYS_NAND_SMALLPAGE #define CONFIG_SYS_USE_NOR +#define CONFIG_DISPLAY_CPUINFO /*===================*/ /* SoC Configuration */ /*===================*/ @@ -59,6 +60,7 @@ #define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ #define CONFIG_SYS_HZ_CLOCK 27000000 /* Timer Input clock freq */ #define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM644X /*====================================================*/ /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */ /* on Sonata/DV_EVM board. No EEPROM on schmoogie. */ diff --git a/include/configs/delta.h b/include/configs/delta.h index bacbd90b5..e7186e839 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -82,6 +82,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h index 27c6e7d4a..e825c2150 100644 --- a/include/configs/fx12mm.h +++ b/include/configs/fx12mm.h @@ -38,6 +38,8 @@ /* cmd config */ #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #undef CONFIG_CMD_NET /* sdram */ diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index b2fbca2f3..85db4f5c7 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -36,7 +36,7 @@ * e.g. bootp/tftp download of the kernel is a far more convenient * when testing new kernels on this target. However the ADS GCPlus Linux * boot ROM leaves the MMU enabled when it passes control to U-Boot. So - * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem. + * we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem. */ #undef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT 1 diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 944d06fbf..841affb7c 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -230,6 +230,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=idmr-0" #define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 69654c7c0..ed03ad32a 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -50,6 +50,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 38c024953..09270ff0a 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -44,7 +44,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ -#undef CONFIG_INIT_CRITICAL +#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CM_INIT 1 #define CONFIG_CM_REMAP 1 #undef CONFIG_CM_SPD_DETECT diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 75707e597..0c092347c 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -55,6 +55,7 @@ */ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ +#define CONFIG_TIMER_IRQ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 0d89594f2..384026731 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -129,7 +129,6 @@ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ #define IIC0_BOOTPROM_ADDR 0x50 diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index b2e37ec22..0fcf692d1 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -97,7 +97,6 @@ #define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ #define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_CMD_TREE 1 #define CONFIG_SYS_MAX_I2C_BUS 2 #define CONFIG_SYS_I2C_INIT_BOARD 1 #define CONFIG_I2C_MUX 1 diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f7fc6c5bf..19da1337e 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -25,7 +25,7 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_KMETER1 1 /* KMETER1 board specific */ #define CONFIG_HOSTNAME kmeter1 @@ -314,7 +314,6 @@ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_I2C_MULTI_BUS 1 -#define CONFIG_I2C_CMD_TREE 1 #define CONFIG_SYS_MAX_I2C_BUS 2 #define CONFIG_I2C_MUX 1 diff --git a/include/configs/korat.h b/include/configs/korat.h index eb2c1d43b..ea6ba8938 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -282,7 +282,6 @@ #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C -#define CONFIG_I2C_CMD_TREE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MII #define CONFIG_CMD_NET diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 889a9a344..5b903f0dc 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -50,6 +50,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 151503879..7ce8d6de1 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -30,8 +30,6 @@ * If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ -#undef CONFIG_INIT_CRITICAL /* undef for developing */ - #undef CONFIG_SKIP_LOWLEVEL_INIT #undef CONFIG_SKIP_RELOCATE_UBOOT diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h index b1bd74fc6..bf4a57d24 100644 --- a/include/configs/lpd7a400.h +++ b/include/configs/lpd7a400.h @@ -43,6 +43,7 @@ /* * select serial console configuration */ +#define CONFIG_LH7A40X_SERIAL #define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h index b197674d4..102c0af3b 100644 --- a/include/configs/lpd7a404.h +++ b/include/configs/lpd7a404.h @@ -43,6 +43,7 @@ /* * select serial console configuration */ +#define CONFIG_LH7A40X_SERIAL #define CONFIG_CONSOLE_UART2 /* UART2 LH7A40x for console */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 2cf9c0281..43913cada 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -64,6 +64,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h new file mode 100644 index 000000000..083184316 --- /dev/null +++ b/include/configs/mecp5123.h @@ -0,0 +1,458 @@ +/* + * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> + * (C) Copyright 2009, DAVE Srl <www.dave.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com + * + */ + +/* + * MECP5123 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MECP5123 1 +/* + * Memory map for the MECP5123 board: + * + * 0x0000_0000 - 0x1FFF_FFFF DDR RAM (512 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_FFFF VPC-3 (64 KB) + * 0xFFC0_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_IMMR 0x80000000 +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CONFIG_SYS_DDR_SIZE 512 /* MB */ + +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is sys memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE + +/* DDR Controller Configuration + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ +#ifdef CONFIG_ADS5121_REV2 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 +#else +#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#endif +#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E +#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E + +#define CONFIG_SYS_MICRON_NOP 0x01380000 +#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 +#define CONFIG_SYS_MICRON_EM2 0x01020000 +#define CONFIG_SYS_MICRON_EM3 0x01030000 +#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 +#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 +#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 + +/* DDR Priority Manager Configuration */ +#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 +#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 +#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 +#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 +#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 +#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 +#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 +#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 +#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 +#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ + +#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 0x00400000 /* max flash size */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only) + */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_MPC5121_NFC +#define CONFIG_SYS_NAND_BASE 0x40000000 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE + +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS 1 + +#define CONFIG_SYS_SRAM_BASE 0x30000000 +#define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ + +/* ALE active low, data size 4bytes */ +#define CONFIG_SYS_CS0_CFG 0x05051150 + +/* Use not alternative CS timing */ +#define CONFIG_SYS_CS_ALETIMING 0x00000000 + +/* ALE active low, data size 4bytes */ +#define CONFIG_SYS_CS1_CFG 0x1f1f3090 +#define CONFIG_SYS_VPC3_BASE 0x82000000 /* start of VPC3 space */ +#define CONFIG_SYS_VPC3_SIZE 0x00010000 /* max VPC3 size */ + +/* Use SRAM for initial stack */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE /* Init RAM addr */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Monitor length */ +#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Malloc size */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif +#define CONFIG_BAUDRATE 9600 /* ... at 9600 bps */ +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ +#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */ + +/* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Atmel: AT24C32A-10TQ-2.7 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10ms of delay */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-Byte Page Write Mode */ +#define CONFIG_SYS_EEPROM_WREN /* Use EEPROM write protect */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_FEC_AN_TIMEOUT 1 +#define CONFIG_HAS_ETH0 + +/* + * Configure on-board RTC + */ +#define CONFIG_SYS_RTC_BUS_NUM 0x01 +#define CONFIG_SYS_I2C_RTC_ADDR 0x32 +#define CONFIG_RTC_RX8025 + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_EEPROM /* Store env in I2C EEPROM */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_OFFSET 0x0000 /* environment starts here */ + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE +#undef CONFIG_CMD_FUSE +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_ELF +#define CONFIG_DOS_PARTITION + +/* + * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5121e Reference Manual. + */ +/* #define CONFIG_WATCHDOG */ /* enable watchdog */ +#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_HZ 1000 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ + +/* Cache Configuration */ +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_CACHELINE_SIZE 32 +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CACHELINE_SHIFT 5 +#endif + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_TIMESTAMP + +#define CONFIG_HOSTNAME mecp512x +#define CONFIG_BOOTFILE /tftpboot/mecp512x/uImage +#define CONFIG_ROOTPATH /tftpboot/mecp512x/target_root + +#define CONFIG_LOADADDR 400000 /* def. location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to MECP5123" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr_r=200000\0" \ + "kernel_addr_r=600000\0" \ + "fdt_addr_r=880000\0" \ + "ramdisk_addr_r=900000\0" \ + "u-boot_addr=FFF00000\0" \ + "kernel_addr=FFC40000\0" \ + "fdt_addr=FFEC0000\0" \ + "ramdisk_addr=FC040000\0" \ + "ramdiskfile=/tftpboot/mecp512x/uRamdisk\0" \ + "u-boot=/tftpboot/mecp512x/u-boot.bin\0" \ + "bootfile=/tftpboot/mecp512x/uImage\0" \ + "fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0" \ + "rootpath=/tftpboot/mecp512x/target_root\n" \ + "netdev=eth0\0" \ + "consdev=ttyPSC0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} " \ + "console=${consdev},${baudrate}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "net_self=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run ramargs addip addtty;" \ + "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off ${u-boot_addr} +${filesize};" \ + "era ${u-boot_addr} +${filesize};" \ + "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ + "upd=run load update\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + +#define OF_CPU "PowerPC,5121@0" +#define OF_SOC_COMPAT "fsl,mpc5121-immr" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc@80000000/serial@11300" + +#endif /* __CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index aa117c8f7..72715f6ed 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -260,6 +260,8 @@ #if defined(CONFIG_CMD_JFFS2) /* JFFS2 partitions */ #define CONFIG_CMD_MTDPARTS /* mtdparts command line support */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=ml401-0" /* default mtd partition table */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 99a02cc22..fa4310b79 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -276,6 +276,8 @@ * MTD configuration */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=motionpro-0" #define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \ "13m(fs),2m(kernel),256k(uboot)," \ diff --git a/include/configs/ads5121.h b/include/configs/mpc5121ads.h index d87902468..45a004eb2 100644 --- a/include/configs/ads5121.h +++ b/include/configs/mpc5121ads.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007, 2008 DENX Software Engineering + * (C) Copyright 2007-2009 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -21,15 +21,15 @@ */ /* - * ADS5121 board configuration file + * MPC5121ADS board configuration file */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_ADS5121 1 +#define CONFIG_MPC5121ADS 1 /* - * Memory map for the ADS5121 board: + * Memory map for the MPC5121ADS board: * * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) @@ -59,7 +59,7 @@ /* CONFIG_PCI is defined at config time */ -#ifdef CONFIG_ADS5121_REV2 +#ifdef CONFIG_MPC5121ADS_REV2 #define CONFIG_SYS_MPC512X_CLKIN 66000000 /* in Hz */ #else #define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */ @@ -78,7 +78,7 @@ /* * DDR Setup - manually set all parameters as there's no SPD etc. */ -#ifdef CONFIG_ADS5121_REV2 +#ifdef CONFIG_MPC5121ADS_REV2 #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #else #define CONFIG_SYS_DDR_SIZE 512 /* MB */ @@ -130,7 +130,7 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#ifdef CONFIG_ADS5121_REV2 +#ifdef CONFIG_MPC5121ADS_REV2 #define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 @@ -200,6 +200,26 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only) + */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_MPC5121_NFC +#define CONFIG_SYS_NAND_BASE 0x40000000 + +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ + +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE + +/* * CPLD registers area is really only 32 bytes in size, but the smallest possible LP * window is 64KB */ @@ -222,7 +242,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ #else @@ -287,7 +307,6 @@ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #if 0 @@ -434,8 +453,8 @@ */ #define CONFIG_TIMESTAMP -#define CONFIG_HOSTNAME ads5121 -#define CONFIG_BOOTFILE ads5121/uImage +#define CONFIG_HOSTNAME mpc5121ads +#define CONFIG_BOOTFILE mpc5121ads/uImage #define CONFIG_ROOTPATH /opt/eldk/ppc_6xx #define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */ @@ -458,10 +477,10 @@ "kernel_addr=FFC40000\0" \ "fdt_addr=FFEC0000\0" \ "ramdisk_addr=FC040000\0" \ - "ramdiskfile=ads5121/uRamdisk\0" \ - "u-boot=ads5121/u-boot.bin\0" \ - "bootfile=ads5121/uImage\0" \ - "fdtfile=ads5121/ads5121.dtb\0" \ + "ramdiskfile=mpc5121ads/uRamdisk\0" \ + "u-boot=mpc5121ads/u-boot.bin\0" \ + "bootfile=mpc5121ads/uImage\0" \ + "fdtfile=mpc5121ads/mpc5121ads.dtb\0" \ "rootpath=/opt/eldk/ppc_6xx\n" \ "netdev=eth0\0" \ "consdev=ttyPSC0\0" \ @@ -520,7 +539,7 @@ #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA +#define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) @@ -534,7 +553,7 @@ /* Interval between registers */ #define CONFIG_SYS_ATA_STRIDE 4 -#define ATA_BASE_ADDR MPC512X_PATA +#define ATA_BASE_ADDR get_pata_base() /* * Control register bit definitions diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index a1783b200..7d421556e 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -179,6 +179,7 @@ */ #define CONFIG_VERSION_VARIABLE 1 #define CONFIG_TSI108_I2C +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 24fa144ec..90a8d8405 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -183,6 +183,8 @@ /* mtdparts command line support */ /* Note: fake mtd_id used, no linux mtd map file */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=mx1fs2-0" #ifdef BUS32BIT_VERSION diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 4d5c1ab34..4bed7ae26 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -61,8 +61,8 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#if defined(CONFIG_440) #define CONFIG_NET_MULTI 1 +#if defined(CONFIG_440) #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_SYS_RX_ETH_BUFFER 32 /* number of eth rx buffers */ #else diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 5cfee6622..5062cdb16 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -130,6 +130,8 @@ * partitions (mtdparts command line support) */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" #define MTDPARTS_DEFAULT "mtdparts=" \ "omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index a3d9cf694..c2bd7e67e 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -105,6 +105,7 @@ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ "1920k(u-boot),128k(u-boot-env),"\ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 549cef99f..e205c01b4 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -149,6 +149,8 @@ /* Environment information */ #define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTFILE uImage + #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 50c05dcb9..9e000ed1c 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -138,19 +138,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define SECTORSIZE 512 - -#define NAND_ALLOW_ERASE_ALL -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 -#define NAND_NO_RB 1 -#define CONFIG_SYS_NAND_WP - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h new file mode 100644 index 000000000..c2ad5bf19 --- /dev/null +++ b/include/configs/omap3_zoom2.h @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments. + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * Nishanth Menon <nm@ti.com> + * Tom Rix <Tom.Rix@windriver.com> + * + * Configuration settings for the TI OMAP3430 Zoom II board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + * Zoom2 uses the TL16CP754C on the debug board + */ +#define CONFIG_SERIAL_MULTI 1 +/* + * 0 - 1 : first USB with respect to the left edge of the debug board + * 2 - 3 : second USB with respect to the left edge of the debug board + */ +#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0) + +#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_REG_SIZE (-2) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200} + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_BLUE 0 +#define STATUS_LED_RED 1 +/* Blue */ +#define STATUS_LED_BIT STATUS_LED_BLUE +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ +#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ +#endif +#define CONFIG_OMAP3_GPIO_3 /* board revision */ +#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_PROMPT "OMAP3 Zoom2 # " +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* Memtest from start of memory to 31MB */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000) +/* The default load address is the start of memory */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) +/* everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using these settings + */ +#define CONFIG_STACKSIZE SZ_128K +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K +#define CONFIG_STACKSIZE_FIQ SZ_4K +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index edaa81b59..1255f21e8 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -51,6 +51,7 @@ * Misc configuration options */ #define CONFIG_USE_IRQ 1 /* we need IRQ stuff for timer */ +#define CONFIG_TIMER_IRQ #define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ #define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index ed873faca..635ef71bc 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -62,6 +62,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0db17b354..f0dbe81d1 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -29,8 +29,7 @@ #define __CONFIG_H /* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9263" - +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO #define MASTER_PLL_DIV 15 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 7485f7241..2cae8ca9b 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -100,6 +100,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/qong.h b/include/configs/qong.h index a67006aa2..7e6718503 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -213,6 +213,8 @@ * JFFS2 partitions */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=physmap-flash.0" #define MTDPARTS_DEFAULT \ "mtdparts=physmap-flash.0:256k(U-Boot),128k(env1)," \ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index f4e08c689..0ab6fc31e 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -408,9 +408,9 @@ "echo hostname ${hostname}\0" \ "ana=run adc ; run dac\0" \ "adc=run adc-12 ; run adc-34\0" \ -"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \ -"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \ -"dac=echo ### DAC ; imd.b 11 81 5\0" \ +"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \ +"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \ +"dac=echo ### DAC ; i2c md 11 81 5\0" \ "boot-hook=echo\0" /* What should the console's baud rate be? */ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 7197aaf79..242f42fdc 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -62,6 +62,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ +#define CONFIG_NET_MULTI #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index edd928d81..84a251a06 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -35,8 +35,8 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ @@ -279,7 +279,6 @@ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index fa226b28c..89acacc7f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -112,13 +112,26 @@ /* * Environment */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#define CONFIG_ENV_IS_IN_NAND /* use NAND for environ vars */ +#define CONFIG_ENV_IS_EMBEDDED /* use embedded environment */ +#elif defined(CONFIG_SYS_RAMBOOT) +#define CONFIG_ENV_IS_NOWHERE /* Store env in memory only */ +#define CONFIG_ENV_SIZE (8 << 10) +/* + * In RAM-booting version, we have no environment storage. So we need to + * provide at least preliminary MAC addresses for the 4xx EMAC driver to + * register the interfaces. Those two addresses are generated via the + * tools/gen_eth_addr tool and should only be used in a closed laboratory + * environment. + */ +#define CONFIG_ETHADDR 4a:56:49:22:3e:43 +#define CONFIG_ETH1ADDR 02:93:53:d5:06:98 #else -#define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */ -#define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ +#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environ vars */ #endif +#if defined(CONFIG_CMD_FLASH) /* * FLASH related */ @@ -148,6 +161,7 @@ #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif +#endif /* CONFIG_CMD_FLASH */ /* * IPL (Initial Program Loader, integrated inside CPU) @@ -211,7 +225,8 @@ * DDR SDRAM */ #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ + !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ @@ -306,7 +321,7 @@ * overwrite part of the U-Boot image which is already loaded from NAND * to SDRAM. */ -#if defined(CONFIG_NAND_U_BOOT) +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_POST_MEMORY_ON 0 #else #define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY @@ -354,7 +369,8 @@ /* * On Sequoia CS0 and CS3 are switched when configuring for NAND booting */ -#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ + !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x03017200 diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 35f3e3a02..5a2ef3aa8 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -215,6 +215,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM5200-0" #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ "1408k(kernel)," \ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index becd13eac..5b91b4d7c 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -243,7 +243,6 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C2_OFFSET 0x3100 /* I2C RTC */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 8c48c669d..836081d0d 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -139,7 +139,7 @@ */ #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CONFIG_SYS_I2C_NOPROBES { 0x69 } /* avoid i2c probe hangup (why?) */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ diff --git a/include/configs/trab.h b/include/configs/trab.h index 51ad3cada..7687ee6dc 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -375,6 +375,8 @@ /* Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=0" /* production flash layout */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index 49173181f..49045fd06 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -65,6 +65,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_SERIAL_MULTI #define CONFIG_FFUART 1 /* we use FFUART on Conxs */ #define CONFIG_BTUART 1 /* we use BTUART on Conxs */ diff --git a/include/configs/vct.h b/include/configs/vct.h index fe679974c..e72b50454 100644 --- a/include/configs/vct.h +++ b/include/configs/vct.h @@ -296,6 +296,7 @@ int vct_gpio_get(int pin); #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_UBI #define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS #define CONFIG_CMD_MTDPARTS diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 021012d0f..9ebafcccb 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -226,6 +226,8 @@ * Dynamic MTD partition support */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=TQM8xxL-0" #define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index aa8efaad5..c9c313235 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -190,6 +190,8 @@ * JFFS2 partitions (mtdparts command line support) */ #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #define MTDIDS_DEFAULT "nor0=omapflash.0" #define MTDPARTS_DEFAULT "mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)" diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 197ac0bbd..9a20cce45 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -33,6 +33,7 @@ /* * Select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_BTUART 1 /* BTUART is default on WEP dev board */ #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 1632d2962..83883f6fd 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -55,6 +55,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */ diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h index e3ea84b31..6efe3421f 100644 --- a/include/configs/xilinx-ppc.h +++ b/include/configs/xilinx-ppc.h @@ -109,6 +109,8 @@ #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_FLASH_CFI_MTD #else #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_NO_FLASH diff --git a/include/configs/xm250.h b/include/configs/xm250.h index c8bdf3186..f18701abf 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -77,6 +77,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART */ /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index 7e2abbf34..2697ccaf6 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -99,6 +99,7 @@ #define CONFIG_SMC_USE_32_BIT 1 /* select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 217636a61..15c37087f 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -72,6 +72,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ |