diff options
Diffstat (limited to 'include/configs')
43 files changed, 9353 insertions, 772 deletions
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 8753b9ff6..c380c5459 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -179,6 +179,19 @@ #undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #endif #endif /* CONFIG_MPC5200 */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + /* * I2C configuration */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h new file mode 100644 index 000000000..cecb2258f --- /dev/null +++ b/include/configs/MPC832XEMDS.h @@ -0,0 +1,631 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83xx family */ +#define CONFIG_MPC832X 1 /* MPC832x CPU specific */ +#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CSB_TO_CLKIN_2X1 |\ + HRCWL_CORE_TO_CSB_2X1 |\ + HRCWL_CE_PLL_VCO_DIV_2 |\ + HRCWL_CE_PLL_DIV_1X1 |\ + HRCWL_CE_TO_PLL_1X3) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_BIG_ENDIAN |\ + HRCWH_LALE_NORMAL) +#endif + +/* + * System IO Config + */ +#define CFG_SICRL 0x00000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ + +#undef CONFIG_SPD_EEPROM +#if defined(CONFIG_SPD_EEPROM) +/* Determine DDR configuration from I2C interface + */ +#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ +#else +/* Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 128 /* MB */ +#define CFG_DDR_CS0_CONFIG 0x80840102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x3935d322 +#define CFG_DDR_TIMING_2 0x0f9048ca +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x44400232 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03200064 +#define CFG_DDR_CS0_BNDS 0x00000007 +#define CFG_DDR_SDRAM_CFG 0x43080000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 16 /* FLASH size is 16M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 128 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ + +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * SDRAM on the Local Bus + */ +#undef CFG_LB_SDRAM /* The board has not SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ + +/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON 0x0063b723 + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + +#endif + +/* + * Windows to access PIB via local bus + */ +#define CFG_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ + +/* + * CS2 on Local Bus, to PIB + */ +#define CFG_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ +#define CFG_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * CS3 on Local Bus, to PIB + */ +#define CFG_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ +#define CFG_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8323@0" +#define OF_SOC "soc8323@e0000000" +#define OF_QE "qe@e0100000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8323@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" + +#define CONFIG_UEC_ETH1 /* ETH3 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 2 /* UCC3 */ +#define CFG_UEC1_RX_CLK QE_CLK9 +#define CFG_UEC1_TX_CLK QE_CLK10 +#define CFG_UEC1_ETH_TYPE FAST_ETH +#define CFG_UEC1_PHY_ADDR 3 +#define CFG_UEC1_INTERFACE_MODE ENET_100_MII +#endif + +#define CONFIG_UEC_ETH2 /* ETH4 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 3 /* UCC4 */ +#define CFG_UEC2_RX_CLK QE_CLK7 +#define CFG_UEC2_TX_CLK QE_CLK8 +#define CFG_UEC2_ETH_TYPE FAST_ETH +#define CFG_UEC2_PHY_ADDR 4 +#define CFG_UEC2_INTERFACE_MODE ENET_100_MII +#endif + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C ) +#endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 16384 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_ETHADDR 00:04:9f:ef:03:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:03:02 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc832xemds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 66f164660..0460be9e5 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -36,6 +36,7 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ @@ -61,7 +62,7 @@ #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ -#define CFG_IMMRBAR 0xE0000000 +#define CFG_IMMR 0xE0000000 #undef CFG_DRAM_TEST /* memory test, takes time */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */ @@ -70,7 +71,7 @@ /* * DDR Setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#define CONFIG_DDR_ECC /* support DDR ECC function */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ @@ -89,8 +90,15 @@ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ #define CFG_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #undef CONFIG_DDR_2T_TIMING +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + #if defined(CONFIG_SPD_EEPROM) /* * Determine DDR configuration from I2C interface. @@ -101,6 +109,21 @@ * Manually set up DDR parameters */ #define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS2_BNDS 0x0000000f +#define CFG_DDR_CS2_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CFG_DDR_TIMING_1 0x36332321 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ @@ -115,6 +138,7 @@ #define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ #endif #endif +#endif /* * SDRAM on the Local Bus @@ -128,19 +152,20 @@ #define CFG_FLASH_CFI /* use the Common Flash Interface */ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CFG_FLASH_SIZE 8 /* flash size in MB */ +#define CFG_FLASH_SIZE 32 /* max flash size in MB */ /* #define CFG_FLASH_USE_BUFFER_WRITE */ #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ BR_V) /* valid */ - -#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ -#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ -#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ @@ -185,7 +210,11 @@ #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) #define CFG_LBC_LBCR 0x00000000 -#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ +/* + * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. + * if board has SRDAM on local bus, you can define CFG_LB_SDRAM + */ +#undef CFG_LB_SDRAM #ifdef CFG_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ @@ -299,29 +328,45 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ /* Use the HUSH parser */ #define CFG_HUSH_PARSER #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR+CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) /* USB */ #define CFG_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ @@ -615,8 +660,8 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CFG_IBAT5L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT5U (CFG_IMMRBAR | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ #define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) @@ -666,11 +711,11 @@ #define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif -#define CONFIG_IPADDR 192.168.205.5 +#define CONFIG_IPADDR 192.168.1.253 #define CONFIG_HOSTNAME mpc8349emds -#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx -#define CONFIG_BOOTFILE /tftpboot/tqm83xx/uImage +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -703,14 +748,31 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=/tftpboot/mpc8349emds/uImage\0" \ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ "upd=run load;run update\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8349emds.dtb\0" \ "" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + #define CONFIG_BOOTCOMMAND "run flash_self" #endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h new file mode 100644 index 000000000..37bbfb336 --- /dev/null +++ b/include/configs/MPC8349ITX.h @@ -0,0 +1,703 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + MPC8349E-mITX and MPC8349E-mITX-GP board configuration file + + Memory map: + + 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) + 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) + 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) + 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) + 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) + 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) + 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) + 0xF001_0000-0xF001_FFFF Local bus expansion slot + 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) + 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory + 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) + + I2C address list: + Align. Board + Bus Addr Part No. Description Length Location + ---------------------------------------------------------------- + I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 + + I2C1 0x20 PCF8574 I2C Expander 0 U8 + I2C1 0x21 PCF8574 I2C Expander 0 U10 + I2C1 0x38 PCF8574A I2C Expander 0 U8 + I2C1 0x39 PCF8574A I2C Expander 0 U10 + I2C1 0x51 (DDR) DDR EEPROM 1 U1 + I2C1 0x68 DS1339 RTC 1 U68 + + Note that a given board has *either* a pair of 8574s or a pair of 8574As. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#if (TEXT_BASE == 0xFE000000) +#define CFG_LOWBOOT +#endif + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC834X /* MPC834x family (8343, 8347, 8349) */ +#define CONFIG_MPC8349 /* MPC8349 specific */ + +#define CFG_IMMR 0xE0000000 /* The IMMR is relocated to here */ + + +/* On-board devices */ + +#ifdef CONFIG_MPC8349ITX +#define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ +#define CONFIG_VSC7385 /* The Vitesse 7385 5-port switch */ +#endif + +#define CONFIG_PCI +#define CONFIG_RTC_DS1337 +#define CONFIG_HARD_I2C +#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ + +/* + * Device configurations + */ + +/* I2C */ +#ifdef CONFIG_HARD_I2C + +#define CONFIG_MISC_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 +#define CFG_SPD_BUS_NUM 1 /* The I2C bus for SPD */ + +#define CFG_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ +#define CFG_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ +#define CFG_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ +#define CFG_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ +#define CFG_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ +#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ + +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* Don't probe these addresses: */ +#define CFG_I2C_NOPROBES {{1, CFG_I2C_8574_ADDR1}, \ + {1, CFG_I2C_8574_ADDR2}, \ + {1, CFG_I2C_8574A_ADDR1}, \ + {1, CFG_I2C_8574A_ADDR2}} +/* Bit definitions for the 8574[A] I2C expander */ +#define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ +#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ +#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ +#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ +#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ + +#undef CONFIG_SOFT_I2C + +#endif + +/* Compact Flash */ +#ifdef CONFIG_COMPACT_FLASH + +#define CFG_IDE_MAXBUS 1 +#define CFG_IDE_MAXDEVICE 1 + +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_BASE_ADDR CFG_CF_BASE +#define CFG_ATA_DATA_OFFSET 0x0000 +#define CFG_ATA_REG_OFFSET 0 +#define CFG_ATA_ALT_OFFSET 0x0200 +#define CFG_ATA_STRIDE 2 + +#define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ + +#define CONFIG_DOS_PARTITION + +#endif + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_83XX_DDR_USES_CS0 +#define CFG_MEMTEST_START 0x1000 /* memtest region */ +#define CFG_MEMTEST_END 0x2000 + +#ifdef CONFIG_HARD_I2C +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#endif + +#ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ + #define CFG_DDR_SIZE 256 /* Mb */ + #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + + #define CFG_DDR_TIMING_1 0x26242321 + #define CFG_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ +#endif + +/* + *Flash on the Local Bus + */ + +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */ +#define CFG_FLASH_EMPTY_INFO +#define CFG_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* The ITX has two flash chips, but the ITX-GP has only one. To support both +boards, we say we have two, but don't display a message if we find only one. */ +#define CFG_FLASH_QUIET_TEST +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE + 0x800000} +#define CFG_FLASH_SIZE 16 /* FLASH size in MB */ +#define CFG_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ + +/* + * BRx, ORx, LBLAWBARx, and LBLAWARx + */ + +/* Flash */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BR_PS_16 | BR_V) +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE +#define CFG_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CFG_FLASH_SIZE_SHIFT)) + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385 + +#define CFG_VSC7385_BASE 0xF8000000 + +#define CFG_BR1_PRELIM (CFG_VSC7385_BASE | BR_PS_8 | BR_V) +#define CFG_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_LBLAWBAR1_PRELIM CFG_VSC7385_BASE +#define CFG_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) + +#endif + +/* LED */ + +#define CFG_LED_BASE 0xF9000000 +#define CFG_BR2_PRELIM (CFG_LED_BASE | BR_PS_8 | BR_V) +#define CFG_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | \ + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ + OR_GPCM_EHTR | OR_GPCM_EAD) + +/* Compact Flash */ + +#ifdef CONFIG_COMPACT_FLASH + +#define CFG_CF_BASE 0xF0000000 + +#define CFG_BR3_PRELIM (CFG_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) +#define CFG_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) + +#define CFG_LBLAWBAR3_PRELIM CFG_CF_BASE +#define CFG_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) + +#endif + +/* + * U-Boot memory configuration + */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_BAUDRATE 115200 + +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE +#define CONFIG_OF_BOARD_SETUP + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + +/* + * PCI + */ +#ifdef CONFIG_PCI + +#define CONFIG_MPC83XX_PCI2 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE (CFG_PCI1_MEM_BASE + CFG_PCI1_MEM_SIZE) +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_PCI2_MEM_BASE (CFG_PCI1_MMIO_BASE + CFG_PCI1_MMIO_SIZE) +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE (CFG_PCI2_MEM_BASE + CFG_PCI2_MEM_SIZE) +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS (CFG_PCI1_IO_PHYS + CFG_PCI1_IO_SIZE) +#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */ +#endif + +#define _IO_BASE 0x00000000 /* points to PCI I/O space */ + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#ifdef CONFIG_RTL8139 +/* This macro is used by RTL8139 but not defined in PPC architecture */ +#define KSEG1ADDR(x) (x) +#endif + +#ifndef CONFIG_PCI_PNP + #define PCI_ENET0_IOADDR 0x00000000 + #define PCI_ENET0_MEMADDR CFG_PCI2_MEM_BASE + #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ +#endif + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ + +#endif + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66666666 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#endif + +/* TSEC */ + +#ifdef CONFIG_TSEC_ENET + +#define CONFIG_NET_MULTI +#define CONFIG_MII +#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ + +#define CONFIG_MPC83XX_TSEC1 + +#ifdef CONFIG_MPC83XX_TSEC1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CFG_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CFG_TSEC2_OFFSET 0x25000 +#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ +#define TSEC2_PHY_ADDR 4 +#define TSEC2_PHYIDX 0 +#endif + +#define CONFIG_ETHPRIME "Freescale TSEC" + +#endif + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + (4 * CFG_ENV_SECT_SIZE)) + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* CONFIG_COMMANDS */ + +#ifdef CONFIG_COMPACT_FLASH +#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) +#else +#define CONFIG_COMMANDS_CF 0 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_COMMANDS_PCI CFG_CMD_PCI +#else +#define CONFIG_COMMANDS_PCI 0 +#endif + +#ifdef CONFIG_HARD_I2C +#define CONFIG_COMMANDS_I2C CFG_CMD_I2C +#else +#define CONFIG_COMMANDS_I2C 0 +#endif + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CONFIG_COMMANDS_CF | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CONFIG_COMMANDS_I2C | \ + CONFIG_COMMANDS_PCI | \ + CFG_CMD_SDRAM | \ + CFG_CMD_DATE | \ + CFG_CMD_CACHE | \ + CFG_CMD_IRQ) +#include <cmd_confdefs.h> + +/* Watchdog */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#ifdef CONFIG_MPC8349ITX +#define CFG_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ +#endif + +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) + +#ifdef CFG_LOWBOOT +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* + * System performance + */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ +#define CFG_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ +#define CFG_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ +#define CFG_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ +#define CFG_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ + +/* + * System IO Config + */ +#define CFG_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ +#define CFG_SICRL (SICRL_LDP_A | SICRL_USB1) + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL CFG_HID0_INIT + +#define CFG_HID2 HID2_HBE + +/* DDR */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L 0 +#define CFG_IBAT1U 0 +#define CFG_IBAT2L 0 +#define CFG_IBAT2U 0 +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L 0 +#define CFG_IBAT3U 0 +#define CFG_IBAT4L 0 +#define CFG_IBAT4U 0 +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L 0 +#define CFG_IBAT7U 0 + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_MPC83XX_TSEC1 +#define CONFIG_ETHADDR 00:E0:0C:00:8C:01 +#endif + +#ifdef CONFIG_MPC83XX_TSEC2 +#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 +#endif + +#define CONFIG_IPADDR 192.168.1.253 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.252.0 +#define CONFIG_NETDEV eth0 + +#ifdef CONFIG_MPC8349ITX +#define CONFIG_HOSTNAME mpc8349emitx +#else +#define CONFIG_HOSTNAME mpc8349emitxgp +#endif + +/* Default path and filenames */ +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +#ifdef CONFIG_MPC8349ITX +#define CONFIG_FDTFILE mpc8349emitx.dtb +#else +#define CONFIG_FDTFILE mpc8349emitxgp.dtb +#endif + +#define CONFIG_BOOTDELAY 0 + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_BOOTARGS \ + "root=/dev/nfs rw" \ + " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" MK_STR(CONFIG_ROOTPATH) \ + " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ + MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ + MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ + " console=ttyS0," MK_STR(CONFIG_BAUDRATE) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=400000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ + " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw" \ + " console=$console,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h new file mode 100644 index 000000000..d2af0e1df --- /dev/null +++ b/include/configs/MPC8360EMDS.h @@ -0,0 +1,662 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu <daveliu@freescale.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */ + +/* + * System Clock Setup + */ +#ifdef CONFIG_PCISLAVE +#define CONFIG_83XX_PCICLK 66000000 /* in HZ */ +#else +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#define CONFIG_SYS_CLK_FREQ 66000000 +#endif + +/* + * Hardware Reset Configuration Word + */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_VCO_1X2 |\ + HRCWL_CE_PLL_VCO_DIV_4 |\ + HRCWL_CE_PLL_DIV_1X1 |\ + HRCWL_CE_TO_PLL_1X6 |\ + HRCWL_CORE_TO_CSB_2X1) + +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_PCICKDRV_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCICKDRV_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT) +#endif + +/* + * System IO Config + */ +#define CFG_SICRH 0x00000000 +#define CFG_SICRL 0x40000000 + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +/* + * IMMR new address + */ +#define CFG_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#define CONFIG_DDR_ECC /* support DDR ECC function */ +#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ + +/* + * DDRCDR - DDR Control Driver Register + */ +#define CFG_DDRCDR_VALUE 0x80080001 + +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */ +#else +/* + * Manually set up DDR parameters + */ +#define CFG_DDR_SIZE 256 /* MB */ +#if defined(CONFIG_DDR_II) +#define CFG_DDRCDR 0x80080001 +#define CFG_DDR_CS0_BNDS 0x0000000f +#define CFG_DDR_CS0_CONFIG 0x80330102 +#define CFG_DDR_TIMING_0 0x00220802 +#define CFG_DDR_TIMING_1 0x38357322 +#define CFG_DDR_TIMING_2 0x2f9048c8 +#define CFG_DDR_TIMING_3 0x00000000 +#define CFG_DDR_CLK_CNTL 0x02000000 +#define CFG_DDR_MODE 0x47d00432 +#define CFG_DDR_MODE2 0x8000c000 +#define CFG_DDR_INTERVAL 0x03cf0080 +#define CFG_DDR_SDRAM_CFG 0x43000000 +#define CFG_DDR_SDRAM_CFG2 0x00401000 +#else +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) +#define CFG_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ +#define CFG_DDR_TIMING_2 0x00000800 /* may need tuning */ +#define CFG_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ +#define CFG_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ +#define CFG_DDR_INTERVAL 0x045b0100 /* page mode */ +#endif +#endif + +/* + * Memory test + */ +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * The reserved memory + */ + +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ +#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ + +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) /* valid */ +#define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * BCSR on the Local Bus + */ +#define CFG_BCSR 0xF8000000 +#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ +#define CFG_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ + +#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ +#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ +#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + +#define CFG_LB_SDRAM /* if board has SRDAM on local bus */ + +#ifdef CFG_LB_SDRAM +#define CFG_LBLAWBAR2_PRELIM CFG_LBC_SDRAM_BASE +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ + +/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 + * + * CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 + */ + +#define CFG_OR2_PRELIM 0xfc006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON 0x0063b723 + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) + +#endif + +/* + * Windows to access PIB via local bus + */ +#define CFG_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ +#define CFG_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ + +/* + * CS4 on Local Bus, to PIB + */ +#define CFG_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ +#define CFG_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * CS5 on Local Bus, to PIB + */ +#define CFG_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ +#define CFG_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8360@0" +#define OF_SOC "soc8360@e0000000" +#define OF_QE "qe@e0100000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8360@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x52} /* Don't probe these addrs */ +#define CFG_I2C_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 + +/* + * Config on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI_MEM_BASE 0x80000000 +#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE +#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_MMIO_BASE 0x90000000 +#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE +#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI_IO_BASE 0xE0300000 +#define CFG_PCI_IO_PHYS 0xE0300000 +#define CFG_PCI_IO_SIZE 0x100000 /* 1M */ + +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE +#define CFG_PCI_SLV_MEM_BUS 0x00000000 +#define CFG_PCI_SLV_MEM_SIZE 0x80000000 + + +#ifdef CONFIG_PCI + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + +#endif /* CONFIG_PCI */ + + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "Freescale GETH" +#define CONFIG_PHY_MODE_NEED_CHANGE + +#define CONFIG_UEC_ETH1 /* GETH1 */ + +#ifdef CONFIG_UEC_ETH1 +#define CFG_UEC1_UCC_NUM 0 /* UCC1 */ +#define CFG_UEC1_RX_CLK QE_CLK_NONE +#define CFG_UEC1_TX_CLK QE_CLK9 +#define CFG_UEC1_ETH_TYPE GIGA_ETH +#define CFG_UEC1_PHY_ADDR 0 +#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII +#endif + +#define CONFIG_UEC_ETH2 /* GETH2 */ + +#ifdef CONFIG_UEC_ETH2 +#define CFG_UEC2_UCC_NUM 1 /* UCC2 */ +#define CFG_UEC2_RX_CLK QE_CLK_NONE +#define CFG_UEC2_TX_CLK QE_CLK4 +#define CFG_UEC2_ETH_TYPE GIGA_ETH +#define CFG_UEC2_PHY_ADDR 1 +#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII +#endif + +/* + * Environment + */ + +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_ASKENV \ + | CFG_CMD_I2C ) +#endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Cache Config + */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ +#endif + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CFG_IBAT1L (CFG_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT1U (CFG_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* BCSR: cache-inhibit and guarded */ +#define CFG_IBAT2L (CFG_BCSR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CFG_IBAT3L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_DBAT3L (CFG_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +/* Local bus SDRAM: cacheable */ +#define CFG_IBAT4L (CFG_LBC_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT4U (CFG_LBC_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP) +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) +#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else +#define CFG_IBAT6L (0) +#define CFG_IBAT6U (0) +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_ETHADDR 00:04:9f:ef:01:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=1000000\0" \ + "ramdiskfile=ramfs.83xx\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8360emds.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + + +#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND + +#endif /* __CONFIG_H */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 9d5c4f4d0..027dd22bf 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -1,6 +1,9 @@ /* + * (C) Copyright 2007 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com + * * (C) Copyright 2001-2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com + * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. @@ -32,8 +35,6 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $" - #define CONFIG_405GP 1 /* This is a PPC405 CPU */ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_PCI405 1 /* ...on a PCI405 board */ @@ -53,9 +54,9 @@ "mem_linux=14336k\0" \ "optargs=panic=0\0" \ "ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \ - "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ + "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \ "" -#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci" +#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci" #define CONFIG_PREBOOT /* enable preboot variable */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index dd5d83168..d02c39b28 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -51,17 +51,13 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if 0 /* test-only */ #define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_PHY1_ADDR 1 /* PHY address */ -#else -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 0 /* PHY address */ -#endif #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 2c34ce09b..5b011e82a 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -238,6 +238,17 @@ "protect on FC000000 +${filesize}\0" #endif +#ifndef CONFIG_CAM5200 +#define CUSTOM_ENV_SETTINGS \ + "bootfile=/tftpboot/tqm5200/uImage\0" \ + "u-boot=/tftpboot/tqm5200/u-boot.bin\0" +#else +#define CUSTOM_ENV_SETTINGS \ + "bootfile=cam5200/uImage\0" \ + "u-boot=cam5200/u-boot.bin\0" \ + "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ @@ -255,8 +266,7 @@ "bootm ${kernel_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ "bootm\0" \ - "bootfile=/tftpboot/tqm5200/uImage\0" \ - "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \ + CUSTOM_ENV_SETTINGS \ "load=tftp 200000 ${u-boot}\0" \ ENV_UPDT \ "" @@ -332,15 +342,7 @@ */ #define CFG_FLASH_BASE 0xFC000000 -#ifndef CONFIG_CAM5200 -/* use CFI flash driver */ -#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#else /* CONFIG_CAM5200 */ +#if defined(CONFIG_CAM5200) && defined(CONFIG_CAM5200_NIOSFLASH) #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks (= chip selects) */ #define CFG_FLASH_WORD_SIZE unsigned int /* main flash device with */ @@ -351,7 +353,15 @@ #define CFG_FLASH_ADDR1 0x2AA #define CFG_FLASH_2ND_16BIT_DEV 1 /* NIOS flash is a 16bit device */ #define CFG_MAX_FLASH_SECT 128 -#endif /* ifndef CONFIG_CAM5200 */ +#else +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#endif #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h new file mode 100644 index 000000000..925bf3431 --- /dev/null +++ b/include/configs/TQM8272.h @@ -0,0 +1,754 @@ +/* + * (C) Copyright 2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ +#define CONFIG_MPC8272_FAMILY 1 +#define CONFIG_TQM8272 1 + +#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */ +#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */ + +#define STK82xx_150 1 /* on a STK82xx.150 */ + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */ + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_EARLY_INIT_R 1 + +#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) +#define CONFIG_BAUDRATE 230400 +#else +#define CONFIG_BAUDRATE 115200 +#endif + +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consdev=ttyCPM0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "hostname=tqm8272\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=$(consdev),$(baudrate)\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addcons;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 300000 ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "bootfile=/tftpboot/tqm8272/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40100000\0" \ + "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \ + "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \ + "cp.b 300000 40000000 40000;" \ + "setenv filesize;saveenv\0" \ + "cphwib=cp.b 4003fc00 33fc00 400\0" \ + "upd=run load;run cphwib;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_I2C 1 + +#if CONFIG_I2C +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#define ADD_CMD_I2C CFG_CMD_I2C | \ + CFG_CMD_DATE |\ + CFG_CMD_DTT |\ + CFG_CMD_EEPROM +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +/* + * Software (bit-bang) I2C driver configuration + */ +#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ +#define I2C_ACTIVE (iop->pdir |= 0x00010000) +#define I2C_TRISTATE (iop->pdir &= ~0x00010000) +#define I2C_READ ((iop->pdat & 0x00010000) != 0) +#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ + else iop->pdat &= ~0x00010000 +#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ + else iop->pdat &= ~0x00020000 +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_I2C_X + +/* EEPROM */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ + +/* I2C RTC */ +#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#else +#undef CONFIG_HARD_I2C +#undef CONFIG_SOFT_I2C +#define ADD_CMD_I2C 0 +#endif + +/* + * select serial console configuration + * + * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + * + * if CONFIG_CONS_NONE is defined, then the serial console routines must + * defined elsewhere (for example, on the cogent platform, there are serial + * ports on the motherboard which are used for the serial console - see + * cogent/cma101/serial.[ch]). + */ +#define CONFIG_CONS_ON_SMC /* define if console on SMC */ +#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else*/ +#ifdef CONFIG_82xx_CONS_SMC1 +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#endif +#ifdef CONFIG_82xx_CONS_SMC2 +#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ +#endif + +#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ +#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ +#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */ + +/* + * select ethernet configuration + * + * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then + * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 + * for FCC) + * + * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be + * defined elsewhere (as for the console), or CFG_CMD_NET must be removed + * from CONFIG_COMMANDS to remove support for networking. + * + * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the + * X.29 connector, and FCC2 is hardwired to the X.1 connector) + */ +#define CFG_FCC_ETHERNET + +#if defined(CFG_FCC_ETHERNET) +#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ +#else +#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */ +#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ +#endif + +#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1) + +/* + * - RX clk is CLK11 + * - TX clk is CLK12 + */ +# define CFG_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12) + +#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) + +/* + * - Rx-CLK is CLK13 + * - Tx-CLK is CLK14 + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + * - Enable Full Duplex in FSMR + */ +# define CFG_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) +# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) +# define CFG_CPMFCR_RAMTYPE 0 +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */ + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 2 /* Port C */ + +#if STK82xx_150 +#define CFG_MDIO_PIN 0x00008000 /* PC16 */ +#define CFG_MDC_PIN 0x00004000 /* PC17 */ +#endif + +#if STK82xx_100 +#define CFG_MDIO_PIN 0x00000002 /* PC30 */ +#define CFG_MDC_PIN 0x00000001 /* PC31 */ +#endif + +#if 1 +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN + +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN +#else +#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CFG_MDIO_PIN; iop->pdir = tmp;}) +#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CFG_MDIO_PIN; iop->pdir = tmp;}) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDIO_PIN; iop->pdat = tmp;}\ + else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDIO_PIN; iop->pdat = tmp;} + +#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CFG_MDC_PIN; iop->pdat = tmp;}\ + else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CFG_MDC_PIN; iop->pdat = tmp;} +#endif + +#define MIIDELAY udelay(1) + + +/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ +#define CONFIG_8260_CLKIN 66666666 /* in Hz */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_NAND | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + ADD_CMD_I2C | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_PCI | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if 0 +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x300000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_RESET_ADDRESS 0x40000104 /* "bad" address */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * CAN stuff + *----------------------------------------------------------------------- + */ +#define CFG_CAN_BASE 0x51000000 +#define CFG_CAN_SIZE 1 +#define CFG_CAN_BR ((CFG_CAN_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_UPMC |\ + BRx_V) + +#define CFG_CAN_OR (MEG_TO_AM(CFG_CAN_SIZE) |\ + ORxU_BI) + + +/* What should the base address of the main FLASH be and how big is + * it (in MBytes)? This must contain TEXT_BASE from board/tqm8272/config.mk + * The main FLASH is whichever is connected to *CS0. + */ +#define CFG_FLASH0_BASE 0x40000000 +#define CFG_FLASH0_SIZE 32 /* 32 MB */ + +/* Flash bank size (for preliminary settings) + */ +#define CFG_FLASH_SIZE CFG_FLASH0_SIZE + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_UPDATE_FLASH_SIZE + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND 0x20000 + +/* Where is the Hardwareinformation Block (from Monitor Sources) */ +#define MON_RES_LENGTH (0x0003FC00) +#define HWIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH) +#define HWIB_INFO_LEN 512 +#define CIB_INFO_START_ADDR (CFG_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN) +#define CIB_INFO_LEN 512 + +#define CFG_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000060 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *----------------------------------------------------------------------- + */ +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#define CFG_NAND_CS_DIST 0x80 +#define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 +#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x40 + +#define CFG_NAND_BR ((CFG_NAND0_BASE & BRx_BA_MSK) |\ + BRx_PS_8 |\ + BRx_MS_UPMB |\ + BRx_V) + +#define CFG_NAND_OR (MEG_TO_AM(CFG_NAND_SIZE) |\ + ORxU_BI |\ + ORxU_EHTR_8IDLE) + +#define CFG_NAND_SIZE 1 +#define CFG_NAND0_BASE 0x50000000 +#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) + +#define CFG_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 + +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ + CFG_NAND2_BASE, \ + CFG_NAND3_BASE, \ + } + +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr))) +#define WRITE_NAND_UPM(d, adr, off) do \ +{ \ + volatile unsigned char *addr = (unsigned char *) (adr + off); \ + WRITE_NAND(d, addr); \ +} while(0) + +#endif /* CFG_CMD_NAND */ + +#define CONFIG_PCI +#ifdef CONFIG_PCI +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_PCI_PNP +#define CONFIG_EEPRO100 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_PCI_SCAN_SHOW +#endif + +/*----------------------------------------------------------------------- + * Hard Reset Configuration Words + * + * if you change bits in the HRCW, you must also change the CFG_* + * defines for the various registers affected by the HRCW e.g. changing + * HRCW_DPPCxx requires you to also change CFG_SIUMCR. + */ +#if 0 +#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS) + +# define CFG_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111) +#else +#define CFG_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111) +#endif + +/* no slaves so just fill with zeros */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE CFG_FLASH0_BASE +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * HIDx - Hardware Implementation-dependent Registers 2-11 + *----------------------------------------------------------------------- + * HID0 also contains cache control - initially enable both caches and + * invalidate contents, then the final state leaves only the instruction + * cache enabled. Note that Power-On and Hard reset invalidate the caches, + * but Soft reset does not. + * + * HID1 has only read-only information - nothing to set. + */ +#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ + HID0_IFEM|HID0_ABE) +#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) +#define CFG_HID2 0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR RMR_CSRE + +/*----------------------------------------------------------------------- + * BCR - Bus Configuration 4-25 + *----------------------------------------------------------------------- + */ +#define CFG_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */ +#define BCR_APD01 0x10000000 +#define CFG_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */ + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 4-31 + *----------------------------------------------------------------------- + */ +#if defined(CONFIG_BOARD_GET_CPU_CLK_F) +#define CFG_SIUMCR_LOW (SIUMCR_DPPC00) +#define CFG_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE) +#else +#define CFG_SIUMCR (SIUMCR_DPPC00) +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 4-35 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) +#else +#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ + SYPCR_SWRI|SYPCR_SWP) +#endif /* CONFIG_WATCHDOG */ + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * SCCR - System Clock Control 9-8 + *----------------------------------------------------------------------- + * Ensure DFBRG is Divide by 16 + */ +#define CFG_SCCR SCCR_DFBRG01 + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * 2 60x UPMB 8 bit NAND + * 3 60x UPMC 8 bit CAN + * + */ + +/* Initialize SDRAM + */ +#undef CFG_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */ + +#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */ + +/* Minimum mask to separate preliminary + * address ranges for CS[0:2] + */ +#define CFG_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */ + +#define CFG_MPTPR 0x4000 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + * In fact, the address is rather configuration data presented to the SDRAM on + * its address lines. Because the address lines may be mux'ed externally either + * for 8 column or 9 column devices, some bits appear twice in the 8260's + * address: + * + * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length | + * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 | + * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 | + * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 | + * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 | + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 + +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ + ORxG_CSNT |\ + ORxG_ACS_DIV4 |\ + ORxG_SCY_8_CLK |\ + ORxG_TRLX) + +/* SDRAM on TQM8272 can have either 8 or 9 columns. + * The number affects configuration values. + */ + +/* Bank 1 - 60x bus SDRAM + */ +#define CFG_PSRT 0x20 /* Low Value */ +/* #define CFG_PSRT 0x10 Fast Value */ +#define CFG_LSRT 0x20 /* Local Bus */ +#ifndef CFG_RAMBOOT +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM CFG_OR1_8COL + +/* SDRAM initialization values for 8-column chips + */ +#define CFG_OR1_8COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A7 |\ + ORxS_NUMR_12) + +#define CFG_PSDMR_8COL (PSDMR_PBI |\ + PSDMR_SDAM_A15_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A8 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD |\ + PSDMR_CL_2) + + +/* SDRAM initialization values for 9-column chips + */ +#define CFG_OR1_9COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A5 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_9COL (PSDMR_PBI |\ + PSDMR_SDAM_A16_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A7 |\ + PSDMR_RFRC_7_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD |\ + PSDMR_CL_2) + +#define CFG_OR1_10COL ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ + ORxS_BPD_4 |\ + ORxS_ROWST_PBI1_A4 |\ + ORxS_NUMR_13) + +#define CFG_PSDMR_10COL (PSDMR_PBI |\ + PSDMR_SDAM_A17_IS_A5 |\ + PSDMR_BSMA_A12_A14 |\ + PSDMR_SDA10_PBI1_A4 |\ + PSDMR_RFRC_6_CLK |\ + PSDMR_PRETOACT_2W |\ + PSDMR_ACTTORW_2W |\ + PSDMR_LDOTOPRE_1C |\ + PSDMR_WRC_2C |\ + PSDMR_EAMUX |\ + PSDMR_BUFCMD |\ + PSDMR_CL_2) + +#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */ +#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */ +#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */ +#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */ +#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */ +#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */ + +#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */ +#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */ +#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */ +#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */ +#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */ +#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */ + +#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */ +#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */ +#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */ +#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */ +#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */ +#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */ + +#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */ +#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */ +#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */ +#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */ +#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */ +#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */ + +#endif /* CFG_RAMBOOT */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 4bbee97db..ed0357791 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -37,10 +37,11 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC83XX 1 /* MPC83XX family */ #define CONFIG_MPC834X 1 /* MPC834X specific */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_TQM834X 1 /* TQM834X board specific */ /* IMMR Base Addres Register, use Freescale default: 0xff400000 */ -#define CFG_IMMRBAR 0xff400000 +#define CFG_IMMR 0xff400000 /* System clock. Primary input clock when in PCI host mode */ #define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */ @@ -83,6 +84,7 @@ #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_BASE 0x80000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* FLASH size in MB */ /* buffered writes in the AMD chip set is not supported yet */ #undef CFG_FLASH_USE_BUFFER_WRITE @@ -197,14 +199,15 @@ extern int tqm834x_num_flash_banks; #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -#define CFG_NS16550_COM1 (CFG_IMMRBAR + 0x4500) -#define CFG_NS16550_COM2 (CFG_IMMRBAR + 0x4600) +#define CFG_NS16550_COM1 (CFG_IMMR + 0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR + 0x4600) /* * I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C #define CFG_I2C_SPEED 400000 /* I2C speed: 400KHz */ #define CFG_I2C_SLAVE 0x7F /* slave address */ #define CFG_I2C_OFFSET 0x3000 @@ -235,9 +238,9 @@ extern int tqm834x_num_flash_banks; #define CONFIG_MII #define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMRBAR + CFG_TSEC1_OFFSET) +#define CFG_TSEC1 (CFG_IMMR + CFG_TSEC1_OFFSET) #define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMRBAR + CFG_TSEC2_OFFSET) +#define CFG_TSEC2 (CFG_IMMR + CFG_TSEC2_OFFSET) #if defined(CONFIG_TSEC_ENET) @@ -460,8 +463,8 @@ extern int tqm834x_num_flash_banks; #endif /* IMMRBAR */ -#define CFG_IBAT6L (CFG_IMMRBAR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_IBAT6U (CFG_IMMRBAR | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_IBAT6L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT6U (CFG_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) /* FLASH */ #define CFG_IBAT7L (CFG_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) diff --git a/include/configs/acadia.h b/include/configs/acadia.h new file mode 100644 index 000000000..9e02ca31b --- /dev/null +++ b/include/configs/acadia.h @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * acadia.h - configuration for AMCC Acadia (405EZ) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CONFIG_NO_SERIAL_EEPROM +/*#undef CONFIG_NO_SERIAL_EEPROM*/ + +#ifdef CONFIG_NO_SERIAL_EEPROM + +/*---------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 66MHz input clock to the 405EZ. + *---------------------------------------------------------------------------*/ +/* #define PLLMR0_100_100_12 */ +#define PLLMR0_200_133_66 +/* #define PLLMR0_266_160_80 */ +/* #define PLLMR0_333_166_83 */ +#endif + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ + +/* + * Define here the location of the environment variables (FLASH). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else + #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=acadia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=acadia/uImage\0" \ + "kernel_addr=fff10000\0" \ + "ramdisk_addr=fff20000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 acadia/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "kozio=bootm ffc60000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#if 0 /* test-only */ +#define TEST_ONLY_NAND +#endif + +#ifdef TEST_ONLY_NAND +#define CMD_NAND CFG_CMD_NAND +#else +#define CMD_NAND 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef TEST_ONLY_NAND +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define CFG_NAND 0xd0000000 +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (Flash) initialization */ +#define CFG_EBC_PB0AP 0x03337200 +#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ + +/* Memory Bank 1 (CRAM) initialization */ +#define CFG_EBC_PB1AP 0x030400c0 +#define CFG_EBC_PB1CR 0x000bc000 + +/* Memory Bank 2 (CRAM) initialization */ +#define CFG_EBC_PB2AP 0x030400c0 +#define CFG_EBC_PB2CR 0x020bc000 + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) + +/* Memory Bank 4 (CPLD) initialization */ +#define CFG_EBC_PB4AP 0x04006000 +#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ + +#define CFG_EBC_CFG 0xf8400000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_0 setup (PPC405EZ specific) + * + * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs + * GPIO0[4] - External Bus Controller Hold Input + * GPIO0[5] - External Bus Controller Priority Input + * GPIO0[6] - External Bus Controller HLDA Output + * GPIO0[7] - External Bus Controller Bus Request Output + * GPIO0[8] - CRAM Clk Output + * GPIO0[9] - External Bus Controller Ready Input + * GPIO0[10] - CRAM Adv Output + * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled + * GPIO0[25] - External DMA Request Input + * GPIO0[26] - External DMA EOT I/O + * GPIO0[25] - External DMA Ack_n Output + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[28-30] - Trace Outputs / PWM Inputs + * GPIO0[31] - PWM_8 I/O + */ +#define CFG_GPIO0_TCR 0xC0000000 +#define CFG_GPIO0_OSRL 0x50000000 +#define CFG_GPIO0_OSRH 0x00000055 +#define CFG_GPIO0_ISR1L 0x00000000 +#define CFG_GPIO0_ISR1H 0x00000055 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TSRH 0x00000055 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_1 setup (PPC405EZ specific) + * + * GPIO1[0-6] - PWM_9 to PWM_15 I/O + * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input + * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input + * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input + * GPIO1[10-12] - UART0 Control Inputs + * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input + * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output + * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input + * GPIO1[16] - SPI_SS_1_N Output + * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs + */ +#define CFG_GPIO1_OSRH 0x55455555 +#define CFG_GPIO1_OSRL 0x40000110 +#define CFG_GPIO1_ISR1H 0x00000000 +#define CFG_GPIO1_ISR1L 0x15555445 +#define CFG_GPIO1_TSRH 0x00000000 +#define CFG_GPIO1_TSRL 0x00000000 +#define CFG_GPIO1_TCR 0xFFFF8014 + +/*----------------------------------------------------------------------- + * EPLD Regs. + */ +#define EPLD_BASE 0x80000000 +#define EPLD_ETHRSTBOOT 0x10 +#define EPLD_CTRL 0x14 +#define EPLD_MUXOE 0x16 + +/* + * State definations + */ +#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ +#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ +#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ +#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ +#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ +#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ +#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h new file mode 100644 index 000000000..67f62d3df --- /dev/null +++ b/include/configs/alpr.h @@ -0,0 +1,365 @@ +/* + * (C) Copyright 2006-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ALPR 1 /* Board is ebony */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + + +#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000) +#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ +#undef CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ + +/*----------------------------------------------------------------------- + * I2C EEPROM (PCF8594C) + *----------------------------------------------------------------------*/ +#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */ + /* 8 byte page write mode using */ + /* last 3 bits of the address */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run kernelx\" to boot the system;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth3\0" \ + "hostname=alpr\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath} ${init}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \ + "mem=193M\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/projects/alpr/nfs_root\0" \ + "bootfile=/alpr/uImage\0" \ + "kernel_addr=fff00000\0" \ + "ramdisk_addr=fff10000\0" \ + "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "ethprime=ppc_4xx_eth3\0" \ + "ethact=ppc_4xx_eth3\0" \ + "autoload=no\0" \ + "ipconfig=dhcp;setenv serverip 11.0.0.152\0" \ + "load_fpga=fpga load 0 ffe00000 10dd9a\0" \ + "mtdargs=setenv bootargs root=/dev/mtdblock6 rw " \ + "rootfstype=jffs2 init=/sbin/init\0" \ + "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\ + ";bootm 200000\0" \ + "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \ + "addtty;bootm 200000\0" \ + "kernel1=setenv actkernel 'kernel1';run load_fpga " \ + "kernel1_mtd\0" \ + "kernel2=setenv actkernel 'kernel2';run load_fpga " \ + "kernel2_mtd\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run kernel2" + +#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */ +#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */ +#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */ +#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */ +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_M88E1111_PHY 1 /* needed for PHY specific setup*/ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_FPGA | \ + CFG_CMD_NAND | \ + CFG_CMD_REGINFO) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 /* Enable more extensive memtest*/ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ +#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/*----------------------------------------------------------------------- + * FPGA stuff + *-----------------------------------------------------------------------*/ +#define CONFIG_FPGA CFG_ALTERA_CYCLON2 +#define CFG_FPGA_CHECK_CTRLC +#define CFG_FPGA_PROG_FEEDBACK +#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in + Reihe geschaltet -> sollte gehen, + aufpassen mit Datasize ist jetzt + halt doppelt so gross ... Seite 306 + ist das mit den multiple Device in PS + Mode erklaert ...*/ + +/* FPGA program pin configuration */ +#define CFG_GPIO_CLK 18 /* FPGA clk pin (cpu output) */ +#define CFG_GPIO_DATA 19 /* FPGA data pin (cpu output) */ +#define CFG_GPIO_STATUS 20 /* FPGA status pin (cpu input) */ +#define CFG_GPIO_CONFIG 21 /* FPGA CONFIG pin (cpu output) */ +#define CFG_GPIO_CON_DON 22 /* FPGA CONFIG_DONE pin (cpu input) */ + +#define CFG_GPIO_SEL_DPR 14 /* cpu output */ +#define CFG_GPIO_SEL_AVR 15 /* cpu output */ +#define CFG_GPIO_PROG_EN 23 /* cpu output */ + +/*----------------------------------------------------------------------- + * Definitions for GPIO setup + *-----------------------------------------------------------------------*/ +#define CFG_GPIO_SHUTDOWN (0x80000000 >> 6) +#define CFG_GPIO_SSD_EMPTY (0x80000000 >> 9) +#define CFG_GPIO_EREADY (0x80000000 >> 26) +#define CFG_GPIO_REV0 (0x80000000 >> 14) +#define CFG_GPIO_REV1 (0x80000000 >> 15) + +/*----------------------------------------------------------------------- + * NAND-FLASH stuff + *-----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 4 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ +#define CFG_NAND_BASE_LIST { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \ + CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 } +#define CFG_NAND_QUIET_TEST 1 /* don't warn upon unknown NAND flash */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x92015480 +#define CFG_EBC_PB0CR (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */ + +/* Memory Bank 1 (NAND-FLASH) initialization */ +#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */ +#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 4961011b5..bcc736ceb 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -257,6 +257,7 @@ "bootfile=/tftpboot/bamboo/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/bamboo/u-boot.bin\0" \ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ "cp.b 100000 fffa0000 60000;" \ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h new file mode 100644 index 000000000..65dfc8155 --- /dev/null +++ b/include/configs/bf533-ezkit.h @@ -0,0 +1,228 @@ +/* + * U-boot - Configuration file for BF533 EZKIT board + */ + +#ifndef __CONFIG_EZKIT533_H__ +#define __CONFIG_EZKIT533_H__ + +#define CONFIG_BAUDRATE 57600 +#define CONFIG_STAMP 1 + +#define CONFIG_BOOTDELAY 5 +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CONFIG_BOOTCOMMAND "tftp $(loadaddr) linux" +/* #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" */ + +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20310300 + +#if 0 +#define CONFIG_MII +#define CFG_DISCOVER_PHY +#endif + +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF533_BYPASS_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF531 0x31 +#define ADSP_BF532 0x32 +#define ADSP_BF533 0x33 +#define BFIN_CPU ADSP_BF533 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 27000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 22 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CONFIG_LOADS_ECHO 1 + + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DATE) +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024 * 1024) /* 1 ... 31 MB in DRAM */ +#define CFG_LOAD_ADDR 0x01000000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_FLASH0_BASE 0x20000000 +#define CFG_FLASH1_BASE 0x20200000 +#define CFG_FLASH2_BASE 0x20280000 +#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 40 +#define FLASH_SIZE 0x220000 +#define CFG_FLASH_SIZE 0x220000 + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h new file mode 100644 index 000000000..79a1404a4 --- /dev/null +++ b/include/configs/bf533-stamp.h @@ -0,0 +1,467 @@ +/* + * U-boot - Configuration file for BF533 STAMP board + */ + +#ifndef __CONFIG_STAMP_H__ +#define __CONFIG_STAMP_H__ + +#define CONFIG_STAMP 1 +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BF533 1 +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF533_BYPASS_BOOT +/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */ + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF531 0x31 +#define ADSP_BF532 0x32 +#define ADSP_BF533 0x33 +#define BFIN_CPU ADSP_BF533 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* + * Stringize definitions - needed for environmental settings + */ +#define STRINGIZE2(x) #x +#define STRINGIZE(x) STRINGIZE2(x) + +/* + * Board settings + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x20300300 + +/* FLASH/ETHERNET uses the same address range */ +#define SHARED_RESOURCES 1 + +/* Is I2C bit-banged? */ +#define CONFIG_SOFT_I2C 1 + +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF3 +#define PF_SDA PF2 + +/* + * Video splash screen support + */ +#define CONFIG_VIDEO 0 + +#define CONFIG_VDSP 1 + +/* + * Clock settings + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 11059200 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 36 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_SPI_BAUD_INITBLOCK 4 +#endif + +/* + * Network settings + */ + +#if (CONFIG_DRIVER_SMC91111) +#if 0 +#define CONFIG_MII +#endif + +/* network support */ +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME STAMP +#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs + +/* To remove hardcoding and enable MAC storage in EEPROM */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ +#endif /* CONFIG_DRIVER_SMC91111 */ + +/* + * Flash settings + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET + +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */ +#endif + +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +#define ENV_IS_EMBEDDED + +#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ +#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 11 + +/* + * following timeouts shall be used once the + * Flash real protection is enabled + */ +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_MEMTEST_START 0x00000000 /* memtest works on */ +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#endif + +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024) +#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1) +#define CONFIG_LOADADDR 0x01000000 + +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000) +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +/* Check to make sure everything fits in SDRAM */ +#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE) + #error Memory Map does not fit into configuration +#endif + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000) +#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */ +#else +#undef CONFIG_SPI_FLASH_FAST_READ +#endif +#endif + +/* + * Command settings + */ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */ +#endif + +/* configuration lookup from the BOOTP/DHCP server, */ +/* but not try to load any image using TFTP */ + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CONFIG_BOOTCOMMAND "run ramboot" +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000" +#endif + +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" + +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) + +#else +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE) +#endif + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + " +#endif + +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "eeprom write $(loadaddr) 0x0 $(filesize);\0"\ + "" +#endif + +#ifdef CONFIG_SOFT_I2C +#if (!CONFIG_SOFT_I2C) +#undef CONFIG_SOFT_I2C +#endif +#endif + +#if (CONFIG_SOFT_I2C) +#define CONFIG_COMMANDS2 CFG_CMD_I2C +#else +#define CONFIG_COMMANDS2 0 +#endif /* CONFIG_SOFT_I2C */ + +#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP) +#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2) +#endif + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Console settings + */ + +#define CONFIG_BAUDRATE 57600 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#if (BFIN_BOOT_MODE == BF533_SPI_BOOT) +#if (BFIN_CPU == ADSP_BF531) +#define CFG_PROMPT "serial_bf531> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF532) +#define CFG_PROMPT "serial_bf532> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "serial_bf533> " /* Monitor Command Prompt */ +#endif +#else +#if (BFIN_CPU == ADSP_BF531) +#define CFG_PROMPT "bf531> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF532) +#define CFG_PROMPT "bf532> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "bf533> " /* Monitor Command Prompt */ +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * I2C settings + * By default PF2 is used as SDA and PF3 as SCL on the Stamp board + */ +#if (CONFIG_SOFT_I2C) + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE +#endif /* CONFIG_SOFT_I2C */ + +/* + * Compact Flash settings + */ + +/* Enabled below option for CF support */ +/* #define CONFIG_STAMP_CF 1 */ + +#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) + +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_DOS_PARTITION 1 +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0x20200000 +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ + +#define CFG_ATA_STRIDE 2 +#endif + +/* + * Miscellaneous configurable options + */ + +#define CFG_HZ 1000 /* 1ms time tick */ + +#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */ + +#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ + +#define CONFIG_SPI + +#ifdef CONFIG_VIDEO +#if (CONFIG_VIDEO) +#define CONFIG_SPLASH_SCREEN 1 +#define CONFIG_SILENT_CONSOLE 1 +#else +#undef CONFIG_VIDEO +#endif +#endif + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ + +/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ +/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ + B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) +#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ + B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) +*/ +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0xBBC3BBC3 +#define AMBCTL1VAL 0x99B39983 +#define CF_AMBCTL1VAL 0x99B3ffc2 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h new file mode 100644 index 000000000..f6755acf6 --- /dev/null +++ b/include/configs/bf537-stamp.h @@ -0,0 +1,502 @@ +/* + * U-boot - Configuration file for BF537 STAMP board + */ + +#ifndef __CONFIG_BF537_H__ +#define __CONFIG_BF537_H__ + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BAUDRATE 57600 +/* Set default serial console for bf537 */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_BF537 1 +#define CONFIG_BOOTDELAY 5 +/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/ +/*#define CONFIG_BF537_STAMP_LEDCMD 1*/ + +/* + * Boot Mode Set + * Blackfin can support several boot modes + */ +#define BF537_BYPASS_BOOT 0x0011 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */ +#define BF537_PARA_BOOT 0x0012 /* Bootmode 1: Boot from 8-bit or 16-bit flash */ +#define BF537_SPI_MASTER_BOOT 0x0014 /* Bootmode 3: SPI master mode boot from SPI flash */ +#define BF537_SPI_SLAVE_BOOT 0x0015 /* Bootmode 4: SPI slave mode boot from SPI flash */ +#define BF537_TWI_MASTER_BOOT 0x0016 /* Bootmode 5: TWI master mode boot from EEPROM */ +#define BF537_TWI_SLAVE_BOOT 0x0017 /* Bootmode 6: TWI slave mode boot from EEPROM */ +#define BF537_UART_BOOT 0x0018 /* Bootmode 7: UART slave mdoe boot via UART host */ +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF537_BYPASS_BOOT + +#define CONFIG_PANIC_HANG 1 + +#define ADSP_BF534 0x34 +#define ADSP_BF536 0x36 +#define ADSP_BF537 0x37 +#define BFIN_CPU ADSP_BF537 + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define if want to do post memory test */ +#undef CONFIG_POST_TEST + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +#define CONFIG_RTC_BFIN 1 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 25000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL*/ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 20 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CONFIG_SPI_BAUD_INITBLOCK 4 +#endif + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000) +#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */ +#else +#undef CONFIG_SPI_FLASH_FAST_READ +#endif +#endif + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC32M8A2_75 1 + +#define CONFIG_LOADS_ECHO 1 + +/* + * rarpb, bootp or dhcp commands will perform only a + * configuration lookup from the BOOTP/DHCP server + * but not try to load any image using TFTP + */ +#define CFG_AUTOLOAD "no" + +/* + * Network Settings + */ +/* network support */ +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME BF537 +#endif + +#define CONFIG_ROOTPATH /romfs +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ +/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */ + +#define CFG_LONGHELP 1 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) && defined(CONFIG_POST_TEST) +/* POST support */ +#define CONFIG_POST ( CFG_POST_MEMORY | \ + CFG_POST_UART | \ + CFG_POST_FLASH | \ + CFG_POST_ETHER | \ + CFG_POST_LED | \ + CFG_POST_BUTTON) +#else +#undef CONFIG_POST +#endif + +#ifdef CONFIG_POST +#define CFG_CMD_POST_DIAG CFG_CMD_DIAG +#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ +#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ +#else +#define CFG_CMD_POST_DIAG 0 +#endif + +/* CF-CARD IDE-HDD Support */ + +/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */ +/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */ +/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */ + +#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE) +# define CONFIG_BFIN_IDE 1 +# define ADD_IDE_CMD CFG_CMD_IDE +#else +# define ADD_IDE_CMD 0 +#endif + +/*#define CONFIG_BF537_NAND */ /* Add nand flash support */ + +#ifdef CONFIG_BF537_NAND +# define ADD_NAND_CMD CFG_CMD_NAND +#else +# define ADD_NAND_CMD 0 +#endif + +#define CONFIG_NETCONSOLE 1 +#define CONFIG_NET_MULTI 1 + +#if (BFIN_CPU == ADSP_BF534) +#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#else +#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING) +#endif + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) +#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DHCP | \ + ADD_IDE_CMD | \ + ADD_NAND_CMD | \ + CFG_CMD_POST_DIAG | \ + CFG_CMD_DATE) +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_EEPROM | \ + ADD_IDE_CMD | \ + CFG_CMD_DATE) +#endif + +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" +#define CONFIG_LOADADDR 0x1000000 + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.bin;" \ + "protect off 0x20000000 0x2007FFFF;" \ + "erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (BFIN_CPU != ADSP_BF534) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux;" \ + "run ramargs;run addip;bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux;" \ + "run nfsargs;run addip;bootelf\0" \ + "flashboot=bootm 0x20100000\0" \ + "update=tftpboot $(loadaddr) u-boot.ldr;" \ + "eeprom write $(loadaddr) 0x0 $(filesize);\0" \ + "" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif +#endif + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#if (BFIN_CPU == ADSP_BF534) +#define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF536) +#define CFG_PROMPT "serial_bf536> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "serial_bf537> " /* Monitor Command Prompt */ +#endif +#else +#if (BFIN_CPU == ADSP_BF534) +#define CFG_PROMPT "bf534> " /* Monitor Command Prompt */ +#elif (BFIN_CPU == ADSP_BF536) +#define CFG_PROMPT "bf536> " /* Monitor Command Prompt */ +#else +#define CFG_PROMPT "bf537> " /* Monitor Command Prompt */ +#endif +#endif + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024) +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x0 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_FLASH_BASE 0x20000000 + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) + +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_UART_BOOT) +/* for bf537-stamp, usrt boot mode still store env in flash */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0x20004000 +#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) +#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) +#define CFG_ENV_IS_IN_EEPROM 1 +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */ +#endif +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */ +/* #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) */ +#define ENV_IS_EMBEDDED +/* #endif */ + +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 15 + +#define CONFIG_SPI + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#define POLL_MODE 1 +#define FLASH_TOT_SECT 71 +#define FLASH_SIZE 0x400000 +#define CFG_FLASH_SIZE 0x400000 + +/* + * Board NAND Infomation + */ + +#define CFG_NAND_ADDR 0x20212000 +#define CFG_NAND_BASE CFG_NAND_ADDR +#define CFG_MAX_NAND_DEVICE 1 +#define SECTORSIZE 512 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define BFIN_NAND_READY PF3 + +#define NAND_WAIT_READY(nand) \ + do { \ + int timeout = 0; \ + while(!(*pPORTFIO & PF3)) \ + if (timeout++ > 100000) \ + break; \ + } while (0) + +#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */ +#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */ + +#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0) +#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0) +#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0) +#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr)) + +/* + * Initialize PSD4256 registers for using I2C + */ +#define CONFIG_MISC_INIT_R + +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* + * I2C settings + * By default PF1 is used as SDA and PF0 as SCL on the Stamp board + */ +/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */ +#define CONFIG_HARD_I2C 1 /* I2C TWI */ +#if defined CONFIG_HARD_I2C +#define CONFIG_TWICLK_KHZ 50 +#endif + +#if defined CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PF_SCL PF0 +#define PF_SDA PF1 + +#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") +#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") +#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") +#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") +#define I2C_SDA(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SDA; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SDA; \ + asm("ssync;"); \ + } +#define I2C_SCL(bit) if(bit) { \ + *pFIO_FLAG_S = PF_SCL; \ + asm("ssync;"); \ + } \ + else { \ + *pFIO_FLAG_C = PF_SCL; \ + asm("ssync;"); \ + } +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ +#endif + +#define CFG_I2C_SPEED 50000 +#define CFG_I2C_SLAVE 0xFE + +/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ +/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) +#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ + ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) +#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ + B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) +*/ + +#define AMGCTLVAL 0xFF +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#define CONFIG_VDSP 1 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#if defined(CONFIG_BFIN_IDE) + +#define CONFIG_DOS_PARTITION 1 +/* + * IDE/ATA stuff + */ +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#undef AMBCTL1VAL +#define AMBCTL1VAL 0xFFC3FFC3 + +#define CONFIG_CF_ATASEL_DIS 0x20311800 +#define CONFIG_CF_ATASEL_ENA 0x20311802 + +#if defined(CONFIG_BFIN_TRUE_IDE) +/* + * Note that these settings aren't for the most part used in include/ata.h + * when all of the ATA registers are setup + */ +#define CFG_ATA_BASE_ADDR 0x2031C000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */ +#endif /* CONFIG_BFIN_TRUE_IDE */ + +#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */ +#define CFG_ATA_BASE_ADDR 0x20211800 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */ +#endif /* CONFIG_BFIN_CF_IDE */ + +#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */ +#define CFG_ATA_BASE_ADDR 0x20314000 +#define CFG_ATA_IDE0_OFFSET 0x0000 +#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ +#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ +#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */ +#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */ + +#undef CONFIG_SCLK_DIV +#define CONFIG_SCLK_DIV 8 +#endif /* CONFIG_BFIN_HDD_IDE */ + +#endif /*CONFIG_BFIN_IDE */ + +#endif diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h new file mode 100644 index 000000000..8d826faaa --- /dev/null +++ b/include/configs/bf561-ezkit.h @@ -0,0 +1,244 @@ +/* + * U-boot - Configuration file for BF561 EZKIT board + */ + +#ifndef __CONFIG_EZKIT561_H__ +#define __CONFIG_EZKIT561_H__ + +#define CONFIG_VDSP 1 +#define CONFIG_BF561 1 + +#define CFG_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 +#define CONFIG_BAUDRATE 57600 +/* Set default serial console for bf537 */ +#define CONFIG_UART_CONSOLE 0 +#define CONFIG_EZKIT561 1 +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_PANIC_HANG 1 + +/* +* Boot Mode Set +* Blackfin can support several boot modes +*/ +#define BF561_BYPASS_BOOT 0x21 +#define BF561_PARA_BOOT 0x22 +#define BF561_SPI_BOOT 0x24 +/* Define the boot mode */ +#define BFIN_BOOT_MODE BF561_BYPASS_BOOT + +/* This sets the default state of the cache on U-Boot's boot */ +#define CONFIG_ICACHE_ON +#define CONFIG_DCACHE_ON + +/* Define where the uboot will be loaded by on-chip boot rom */ +#define APP_ENTRY 0x00001000 + +/* + * Stringize definitions - needed for environmental settings + */ +#define STRINGIZE2(x) #x +#define STRINGIZE(x) STRINGIZE2(x) + +/* + * Board settings + */ +#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_SMC91111_BASE 0x2C010300 +#define CONFIG_ASYNC_EBIU_BASE CONFIG_SMC91111_BASE & ~(4*1024*1024) +#define CONFIG_SMC_USE_32_BIT 1 +#define CONFIG_MISC_INIT_R 1 + +/* + * Clock settings + */ + +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 30000000 +/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ +/* 1=CLKIN/2 */ +#define CONFIG_CLKIN_HALF 0 +/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ +/* 1=bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* CONFIG_VCO_MULT controls what the multiplier of the PLL is */ +/* Values can range from 1-64 */ +#define CONFIG_VCO_MULT 20 +/* CONFIG_CCLK_DIV controls what the core clock divider is */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */ +/* Values can range from 2-65535 */ +/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */ +#define CONFIG_SPI_BAUD 2 +#define CONFIG_SPI_BAUD_INITBLOCK 4 + +/* + * Network settings + */ +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_IPADDR 192.168.0.15 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_GATEWAYIP 192.168.0.1 +#define CONFIG_SERVERIP 192.168.0.2 +#define CONFIG_HOSTNAME ezkit561 +#define CONFIG_ROOTPATH /arm-cross-build/BF561/uClinux-dist/romfs +#endif /* CONFIG_DRIVER_SMC91111 */ + +/* + * Flash settings + */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_FLASH_BASE 0x20000000 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 135 /* max number of sectors on one chip */ +#define CFG_ENV_ADDR 0x20020000 +#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ +/* JFFS Partition offset set */ +#define CFG_JFFS2_FIRST_BANK 0 +#define CFG_JFFS2_NUM_BANKS 1 +/* 512k reserved for u-boot */ +#define CFG_JFFS2_FIRST_SECTOR 8 + +/* + * SDRAM settings & memory map + */ + +#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */ +#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ +#define CONFIG_MEM_MT48LC16M16A2TG_75 1 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) + +#define CFG_MEMTEST_START 0x0 /* memtest works on */ +#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */ + +#define CONFIG_LOADADDR 0x01000000 /* default load address */ +#define CFG_LOAD_ADDR CONFIG_LOADADDR +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) + +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) + +#define CFG_GBL_DATA_SIZE 0x4000 +#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ + +#if ( CONFIG_CLKIN_HALF == 0 ) +#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) +#else +#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) +#endif + +#if (CONFIG_PLL_BYPASS == 0) +#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) +#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) +#else +#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ +#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ +#endif + +/* + * Command settings + */ + +#define CFG_AUTOLOAD "no" /* rarpb, bootp, dhcp commands will */ + /* only perform a configuration */ + /* lookup from the BOOTP/DHCP server */ + /* but not try to load any image */ + /* using TFTP */ +#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, */ + /* currently its disabled */ +#define CONFIG_BOOTCOMMAND "run ramboot" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" + +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_DHCP) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ + "$(rootpath) console=ttyBF0,57600\0" \ + "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):eth0:off\0" \ + "ramboot=tftpboot $(loadaddr) linux; " \ + "run ramargs; run addip; bootelf\0" \ + "nfsboot=tftpboot $(loadaddr) linux; " \ + "run nfsargs; run addip; bootelf\0" \ + "update=tftpboot $(loadaddr) u-boot.bin; " \ + "protect off 0x20000000 0x2003FFFF; " \ + "erase 0x20000000 0x2003FFFF; " \ + "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ + "" +#else +#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ + CFG_CMD_ELF | \ + CFG_CMD_CACHE | \ + CFG_CMD_JFFS2) +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ + "flashboot=bootm 0x20100000\0" \ + "" +#endif + +#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Console settings + */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_LOADS_ECHO 1 + +/* + * Miscellaneous configurable options + */ +#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ +#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ + +/* + * FLASH organization and environment definitions + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define AMGCTLVAL 0x3F +#define AMBCTL0VAL 0x7BB07BB0 +#define AMBCTL1VAL 0xFFC27BB0 + +#ifdef CONFIG_VDSP +#define ET_EXEC_VDSP 0x8 +#define SHT_STRTAB_VDSP 0x1 +#define ELFSHDRSIZE_VDSP 0x2C +#define VDSP_ENTRY_ADDR 0xFFA00000 +#endif + +#endif /* __CONFIG_EZKIT561_H__ */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index a66cdc395..10c481431 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -106,6 +106,7 @@ "bootfile=/tftpboot/bubinga/uImage\0" \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff90000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/bubinga/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index d8882ea31..a42319b09 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -133,8 +133,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ /*----------------------------------------------------------------------- * I2C @@ -177,6 +178,7 @@ "bootfile=/tftpboot/ebony/uImage\0" \ "kernel_addr=ff800000\0" \ "ramdisk_addr=ff810000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/ebony/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/ezkit533.h b/include/configs/ezkit533.h deleted file mode 100644 index 5eda6732c..000000000 --- a/include/configs/ezkit533.h +++ /dev/null @@ -1,188 +0,0 @@ -#ifndef __CONFIG_EZKIT533_H__ -#define __CONFIG_EZKIT533_H__ - -#define CFG_LONGHELP 1 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_STAMP 1 -#define CONFIG_BOOTDELAY 5 - -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20310300 -#if 0 -#define CONFIG_MII -#define CFG_DISCOVER_PHY -#endif - -#define CONFIG_RTC_BF533 1 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ - -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 27000000 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 22 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 5 - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -#define CONFIG_MEM_SIZE 32 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC16M16A2TG_75 1 - -#define CONFIG_LOADS_ECHO 1 - - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off" - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -#define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x01F00000 /* 1 ... 31 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x02000000 -#define CFG_FLASH_BASE 0x20000000 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_SIZE 0x4000 -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) - -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -#define CFG_FLASH0_BASE 0x20000000 -#define CFG_FLASH1_BASE 0x20200000 -#define CFG_FLASH2_BASE 0x20280000 -#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ - -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ - -/* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 - - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -#define POLL_MODE 1 -#define FLASH_TOT_SECT 40 -#define FLASH_SIZE 0x220000 -#define CFG_FLASH_SIZE 0x220000 - -/* - * Initialize PSD4256 registers for using I2C - */ -#define CONFIG_MISC_INIT_R - -/* - * I2C settings - * By default PF1 is used as SDA and PF0 as SCL on the Stamp board - */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE - - -#define __ADSPLPBLACKFIN__ 1 -#define __ADSPBF533__ 1 - -/* 0xFF, 0x7BB07BB0, 0x22547BB0 */ -/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ - ~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN) -#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \ - B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN) -*/ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0x7BB07BB0 -#define AMBCTL1VAL 0xFFC27BB0 - -#define CONFIG_VDSP 1 - -#ifdef CONFIG_VDSP -#define ET_EXEC_VDSP 0x8 -#define SHT_STRTAB_VDSP 0x1 -#define ELFSHDRSIZE_VDSP 0x2C -#define VDSP_ENTRY_ADDR 0xFFA00000 -#endif - -#endif diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index cfaf15322..095b5f6dc 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -210,6 +210,7 @@ */ #define CONFIG_MPC5xxx_FEC 1 #define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 /* MII PHY management */ /* * GPIO configuration diff --git a/include/configs/idmr.h b/include/configs/idmr.h new file mode 100644 index 000000000..b1dbe2ccb --- /dev/null +++ b/include/configs/idmr.h @@ -0,0 +1,213 @@ +/* + * Configuration settings for the iDMR board + * + * Based on MC5272C3, r5200 and M5271EVB board configs + * (C) Copyright 2006 Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * (C) Copyright 2006 Lab X Technologies <zachary.landau@labxtechnologies.com> + * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IDMR_H +#define _IDMR_H + + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5271 /* define processor type */ +#define CONFIG_IDMR /* define board type */ + +#undef CONFIG_WATCHDOG /* disable watchdog */ + +/* + * Default environment settings + */ +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BAUDRATE 19200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } +#define CONFIG_ETHADDR 00:06:3b:01:41:55 +#define CONFIG_ETHPRIME +#define CONFIG_IPADDR 192.168.30.1 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_ROOTPATH +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.0.0 +#define CONFIG_HOSTNAME idmr +#define CONFIG_BOOTFILE /tftpboot/idmr/uImage +#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root " \ + "filesystem over NFS; echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "ethact=FEC ETHERNET\0" \ + "update=prot off ff800000 ff81ffff; era ff800000 ff81ffff; " \ + "cp.b 200000 ff800000 $(filesize);" \ + "prot on ff800000 ff81ffff\0" \ + "load=tftp 200000 $(u-boot)\0" \ + "u-boot=/tftpboot/idmr/u-boot.bin\0" \ + "" + +/* + * Commands' definition + */ +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ + CFG_CMD_PING | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_NET) & \ + ~(CFG_CMD_LOADS | \ + CFG_CMD_LOADB)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ + +/* + * Configuration for environment, which occupies third sector in flash. + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_ADDR 0xff820000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH +#else /* CONFIG_MONITOR_IS_IN_RAM */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH +#endif /* !CONFIG_MONITOR_IS_IN_RAM */ + +#define CFG_PROMPT "=> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x00100000 + +#define CFG_MEMTEST_START 0x400 +#define CFG_MEMTEST_END 0x380000 + +#define CFG_HZ (50000000 / 64) +#define CFG_CLK 100000000 + +#define CFG_MBAR 0x40000000 /* Register Base Addrs */ + +/* + * Ethernet + */ +#define FEC_ENET +#define CONFIG_NET_RETRY_COUNT 5 +#define CFG_ENET_BD_BASE 0x480000 +#define CFG_DISCOVER_PHY 1 +#define CONFIG_MII 1 + +/* + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ +#define CFG_FLASH_BASE 0xff800000 + +#ifdef CONFIG_MONITOR_IS_IN_RAM +#define CFG_MONITOR_BASE 0x20000 +#else /* !CONFIG_MONITOR_IS_IN_RAM */ +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#endif /* CONFIG_MONITOR_IS_IN_RAM */ + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN (64*1024) + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 1000 + +#define CFG_FLASH_SIZE 0x800000 +/* + * #define CFG_FLASH_USE_BUFFER_WRITE 1 + */ + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 16 + +/* Port configuration */ +#define CFG_FECI2C 0xF0 + + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=idmr-0" + +#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ + "64k(env)," \ + "640k(kernel)," \ + "2m(rootfs)," \ + "-(user)"; + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#error MII commands don't work on iDMR board and sholud not be enabled. +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ + +#endif /* _IDMR_H */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h new file mode 100644 index 000000000..5b97526fc --- /dev/null +++ b/include/configs/jupiter.h @@ -0,0 +1,291 @@ +/* + * (C) Copyright 2007 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* especially an MPC5200 */ +#define CONFIG_JUPITER 1 /* ... on Jupiter board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_BOARD_EARLY_INIT_R 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* + * PCI Mapping: + * 0x40000000 - 0x4fffffff - PCI Memory + * 0x50000000 - 0x50ffffff - PCI IO Space + */ +/*#define CONFIG_PCI */ + +#if defined(CONFIG_PCI) +#define CONFIG_PCI_PNP 1 +#define CONFIG_PCI_SCAN_SHOW 1 + +#define CONFIG_PCI_MEM_BUS 0x40000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x50000000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0x01000000 +#define ADD_PCI_CMD CFG_CMD_PCI +#endif + +#define CFG_XLB_PIPELINING 1 + +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_NFS | \ + CFG_CMD_SNTP) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "addcons=setenv bootargs ${bootargs} console=${contyp}," \ + "${baudrate}\0" \ + "contyp=ttyS0\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "bootfile=/tftpboot/jupiter/uImage\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ + +#if 0 +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 8) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" +#endif + +#if 0 +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70 +#endif + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 0x01000000 + +#define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (TEXT_BASE + 0x40000) /* third sector */ + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CFG_UPDATE_FLASH_SIZE 1 +#define CFG_FLASH_USE_BUFFER_WRITE 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_OVERWRITE 1 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x10000004 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CFG_ALT_MEMTEST 1 + +#define CFG_LOAD_ADDR 0x200000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00047801 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +#endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h new file mode 100644 index 000000000..1606d0da1 --- /dev/null +++ b/include/configs/katmai.h @@ -0,0 +1,429 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * katmai.h - configuration for AMCC Katmai (440SPe) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_KATMAI 1 /* Board is Katmai */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_440SPE 1 /* Specifc SPe support */ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ +#undef CONFIG_SHOW_BOOT_PROGRESS + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ + +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xff000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CFG_PCI_TARGBASE CFG_PCI_MEMBASE + +#define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ + +#define CFG_PCIE0_CFGBASE 0xc0000000 +#define CFG_PCIE0_XCFGBASE 0xc0000400 +#define CFG_PCIE1_CFGBASE 0xc0001000 +#define CFG_PCIE1_XCFGBASE 0xc0001400 +#define CFG_PCIE2_CFGBASE 0xc0002000 +#define CFG_PCIE2_XCFGBASE 0xc0002400 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE +#undef CFG_EXT_SERIAL_CLOCK +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ +#define CONFIG_DDR_ECC 1 /* with ECC support */ +#undef CONFIG_STRESS + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */ + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0x50) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */ +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/* I2C DTT */ +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ +#define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */ +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the ADM1021, the rest determines index into + * CFG_DTT_ADM1021 array below. + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). + * there will be one entry in this array for each two (dummy) sensors in + * CONFIG_DTT_SENSORS. + * + * For Katmai board: + * - only one ADM1021 + * - i2c addr 0x18 + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg + */ +#define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=katmai\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=katmai/uImage\0" \ + "kernel_addr=fff10000\0" \ + "ramdisk_addr=fff20000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 katmai/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "kozio=bootm ffc60000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_EEPROM | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DTT | \ + CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_HAS_ETH0 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_NET_MULTI /* needed for NetConsole */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#undef CONFIG_PCI_CONFIG_HOST_BRIDGE + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ +#undef CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ +/* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */ + +/* + * NETWORK Support (PCI): + */ +/* Support for Intel 82557/82559/82559ER chips. */ +#define CONFIG_EEPRO100 + +/*----------------------------------------------------------------------- + * Xilinx System ACE support + *----------------------------------------------------------------------*/ +#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ +#define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ +#define CFG_SYSTEMACE_BASE CFG_ACE_BASE +#define CONFIG_DOS_PARTITION 1 + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ + +/* Memory Bank 0 (Flash) initialization */ +#define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(0) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_DELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +#define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \ + EBC_BXCR_BS_16MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/* Memory Bank 1 (Xilinx System ACE controller) initialization */ +#define CFG_EBC_PB1AP 0x7F8FFE80 +#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \ + EBC_BXCR_BS_1MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) + +/*------------------------------------------------------------------------- + * Initialize EBC CONFIG - + * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC + * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 + *-------------------------------------------------------------------------*/ +#define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \ + EBC_CFG_PTD_ENABLE | \ + EBC_CFG_RTC_16PERCLK | \ + EBC_CFG_ATC_PREVIOUS | \ + EBC_CFG_DTC_PREVIOUS | \ + EBC_CFG_CTC_PREVIOUS | \ + EBC_CFG_OEO_PREVIOUS | \ + EBC_CFG_EMC_DEFAULT | \ + EBC_CFG_PME_DISABLE | \ + EBC_CFG_PR_16) + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_GPIO_PCIE_PRESENT0 17 +#define CFG_GPIO_PCIE_PRESENT1 21 +#define CFG_GPIO_PCIE_PRESENT2 23 +#define CFG_GPIO_RS232_FORCEOFF 30 + +#define CFG_PFC0 (GPIO_VAL(CFG_GPIO_PCIE_PRESENT0) | \ + GPIO_VAL(CFG_GPIO_PCIE_PRESENT1) | \ + GPIO_VAL(CFG_GPIO_PCIE_PRESENT2) | \ + GPIO_VAL(CFG_GPIO_RS232_FORCEOFF)) +#define CFG_GPIO_OR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) +#define CFG_GPIO_TCR GPIO_VAL(CFG_GPIO_RS232_FORCEOFF) +#define CFG_GPIO_ODR 0 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h new file mode 100644 index 000000000..7e515230a --- /dev/null +++ b/include/configs/lpc2292sodimm.h @@ -0,0 +1,158 @@ +/* + * (C) Copyright 2000 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * Configuation settings for the EP7312 board. + * + * Modified to work on Armadillo HT1070 ARM720T board + * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start armboot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_INIT_CRITICAL /* undef for developing */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_LPC2292 +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_MMC | \ + CFG_CMD_NET | \ + CFG_CMD_PING) + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_BOOTDELAY 5 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "LPC2292SODIMM # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x40000000 /* memtest works on */ +#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ + +#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ +#define CFG_HZ 2048 /* decrementer freq in Hz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x81000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB SDRAM */ + +#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00200000 /* 2 MB */ + +#define CFG_FLASH_BASE PHYS_FLASH_1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 1024 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR (0x0 + 0x3C000) /* Addr of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MMC 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 0350e91f0..9c8769b20 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,8 +37,9 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -132,10 +133,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* SPD EEPROM init doesn't support DDR2 */ -#define SPD_EEPROM_ADDRESS {0x52,0x53} /* I2C SPD addresses */ -#define IIC0_DIMM0_ADDR 0x52 -#define IIC0_DIMM1_ADDR 0x53 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -178,6 +178,7 @@ "bootfile=/tftpboot/luan/uImage\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc100000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/luan/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ @@ -205,11 +206,6 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* needed for NetConsole */ -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - #ifdef DEBUG #define CONFIG_PANIC_HANG #else @@ -218,9 +214,7 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ CFG_CMD_ELF | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ @@ -231,7 +225,6 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ - CFG_CMD_SETGETDCR | \ CFG_CMD_SDRAM | \ 0) diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 0c935bfce..621a81c9c 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -94,6 +94,8 @@ #define CONFIG_USB_OHCI #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE +/* automatic software updates (see board/mcc200/auto_update.c) */ +#define CONFIG_AUTO_UPDATE 1 /* * Supported commands @@ -173,7 +175,7 @@ * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CFG_I2C_SPEED 100000 /* 100 kHz */ #define CFG_I2C_SLAVE 0x7F @@ -263,6 +265,7 @@ */ #if !defined(CONFIG_PRS200) #define CONFIG_LCD 1 +#define CONFIG_PROGRESSBAR 1 #endif #if defined(CONFIG_LCD) diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h new file mode 100644 index 000000000..0c1029426 --- /dev/null +++ b/include/configs/mecp5200.h @@ -0,0 +1,345 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +/************************************************************************* + * (c) 2005 esd gmbh Hannover + * + * + * from IceCube.h file + * by Reinhard Arlt reinhard.arlt@esd-electronics.com + * + *************************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_ICECUBE 1 /* ... on IceCube board */ +#define CONFIG_MECP5200 1 /* ... on MECP5200 board */ +#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#if 0 /* test-only */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#else +#define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */ +#endif +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +#ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */ + +#define CONFIG_MII +#if 0 /* test-only !!! */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_EEPRO100 1 +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CONFIG_NS8382X 1 +#endif + +#else /* MPC5100 */ + +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +/* USB */ +#if 0 +#define CONFIG_USB_OHCI +#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT +#define CONFIG_USB_STORAGE +#else +#define ADD_USB_CMD 0 +#endif + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_EEPROM | \ + CFG_CMD_FAT | \ + CFG_CMD_EXT2 | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_BSP | \ + CFG_CMD_ELF) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT16 1 +#endif +#if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ +# define CFG_LOWBOOT 1 +# define CFG_LOWBOOT08 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Welcome to CBX-CPU5200 (mecp5200);" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \ + "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \ + "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \ + "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \ + "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \ + "loadaddr=01000000\0" \ + "serverip=192.168.2.99\0" \ + "gatewayip=10.0.0.79\0" \ + "user=mu\0" \ + "target=mecp5200.esd\0" \ + "script=mecp5200.bat\0" \ + "image=/tftpboot/vxWorks_mecp5200\0" \ + "ipaddr=10.0.13.196\0" \ + "netmask=255.255.0.0\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run flash_vxworks0" + +#if defined(CONFIG_MPC5200) +/* + * IPB Bus clocking configuration. + */ +#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ +#endif +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 86000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CFG_I2C_MULTI_EEPROMS 1 +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_SIZE 0x00400000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x003E0000) +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_MAX_FLASH_SECT 512 + +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +/* + * Environment settings + */ +#if 1 /* test-only */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 +#else +#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CFG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/ + /* total size of a CAT24WC32 is 8192 bytes */ +#define CONFIG_ENV_OVERWRITE 1 +#endif + +#define CFG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#if 0 +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#endif +#define CFG_FLASH_INCREMENT 0x00400000 /* size of flash bank */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */ + + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +/* + * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + */ +/* #define CONFIG_FEC_10MBIT 1 */ +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_UDP_CHECKSUM 1 + + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x01052444 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00085d00 + +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +#define CFG_CS1_START 0xfd000000 +#define CFG_CS1_SIZE 0x00010000 +#define CFG_CS1_CFG 0x10101410 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +#define CFG_RESET_ADDRESS 0xff000000 + +/*----------------------------------------------------------------------- + * USB stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_IDE_RESET /* reset for ide supported */ +#define CONFIG_IDE_PREINIT + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#endif /* __CONFIG_H */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h new file mode 100644 index 000000000..5328e8d6b --- /dev/null +++ b/include/configs/motionpro.h @@ -0,0 +1,305 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Based on PRO Motion board config file by Andy Joseph, andy@promessdev.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + + +/* + * High Level Configuration Options + */ + + +/* CPU and board */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ +#define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ + + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_REGINFO | \ + CFG_CMD_IMMAP | \ + CFG_CMD_ELF | \ + CFG_CMD_MII | \ + CFG_CMD_BEDBUG | \ + CFG_CMD_NET | \ + CFG_CMD_PING) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_NETCONSOLE 1 /* network console */ +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x2 +#define CONFIG_PHY_TYPE 0x79c874 + + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" +#define DEBUG_BOOTKEYS 0 +#undef CONFIG_AUTOBOOT_DELAY_STR +#undef CONFIG_BOOTARGS +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"<Esc><Esc>\" to stop\n" + +#define CONFIG_ETHADDR 00:50:C2:40:10:00 +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "sdram_test=0\0" \ + "netdev=eth0\0" \ + "hostname=motionpro\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.22\0" \ + "serverip=192.168.1.1\0" \ + "gatewayip=192.168.1.1\0" \ + "kernel_addr=200000\0" \ + "u-boot_addr=100000\0" \ + "kernel_sector=20\0" \ + "kernel_size=1000\0" \ + "console=ttyS0,115200\0" \ + "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ + "bootfile=/tftpboot/motionpro/uImage\0" \ + "u-boot=/tftpboot/motionpro/u-boot.bin\0" \ + "load=tftp $(u-boot_addr) $(u-boot)\0" \ + "update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \ + "cp.b $(u-boot_addr) fff00000 $(filesize);" \ + "prot on fff00000 fff3ffff\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs $(bootargs) console=$(console) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):" \ + "$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ + "flash_self=run ramargs addip;bootm $(kernel_addr) " \ + "$(ramdisk_addr)\0" \ + "net_nfs=tftp $(kernel_addr) $(bootfile); run nfsargs addip; " \ + "bootm $(kernel_addr)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$(serverip):$(rootpath)\0" \ + "fstype=ext3\0" \ + "fatargs=setenv bootargs init=/linuxrc rw\0" \ + "" +#define CONFIG_BOOTCOMMAND "run net_nfs" + + +/* + * do board-specific init + */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + + +/* + * Low level configuration + */ + + +/* + * Clock configuration: SYS_XTALIN = 25MHz + */ +#define CFG_MPC5XXX_CLKIN 25000000 + + +/* + * Memory map + */ +/* + * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000. + * Setting MBAR to otherwise will cause system hang when using SmartDMA such + * as network commands. + */ +#define CFG_MBAR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 + +/* + * If building for running out of SDRAM, then MBAR has been set up beforehand + * (e.g., by the BDI). Otherwise we must specify the default boot-up value of + * MBAR, as given in the doccumentation. + */ +#if TEXT_BASE == 0x00100000 +#define CFG_DEFAULT_MBAR 0xf0000000 +#else /* TEXT_BASE != 0x00100000 */ +#define CFG_DEFAULT_MBAR 0x80000000 +#define CFG_LOWBOOT 1 +#endif /* TEXT_BASE == 0x00100000 */ + +/* Use SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* 256 kB for Monitor */ +#define CFG_MALLOC_LEN (128 << 10) /* 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ + + +/* + * Chip selects configuration + */ +/* Boot Chipselect */ +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x03035D00 + +/* Flash memory addressing */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE +#define CFG_CS0_CFG CFG_BOOTCS_CFG + +/* Dual Port SRAM -- Kollmorgen Drive memory addressing */ +#define CFG_CS1_START 0x50000000 +#define CFG_CS1_SIZE 0x10000 +#define CFG_CS1_CFG 0x05055800 + +/* Local register access */ +#define CFG_CS2_START 0x50010000 +#define CFG_CS2_SIZE 0x10000 +#define CFG_CS2_CFG 0x05055800 + +/* Anybus CompactCom Module memory addressing */ +#define CFG_CS3_START 0x50020000 +#define CFG_CS3_SIZE 0x10000 +#define CFG_CS3_CFG 0x05055800 + +/* No burst and dead cycle = 2 for all CSs */ +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x22222222 + + +/* + * SDRAM configuration + */ +/* 2 x MT48LC16M16A2BG-75 IT:D, CASL 2, 32 bit data bus */ +#define SDRAM_CONFIG1 0x52222600 +#define SDRAM_CONFIG2 0x88b70000 +#define SDRAM_CONTROL 0x50570000 +#define SDRAM_MODE 0x008d0000 + + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_BASE 0xff000000 +#define CFG_FLASH_SIZE 0x01000000 +#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */ +#define CONFIG_FLASH_16BIT /* Flash is 16-bit */ + + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_SECT_SIZE 0x10000 + + +/* + * Pin multiplexing configuration + */ + +/* PSC1: UART1 + * PSC2: GPIO (default) + * PSC3: GPIO (default) + * USB: 2xUART4/5 + * Ethernet: Ethernet 100Mbit with MD + * Timer: CAN2/GPIO + * PSC6/IRDA: GPIO (default) + */ +#define CFG_GPS_PORT_CONFIG 0x1105a004 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03f00000 /* 1 ... 64 MiB in DRAM */ + +#define CFG_LOAD_ADDR 0x200000 /* default kernel load addr */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ + + +/* Not needed for MPC 5xxx U-Boot, but used by tools/updater */ +#define CFG_RESET_ADDRESS 0xfff00100 + +#endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 89e9164e0..fe4e63810 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -148,8 +148,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */ +#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/ /*----------------------------------------------------------------------- * I2C @@ -192,6 +193,7 @@ "bootfile=/tftpboot/ocotea/uImage\0" \ "kernel_addr=fff00000\0" \ "ramdisk_addr=fff10000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h new file mode 100644 index 000000000..54462f007 --- /dev/null +++ b/include/configs/p3mx.h @@ -0,0 +1,451 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Based on original work by + * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards + * + * The defines: + * CONFIG_P3M750 or + * CONFIG_P3M7448 + * are written into include/config.h by the "make xxx_config" command + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_P3Mx /* used for both board versions */ + +#if defined (CONFIG_P3M750) +#define CONFIG_750FX /* 750GL/GX/FX */ +#define CFG_BOARD_NAME "P3M750" +#define CFG_BUS_HZ 100000000 +#define CFG_BUS_CLK CFG_BUS_HZ +#define CFG_TCLK 100000000 +#elif defined (CONFIG_P3M7448) +#define CONFIG_74xx +#define CFG_BOARD_NAME "P3M7448" +#define CFG_BUS_HZ 133333333 +#define CFG_BUS_CLK CFG_BUS_HZ +#define CFG_TCLK 133333333 +#endif +#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ + +/* which initialization functions to call for this board */ +#define CFG_BOARD_ASM_INIT 1 +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#ifdef CONFIG_P3M750 +#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#if defined (CONFIG_P3M750) +#define CFG_FLASH_BASE 0xff800000 /* start of flash banks */ +#define CFG_BOOT_SIZE _8M /* boot flash */ +#elif defined (CONFIG_P3M7448) +#define CFG_FLASH_BASE 0xff000000 /* start of flash banks */ +#define CFG_BOOT_SIZE _16M /* boot flash */ +#endif +#define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */ +#define CFG_MONITOR_BASE 0xfff00000 +#define CFG_RESET_ADDRESS 0xfff00100 +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ +#define CFG_MISC_REGION_BASE 0xf0000000 + +#define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ +#define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */ +#define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ + /* + * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS + * To an unused memory region. The stack will remain in cache until RAM + * is initialized +*/ +#undef CFG_INIT_RAM_LOCK +#define CFG_INIT_RAM_ADDR 0x42000000 +#define CFG_INIT_RAM_END 0x1000 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) + + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_MPSC /* MV64460 Serial */ +#define CONFIG_MPSC_PORT 0 +#define CONFIG_BAUDRATE 115200 /* console baudrate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Ethernet + *----------------------------------------------------------------------*/ +/* Change the default ethernet port, use this define (options: 0, 1, 2) */ +#define CFG_ETH_PORT ETH_0 +#define CONFIG_NET_MULTI +#define MV_ETH_DEVS 2 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#if defined (CONFIG_P3M750) +#define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/ +#elif defined (CONFIG_P3M7448) +#define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ +#endif +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_MV64460_ECC + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CFG_I2C_SPEED 100000 /* I2C speed default */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CFG_I2C_RTC_ADDR 0x68 +#define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#undef CONFIG_PCI /* include pci support */ +#ifdef CONFIG_PCI +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ +#endif /* CONFIG_PCI */ + +/* PCI MEMORY MAP section */ +#define CFG_PCI0_MEM_BASE 0x80000000 +#define CFG_PCI0_MEM_SIZE _128M +#define CFG_PCI1_MEM_BASE 0x88000000 +#define CFG_PCI1_MEM_SIZE _128M + +#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) +#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) + +/* PCI I/O MAP section */ +#define CFG_PCI0_IO_BASE 0xfa000000 +#define CFG_PCI0_IO_SIZE _16M +#define CFG_PCI1_IO_BASE 0xfb000000 +#define CFG_PCI1_IO_SIZE _16M + +#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) +#define CFG_PCI0_IO_SPACE_PCI 0x00000000 +#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) +#define CFG_PCI1_IO_SPACE_PCI 0x00000000 + +#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) +#define CFG_PCI_IDSEL 0x30 + +#undef CONFIG_BOOTARGS +#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_6xx\0" \ + "u-boot=p3mx/u-boot/u-boot.bin\0" \ + "load=tftp 100000 ${u-boot}\0" \ + "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ + "cp.b 100000 fff00000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "serverip=11.0.0.152\0" + +#if defined (CONFIG_P3M750) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "hostname=p3m750\0" \ + "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "vxfile=p3m750/vxWorks\0" \ + "vxuser=ddg\0" \ + "vxpass=ddg\0" \ + "vxtarget=target\0" \ + "vxflags=0x8\0" \ + "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ + "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ + "f=${vxflags}\0" +#elif defined (CONFIG_P3M7448) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_EXTRA_ENV_SETTINGS_COMMON \ + "hostname=p3m7448\0" +#endif + +#if defined (CONFIG_P3M750) +#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" +#elif defined (CONFIG_P3M7448) +#define CONFIG_BOOTCOMMAND " " +#endif + +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ + CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DIAG | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_PCI | \ + CFG_CMD_CACHE | \ + CFG_CMD_SDRAM) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x08000000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * Marvell MV64460 config settings + *----------------------------------------------------------------------*/ +/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ +#if defined (CONFIG_P3M750) +#define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ +#elif defined (CONFIG_P3M7448) +#define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ +#endif + +/* + * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) + * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) + * MPP[2] NC + * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) + * MPP[4] PCI Monarch# GPIO IN Connected to P12 + * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) + * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 + * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 + * MPP[8] Reserved Do not use + * MPP[9] Reserved Do not use + * MPP[10] Reserved Do not use + * MPP[11] Reserved Do not use + * MPP[12] Phy 0 Interrupt Int IN + * MPP[13] Phy 1 Interrupt Int IN + * MPP[14] NC + * MPP[15] NC + * MPP[16] PCI Interrupt C Int IN Connected to P11 + * MPP[17] PCI Interrupt D Int IN Connected to P11 + * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] + * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic + * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog + * MPP[21] NC + * MPP[22] GP LED Green GPIO OUT + * MPP[23] GP LED Red GPIO OUT + * MPP[24] Watchdog NMI# Int OUT + * MPP[25] NC + * MPP[26] NC + * MPP[27] PCI Interrupt A Int IN Connected to P11 + * MPP[28] NC + * MPP[29] PCI Interrupt B Int IN Connected to P11 + * MPP[30] Module reset GPIO OUT Board reset + * MPP[31] PCI EReady GPIO IN Connected to P12 + */ +#define CFG_MPP_CONTROL_0 0x00303022 +#define CFG_MPP_CONTROL_1 0x00000000 +#define CFG_MPP_CONTROL_2 0x00004000 +#define CFG_MPP_CONTROL_3 0x00000004 +#define CFG_GPP_LEVEL_CONTROL 0x280730D0 + +/*---------------------------------------------------------------------- + * Initial BAT mappings + */ + +/* NOTES: + * 1) GUARDED and WRITE_THRU not allowed in IBATS + * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT + */ +/* SDRAM */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) +#define CFG_DBAT0U CFG_IBAT0U + +/* init ram */ +#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U + +/* PCI0, PCI1 in one BAT */ +#define CFG_IBAT2L BATL_NO_ACCESS +#define CFG_IBAT2U CFG_DBAT2U +#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* GT regs, bootrom, all the devices, PCI I/O */ +#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) +#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) +#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) +#define CFG_DBAT3U CFG_IBAT3U + +#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT4U CFG_IBAT4U + +/* set rest out of range for Linux !!!!!!!!!!! */ + +/* IBAT5 and DBAT5 */ +#define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT5U CFG_IBAT5U + +/* IBAT6 and DBAT6 */ +#define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT6U CFG_IBAT6U + +/* IBAT7 and DBAT7 */ +#define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_DBAT7U CFG_IBAT7U + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ +#define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * L2CR setup -- make sure this is right for your board! + * look in include/mpc74xx.h for the defines used here + */ +#define CFG_L2 + +#if defined (CONFIG_750CX) || defined (CONFIG_750FX) +#define L2_INIT 0 +#else +#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ + L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) +#endif + +#define L2_ENABLE (L2_INIT | L2CR_L2E) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index ba6b113d8..06c665287 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Configuation settings for the PDNB3 board. @@ -71,12 +71,18 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +#if defined(CONFIG_SCPU) +#define CMD_NAND_ADD 0 +#else +#define CMD_NAND_ADD CFG_CMD_NAND +#endif + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_DATE | \ CFG_CMD_NET | \ CFG_CMD_MII | \ - CFG_CMD_NAND | \ + CMD_NAND_ADD | \ CFG_CMD_I2C | \ CFG_CMD_ELF | \ CFG_CMD_PING) @@ -176,12 +182,20 @@ #define CFG_FLASH_BASE 0x50000000 #define CFG_MONITOR_BASE CFG_FLASH_BASE +#if defined(CONFIG_SCPU) +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ +#else #define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ +#endif /* * Expansion bus settings */ +#if defined(CONFIG_SCPU) +#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */ +#else #define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */ +#endif #define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */ /* @@ -194,6 +208,12 @@ /* * FLASH and environment organization */ +#if defined(CONFIG_SCPU) +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#endif + #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -217,20 +237,28 @@ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +#if defined(CONFIG_SCPU) +/* no redundant environment on SCPU */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#else +#define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif +#if !defined(CONFIG_SCPU) /* * NAND-FLASH stuff */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ +#endif /* * GPIO settings @@ -284,9 +312,15 @@ /* * I2C RTC */ +#if 0 /* test-only */ +#define CONFIG_RTC_DS1340 1 +#define CFG_I2C_RTC_ADDR 0x68 +#else +/* M41T11 Serial Access Timekeeper(R) SRAM */ #define CONFIG_RTC_M41T11 1 #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ +#endif /* * Spartan3 FPGA configuration support diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h new file mode 100644 index 000000000..65aac5cef --- /dev/null +++ b/include/configs/sbc8349.h @@ -0,0 +1,734 @@ +/* + * WindRiver SBC8349 U-Boot configuration file. + * Copyright (c) 2006, 2007 Wind River Systems, Inc. + * + * Paul Gortmaker <paul.gortmaker@windriver.com> + * Based on the MPC8349EMDS config. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * sbc8349 board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef DEBUG + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC8349 1 /* MPC8349 specific */ +#define CONFIG_SBC8349 1 /* WRS SBC8349 board specific */ + +#undef CONFIG_PCI +/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ +#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ + +#define PCI_66M +#ifdef PCI_66M +#define CONFIG_83XX_CLKIN 66000000 /* in Hz */ +#else +#define CONFIG_83XX_CLKIN 33000000 /* in Hz */ +#endif + +#ifndef CONFIG_SYS_CLK_FREQ +#ifdef PCI_66M +#define CONFIG_SYS_CLK_FREQ 66000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 +#else +#define CONFIG_SYS_CLK_FREQ 33000000 +#define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 +#endif +#endif + +#undef CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ + +#define CFG_IMMR 0xE0000000 + +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00000000 /* memtest region */ +#define CFG_MEMTEST_END 0x00100000 + +/* + * DDR Setup + */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ +#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ +#define CFG_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ + +/* + * 32-bit data path mode. + * + * Please note that using this mode for devices with the real density of 64-bit + * effectively reduces the amount of available memory due to the effect of + * wrapping around while translating address to row/columns, for example in the + * 256MB module the upper 128MB get aliased with contents of the lower + * 128MB); normally this define should be used for devices with real 32-bit + * data path. + */ +#undef CONFIG_DDR_32BIT + +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE +#define CFG_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) +#define CONFIG_DDR_2T_TIMING + +#if defined(CONFIG_SPD_EEPROM) +/* + * Determine DDR configuration from I2C interface. + */ +#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ + +#else +/* + * Manually set up DDR parameters + * NB: manual DDR setup untested on sbc834x + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CFG_DDR_TIMING_1 0x36332321 +#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ +#define CFG_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ + +#if defined(CONFIG_DDR_32BIT) +/* set burst length to 8 for 32-bit data path */ +#define CFG_DDR_MODE 0x00000023 /* DLL,normal,seq,4/2.5, 8 burst len */ +#else +/* the default burst length is 4 - for 64-bit data path */ +#define CFG_DDR_MODE 0x00000022 /* DLL,normal,seq,4/2.5, 4 burst len */ +#endif +#endif + +/* + * SDRAM on the Local Bus + */ +#define CFG_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ +#define CFG_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ + +/* + * FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFF800000 /* start of FLASH */ +#define CFG_FLASH_SIZE 8 /* flash size in MB */ +/* #define CFG_FLASH_USE_BUFFER_WRITE */ + +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \ + (2 << BR_PS_SHIFT) | /* 32 bit port size */ \ + BR_V) /* valid */ + +#define CFG_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */ +#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CFG_MID_FLASH_JUMP 0x7F000000 +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#else +#undef CFG_RAMBOOT +#endif + +#define CONFIG_L1_INIT_RAM +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + * LCRR: DLL bypass, Clock divider is 4 + * External Local Bus rate is + * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV + */ +#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CFG_LBC_LBCR 0x00000000 + +#undef CFG_LB_SDRAM /* if board has SDRAM on local bus */ + +#ifdef CFG_LB_SDRAM +/* Local bus BR2, OR2 definition for SDRAM if soldered on the board*/ +/* + * Base Register 2 and Option Register 2 configure SDRAM. + * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000. + * + * For BR2, need: + * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 + * + * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into + * FIXME: the top 17 bits of BR2. + */ + +#define CFG_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ +#define CFG_LBLAWBAR2_PRELIM 0xF0000000 +#define CFG_LBLAWAR2_PRELIM 0x80000019 /* 64M */ + +/* + * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. + * + * For OR2, need: + * 64MB mask for AM, OR2[0:7] = 1111 1100 + * XAM, OR2[17:18] = 11 + * 9 columns OR2[19-21] = 010 + * 13 rows OR2[23-25] = 100 + * EAD set for extra time OR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 + */ + +#define CFG_OR2_PRELIM 0xFC006901 + +#define CFG_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* + * LSDMR masks + */ +#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1)) +#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) +#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) +#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR8 (5 << (31 - 16)) +#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16)) +#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) +#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) +#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) +#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) +#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23)) +#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC3 (3 << (31 - 27)) +#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27)) +#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29)) +#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31)) + +#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) +#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) + +#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ + | CFG_LBC_LSDMR_BSMA1516 \ + | CFG_LBC_LSDMR_RFCR8 \ + | CFG_LBC_LSDMR_PRETOACT6 \ + | CFG_LBC_LSDMR_ACTTORW3 \ + | CFG_LBC_LSDMR_BL8 \ + | CFG_LBC_LSDMR_WRC3 \ + | CFG_LBC_LSDMR_CL3 \ + ) + +/* + * SDRAM Controller configuration sequence. + */ +#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_PCHALL) +#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_ARFRSH) +#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_MRW) +#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ + | CFG_LBC_LSDMR_OP_NORMAL) +#endif + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_CLK get_bus_freq(0) + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CFG_NS16550_COM1 (CFG_IMMR+0x4500) +#define CFG_NS16550_COM2 (CFG_IMMR+0x4600) + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 + +#define OF_CPU "PowerPC,8349@0" +#define OF_SOC "soc8349@e0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc8349@e0000000/serial@4500" + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C1_OFFSET 0x3000 +#define CFG_I2C2_OFFSET 0x3100 +#define CFG_I2C_OFFSET CFG_I2C2_OFFSET +/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SPD_BUS_NUM... */ + +/* TSEC */ +#define CFG_TSEC1_OFFSET 0x24000 +#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) +#define CFG_TSEC2_OFFSET 0x25000 +#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CFG_PCI1_MEM_BASE 0x80000000 +#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE +#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_MMIO_BASE 0x90000000 +#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE +#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xE2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CFG_PCI2_MEM_BASE 0xA0000000 +#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE +#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_MMIO_BASE 0xB0000000 +#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE +#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xE2100000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ + +#if defined(CONFIG_PCI) + +#define PCI_64BIT +#define PCI_ONE_PCI1 +#if defined(PCI_64BIT) +#undef PCI_ALL_PCI1 +#undef PCI_TWO_PCI1 +#undef PCI_ONE_PCI1 +#endif + +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#undef CONFIG_EEPRO100 +#undef CONFIG_TULIP + +#if !defined(CONFIG_PCI_PNP) + #define PCI_ENET0_IOADDR 0xFIXME + #define PCI_ENET0_MEMADDR 0xFIXME + #define PCI_IDSEL_NUMBER 0xFIXME +#endif + +#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +#endif /* CONFIG_PCI */ + +/* + * TSEC configuration + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#if defined(CONFIG_TSEC_ENET) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif + +#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#define CONFIG_MPC83XX_TSEC2 1 +#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_PHY_BCM5421S 1 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC0" + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#ifndef CFG_RAMBOOT + #define CFG_ENV_IS_IN_FLASH 1 + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + #define CFG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#else + #define CFG_NO_FLASH 1 /* Flash is not usable now */ + #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) + #define CFG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CFG_RAMBOOT) +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_PCI \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#else +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C) \ + & \ + ~(CFG_CMD_ENV \ + | CFG_CMD_LOADS)) +#endif +#else +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PING \ + | CFG_CMD_I2C \ + | CFG_CMD_MII \ + ) +#endif +#endif + +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#if 1 /*528/264*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X2 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*396/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_3X1) +#elif 0 /*264/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_2X1) +#elif 0 /*132/132*/ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#elif 0 /*264/264 */ +#define CFG_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_1X1 |\ + HRCWL_CSB_TO_CLKIN |\ + HRCWL_VCO_1X4 |\ + HRCWL_CORE_TO_CSB_1X1) +#endif + +#if defined(PCI_64BIT) +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_32_BIT_PCI |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_PCI2_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#endif + +/* System IO Config */ +#define CFG_SICRH SICRH_TSOBI1 +#define CFG_SICRL SICRL_LDP_A + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK + +/* #define CFG_HID0_FINAL (\ + HID0_ENABLE_INSTRUCTION_CACHE |\ + HID0_ENABLE_M_BIT |\ + HID0_ENABLE_ADDRESS_BROADCAST ) */ + + +#define CFG_HID2 HID2_HBE + +/* DDR @ 0x00000000 */ +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#ifdef CONFIG_PCI +#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT1L (0) +#define CFG_IBAT1U (0) +#define CFG_IBAT2L (0) +#define CFG_IBAT2U (0) +#endif + +#ifdef CONFIG_MPC83XX_PCI2 +#define CFG_IBAT3L (CFG_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT3U (CFG_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT4U (CFG_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#else +#define CFG_IBAT3L (0) +#define CFG_IBAT3U (0) +#define CFG_IBAT4L (0) +#define CFG_IBAT4U (0) +#endif + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CFG_IBAT5L (CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT5U (CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CFG_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CFG_IBAT7L (0) +#define CFG_IBAT7U (0) + +#define CFG_DBAT0L CFG_IBAT0L +#define CFG_DBAT0U CFG_IBAT0U +#define CFG_DBAT1L CFG_IBAT1L +#define CFG_DBAT1U CFG_IBAT1U +#define CFG_DBAT2L CFG_IBAT2L +#define CFG_DBAT2U CFG_IBAT2U +#define CFG_DBAT3L CFG_IBAT3L +#define CFG_DBAT3U CFG_IBAT3U +#define CFG_DBAT4L CFG_IBAT4L +#define CFG_DBAT4U CFG_IBAT4U +#define CFG_DBAT5L CFG_IBAT5L +#define CFG_DBAT5U CFG_IBAT5U +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_ETHADDR 00:a0:1e:a0:13:8d +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:a0:1e:a0:13:8e +#endif + +#define CONFIG_IPADDR 192.168.1.234 + +#define CONFIG_HOSTNAME SBC8349 +#define CONFIG_ROOTPATH /tftpboot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.255.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=sbc8349\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "fdtaddr=400000\0" \ + "fdtfile=sbc8349.dtb\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h new file mode 100644 index 000000000..8298084f1 --- /dev/null +++ b/include/configs/sc3.h @@ -0,0 +1,588 @@ +/* + * (C) Copyright 2007 + * Heiko Schocher, DENX Software Engineering, <hs@denx.de>. + * + * From: + * (C) Copyright 2003 + * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#undef USE_VGA_GRAPHICS + +/* Memory Map + * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB) + * 0x74000000 .... 0x740FFFFF -> CS#6 + * 0x74100000 .... 0x741FFFFF -> CS#7 + * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB + * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE + * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB) + * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB) + * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB) + * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB) + * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored) + * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB) + * + * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1) + * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF) + * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF) + * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF) + * 0xEED00000 .... 0xEED00003 -> PCI-Bus + * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers + * 0xEF40003F .... 0xEF5FFFFF -> reserved + * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB) + * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB) + * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices + * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB) + * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices + * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) + */ + +#define CONFIG_SOLIDCARD3 1 +#define CONFIG_4xx 1 +#define CONFIG_405GP 1 + +#define CONFIG_BOARD_EARLY_INIT_F 1 + +/* + * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range + * If undefined, IDE access uses a seperat emulation with higher access speed. + * Consider to inform your Linux IDE driver about the different addresses! + * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes + * the CFG_CMD_IDE macro! + */ +#define IDE_USES_ISA_EMULATION + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_SERIAL_MULTI +#undef CONFIG_SERIAL_SOFTWARE_FIFO +/* + * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input + * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature + */ +#if CONFIG_SERIAL_SOFTWARE_FIFO + #define CONFIG_POWER_DOWN +#endif + +/* + * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz + */ +#define CONFIG_SYS_CLK_FREQ 33333333 + +/* + * define CONFIG_BAUDRATE to the baudrate value you want to use as default + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ + "rootfstype=jffs2\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=ttyS0,${baudrate}\0" \ + "flash_nfs=run nfsargs addip addcons;" \ + "bootm ${kernel_addr}\0" \ + "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/sc3/uImage\0" \ + "u-boot=/tftpboot/sc3/u-boot.bin\0" \ + "setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \ + "kernel_addr=FFE08000\0" \ + "" +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +#if 1 /* feel free to disable for development */ +#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ +#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with S\n" +#define CONFIG_AUTOBOOT_DELAY_STR "S" /* 1st "password" */ +#endif + +/* + * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after + * the CONFIG_BOOTDELAY delay to boot your machine + */ +#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm" + +/* + * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't + * set different values at the u-boot prompt + */ +#ifdef USE_VGA_GRAPHICS + #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re" +#else + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp" +#endif +/* + * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT + * This reserves memory bank #4 for this purpose + */ +#undef CONFIG_ISP1161_PRESENT + +#undef CONFIG_LOADS_ECHO /* no echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_NET_MULTI +/* #define CONFIG_EEPRO100_SROM_WRITE */ +/* #define CONFIG_SHOW_MAC */ +#define CONFIG_EEPRO100 +#define CONFIG_MII 1 /* add 405GP MII PHY management */ +#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ + +#define CONFIG_COMMANDS \ + (CONFIG_CMD_DFL | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_CACHE | \ + CFG_CMD_ELF ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ + +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +/* + * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1. + * If CFG_405_UART_ERRATA_59, then UART divisor is 31. + * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value. + * The Linux BASE_BAUD define should match this configuration. + * baseBaud = cpuClock/(uartDivisor*16) + * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock, + * set Linux BASE_BAUD to 403200. + * + * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to + * (see 405GP datasheet for descritpion) + */ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ +#define CFG_BASE_BAUD 921600 /* internal clock */ + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +#define CFG_LOAD_ADDR 0x1000000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/*----------------------------------------------------------------------- + * IIC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ + +#define I2C_INIT +#define I2C_ACTIVE 0 +#define I2C_TRISTATE 0 + +#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */ +#define CFG_I2C_SLAVE 0x7F /* mask valid bits */ + +#define CONFIG_RTC_DS1337 +#define CFG_I2C_RTC_ADDR 0x68 + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ + +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ + +/* If you want to see, whats connected to your PCI bus */ +/* #define CONFIG_PCI_SCAN_SHOW */ + +#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ +#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ +#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ + +/*----------------------------------------------------------------------- + * External peripheral base address + *----------------------------------------------------------------------- + */ +#if !(CONFIG_COMMANDS & CFG_CMD_IDE) + +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ +#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ +#define CONFIG_START_IDE 1 /* check, if use IDE */ + +#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* no reset for ide supported */ + +#define CONFIG_ATAPI +#define CONFIG_DOS_PARTITION +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ + +#ifndef IDE_USES_ISA_EMULATION + +/* New and faster access */ +#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */ + +/* How many IDE busses are available */ +#define CFG_IDE_MAXBUS 1 + +/* What IDE ports are available */ +#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */ +#undef CFG_ATA_IDE1_OFFSET /* second not available */ + +/* access to the data port is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ + +/* access to the registers is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ + +/* access to the alternate register is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */ +#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */ + +#else /* IDE_USES_ISA_EMULATION */ + +#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */ + +/* How many IDE busses are available */ +#define CFG_IDE_MAXBUS 1 + +/* What IDE ports are available */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */ +#undef CFG_ATA_IDE1_OFFSET /* second not available */ + +/* access to the data port is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */ +#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ + +/* access to the registers is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */ +#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ + +/* access to the alternate register is calculated: + CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */ +#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */ + +#endif /* IDE_USES_ISA_EMULATION */ + +#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ + +/* +#define CFG_KEY_REG_BASE_ADDR 0xF0100000 +#define CFG_IR_REG_BASE_ADDR 0xF0200000 +#define CFG_FPGA_REG_BASE_ADDR 0xF0300000 +*/ + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + * + * CFG_FLASH_BASE -> start address of internal flash + * CFG_MONITOR_BASE -> start of u-boot + */ +#ifndef __ASSEMBLER__ +extern unsigned long offsetOfBigFlash; +extern unsigned long offsetOfEnvironment; +#endif + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */ +#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */ +#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MiB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +/*----------------------------------------------------------------------- + * FLASH organization ## FIXME: lookup in datasheet + */ +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ + +#define CFG_ENV_IS_IN_FLASH 1 +#if CFG_ENV_IS_IN_FLASH +#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#endif +/* let us changing anything in our environment */ +#define CONFIG_ENV_OVERWRITE + +/* + * NAND-FLASH stuff + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE 0x77D00000 + + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ + +/* No command line, one static partition Partition 3 contains jffs2 rootfs */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00c00000 + +/*----------------------------------------------------------------------- + * Cache Configuration + * + * CFG_DCACHE_SIZE -> size of data cache: + * - 405GP 8k + * - 405GPr 16k + * How to handle the difference in chache size? + * CFG_CACHELINE_SIZE -> size of one cache line: 32 bytes + * (used in cpu/ppc4xx/start.S) +*/ +#define CFG_DCACHE_SIZE 16384 + +#define CFG_CACHELINE_SIZE 32 + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Init Memory Controller: + * + */ + +#define FLASH_BASE0_PRELIM CFG_FLASH_BASE +#define FLASH_BASE1_PRELIM 0 + +/*----------------------------------------------------------------------- + * Some informations about the internal SRAM (OCM=On Chip Memory) + * + * CFG_OCM_DATA_ADDR -> location + * CFG_OCM_DATA_SIZE -> size +*/ + +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x1000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM): + * - we are using the internal 4k SRAM, so we don't need data cache mapping + * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR + * - Stackpointer will be located to + * (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF) + * in cpu/ppc4xx/start.S + */ + +#undef CFG_INIT_DCACHE_CS +/* Where the internal SRAM starts */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR +/* Where the internal SRAM ends (only offset) */ +#define CFG_INIT_RAM_END 0x0F00 + +/* + + CFG_INIT_RAM_ADDR ------> ------------ lower address + | | + | ^ | + | | | + | | Stack | + CFG_GBL_DATA_OFFSET ----> ------------ + | | + | 64 Bytes | + | | + CFG_INIT_RAM_END ------> ------------ higher address + (offset only) + +*/ +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 64 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +/* Initial value of the stack pointern in internal SRAM */ +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* ################################################################################### */ +/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */ +/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */ + +/* This chip select accesses the boot device */ +/* It depends on boot select switch if this device is 16 or 8 bit */ + +#undef CFG_EBC_PB0AP +#undef CFG_EBC_PB0CR + +#undef CFG_EBC_PB1AP +#undef CFG_EBC_PB1CR + +#undef CFG_EBC_PB2AP +#undef CFG_EBC_PB2CR + +#undef CFG_EBC_PB3AP +#undef CFG_EBC_PB3CR + +#undef CFG_EBC_PB4AP +#undef CFG_EBC_PB4CR + +#undef CFG_EBC_PB5AP +#undef CFG_EBC_PB5CR + +#undef CFG_EBC_PB6AP +#undef CFG_EBC_PB6CR + +#undef CFG_EBC_PB7AP +#undef CFG_EBC_PB7CR + +#define CFG_EBC_CFG 0xb84ef000 + +#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ +#undef CONFIG_SPD_EEPROM + +/* + * Define this to get more information about system configuration + */ +/* #define SC3_DEBUGOUT */ +#undef SC3_DEBUGOUT + +/*********************************************************************** + * External peripheral base address + ***********************************************************************/ + +#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000 +/* + Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu. + Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die + das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen + auf ISA- und PCI-Zyklen) + */ +#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 +/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */ + +/************************************************************ + * Video support + ************************************************************/ + +#ifdef USE_VGA_GRAPHICS +#define CONFIG_VIDEO /* To enable video controller support */ +#define CONFIG_VIDEO_CT69000 +#define CONFIG_CFB_CONSOLE +/* #define CONFIG_VIDEO_LOGO */ +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_SW_CURSOR +/* #define CONFIG_VIDEO_HW_CURSOR */ +#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */ + +#define VIDEO_HW_RECTFILL +#define VIDEO_HW_BITBLT + +#endif + +/************************************************************ + * Ident + ************************************************************/ +#define CONFIG_SC3_VERSION "r1.4" + +#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x) + +#endif /* __CONFIG_H */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 1a460cde0..29f3b408d 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 @@ -23,7 +23,7 @@ */ /************************************************************************ - * sequoia.h - configuration for Sequoia board (PowerPC440EPx) + * sequoia.h - configuration for Sequoia & Rainier boards ***********************************************************************/ #ifndef __CONFIG_H #define __CONFIG_H @@ -31,7 +31,7 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ +/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */ #ifndef CONFIG_RAINIER #define CONFIG_SEQUOIA 1 /* Board is Sequoia */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ @@ -39,7 +39,7 @@ #define CONFIG_440GRX 1 /* Specific PPC440GRx */ #endif #define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -102,6 +102,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ #else #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */ #endif /*----------------------------------------------------------------------- @@ -187,7 +188,10 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#endif /*----------------------------------------------------------------------- * I2C @@ -218,9 +222,21 @@ #undef CONFIG_BOOTARGS +/* Setup some board specific values for the default environment variables */ +#ifndef CONFIG_RAINIER +#define CONFIG_HOSTNAME sequoia +#define CFG_BOOTFILE "bootfile=/tftpboot/sequoia/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" +#else +#define CONFIG_HOSTNAME rainier +#define CFG_BOOTFILE "bootfile=/tftpboot/rainier/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ "netdev=eth0\0" \ - "hostname=sequoia\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -234,13 +250,11 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xxFP\0" \ - "bootfile=/tftpboot/sequoia/uImage\0" \ "kernel_addr=FC000000\0" \ "ramdisk_addr=FC180000\0" \ - "load=tftp 100000 /tftpboot/sequoia/u-boot.bin\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 100000 FFFA0000 60000\0" \ + "cp.b 200000 FFFA0000 60000\0" \ "upd=run load;run update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -345,7 +359,7 @@ *----------------------------------------------------------------------*/ /* General PCI */ #define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ @@ -377,7 +391,7 @@ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CFG_NAND_CS 3 /* NAND chip connected to CSx */ /* Memory Bank 0 (NOR-FLASH) initialization */ -#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0AP 0x03017200 #define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) /* Memory Bank 3 (NAND-FLASH) initialization */ @@ -386,7 +400,7 @@ #else #define CFG_NAND_CS 0 /* NAND chip connected to CSx */ /* Memory Bank 3 (NOR-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x03017300 +#define CFG_EBC_PB3AP 0x03017200 #define CFG_EBC_PB3CR (CFG_FLASH | 0xda000) /* Memory Bank 0 (NAND-FLASH) initialization */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index 9d3609a67..09bbebdce 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -44,19 +44,19 @@ #define CONFIG_BAUDRATE 19200 /* use PLD CLK4 instead of brg */ -#undef CFG_SPC1920_SMC1_CLK4 +#define CFG_SPC1920_SMC1_CLK4 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 -#define CFG_RESET_ADDRESS 0xf8000000 +#define CFG_RESET_ADDRESS 0xC0000000 #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_LAST_STAGE_INIT - -#if 1 +#if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ #else #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -83,12 +83,13 @@ #ifndef CONFIG_COMMANDS #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_ASKENV \ + | CFG_CMD_DATE \ | CFG_CMD_ECHO \ | CFG_CMD_IMMAP \ | CFG_CMD_JFFS2 \ | CFG_CMD_PING \ | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ + | CFG_CMD_I2C \ | CFG_CMD_MII) /* & ~( CFG_CMD_NET)) */ @@ -193,13 +194,39 @@ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#ifdef CFG_CMD_DATE +# define CONFIG_RTC_DS3231 +# define CFG_I2C_RTC_ADDR 0x68 +#endif + /*----------------------------------------------------------------------- * I2C configuration */ #if (CONFIG_COMMANDS & CFG_CMD_I2C) -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */ -#define CFG_I2C_SLAVE 0x7F +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ #endif /*----------------------------------------------------------------------- @@ -220,7 +247,7 @@ *----------------------------------------------------------------------- * PCMCIA config., multi-function pin tri-state */ -#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#define CFG_SIUMCR (SIUMCR_FRC) /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control 11-26 @@ -283,7 +310,7 @@ * FLASH timing: */ #define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) + OR_SCY_6_CLK | OR_EHTR | OR_BI) #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) @@ -330,7 +357,56 @@ MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ -/* PLD CS5 */ +/* + * DSP Host Port Interface CS3 + */ +#define CFG_SPC1920_HPI_BASE 0x90000000 +#define CFG_PRELIM_OR3_AM 0xF8000000 + +#define CFG_OR3 (CFG_PRELIM_OR3_AM | \ + OR_G5LS | \ + OR_SCY_0_CLK | \ + OR_BI) + +#define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \ + BR_MS_UPMA | \ + BR_PS_16 | \ + BR_V); + +#define CFG_MAMR (MAMR_GPL_A4DIS | \ + MAMR_RLFA_5X | \ + MAMR_WLFA_5X) + +#define CONFIG_SPC1920_HPI_TEST + +#ifdef CONFIG_SPC1920_HPI_TEST +#define HPI_REG(x) (*((volatile u16 *) (CFG_SPC1920_HPI_BASE + x))) +#define HPI_HPIC_1 HPI_REG(0) +#define HPI_HPIC_2 HPI_REG(2) +#define HPI_HPIA_1 HPI_REG(0x2000008) +#define HPI_HPIA_2 HPI_REG(0x2000008 + 2) +#define HPI_HPID_INC_1 HPI_REG(0x1000004) +#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2) +#define HPI_HPID_NOINC_1 HPI_REG(0x300000c) +#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2) +#endif /* CONFIG_SPC1920_HPI_TEST */ + +/* + * Ramtron FM18L08 FRAM 32KB on CS4 + */ +#define CFG_SPC1920_FRAM_BASE 0x80100000 +#define CFG_PRELIM_OR4_AM 0xffff8000 +#define CFG_OR4 (CFG_PRELIM_OR4_AM | \ + OR_ACS_DIV2 | \ + OR_BI | \ + OR_SCY_4_CLK | \ + OR_TRLX) + +#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); + +/* + * PLD CS5 + */ #define CFG_SPC1920_PLD_BASE 0x80000000 #define CFG_PRELIM_OR5_AM 0xffff8000 @@ -343,10 +419,6 @@ #define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V); -/* #define CFG_PLD_BASE 0x30000000 */ -/* #define CFG_OR5_PRELIM 0xffff1110 */ -/* #define CFG_BR5_PRELIM 0x30000401 */ - /* * Internal Definitions * diff --git a/include/configs/stamp.h b/include/configs/stamp.h deleted file mode 100644 index 248ca70de..000000000 --- a/include/configs/stamp.h +++ /dev/null @@ -1,333 +0,0 @@ -/* - * U-boot - stamp.h Configuration file for STAMP board - * having BF533 processor - * - * Copyright (c) 2005 blackfin.uclinux.org - * - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_STAMP_H__ -#define __CONFIG_STAMP_H__ - -/* - * Board settings - * - */ - -#define __ADSPLPBLACKFIN__ 1 -#define __ADSPBF533__ 1 -#define CONFIG_STAMP 1 -#define CONFIG_RTC_BF533 1 - -/* FLASH/ETHERNET uses the same address range */ -#define SHARED_RESOURCES 1 - -#define CONFIG_VDSP 1 - -/* - * Clock settings - * - */ - -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 11059200 -/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */ -/* 1=CLKIN/2 */ -#define CONFIG_CLKIN_HALF 0 -/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */ -/* 1=bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */ -/* Values can range from 1-64 */ -#define CONFIG_VCO_MULT 45 -/* CONFIG_CCLK_DIV controls what the core clock divider is */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 6 - -/* - * Network Settings - */ -/* network support */ -#define CONFIG_IPADDR 192.168.0.15 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_HOSTNAME STAMP -#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs - -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */ - -/* - * Command settings - * - */ - -#define CFG_LONGHELP 1 - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */ -#define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" - -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot 0x1000000 linux;" \ - "run ramargs;run addip;bootelf\0" \ - "nfsboot=tftpboot 0x1000000 linux;" \ - "run nfsargs;run addip;bootelf\0" \ - "flashboot=bootm 0x20100000\0" \ - "" - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include <cmd_confdefs.h> - -/* - * Console settings - * - */ - -#define CONFIG_BAUDRATE 57600 -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_LOADS_ECHO 1 - -/* - * Network settings - * - */ - -#define CONFIG_DRIVER_SMC91111 1 -#define CONFIG_SMC91111_BASE 0x20300300 -/* To remove hardcoding and enable MAC storage in EEPROM */ -/* #define HARDCODE_MAC 1 */ - -/* - * Flash settings - * - */ - -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET - -#define CFG_ENV_IS_IN_FLASH 1 - -#define CFG_FLASH_BASE 0x20000000 -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ - -#define CFG_ENV_ADDR 0x20020000 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */ - -#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */ -#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */ - -/* JFFS Partition offset set */ -#define CFG_JFFS2_FIRST_BANK 0 -#define CFG_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CFG_JFFS2_FIRST_SECTOR 11 - -/* - * following timeouts shall be used once the - * Flash real protection is enabled - */ -#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ -#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ - -/* - * I2C settings - * By default PF2 is used as SDA and PF3 as SCL on the Stamp board - */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF3 -#define PF_SDA PF2 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CFG_I2C_SPEED 50000 -#define CFG_I2C_SLAVE 0xFE - -/* - * Compact Flash settings - */ - -/* Enabled below option for CF support */ -/* #define CONFIG_STAMP_CF 1 */ - -#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) - -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_DOS_PARTITION 1 - -/* - * IDE/ATA stuff - */ -#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ -#undef CONFIG_IDE_LED /* no led for ide supported */ -#undef CONFIG_IDE_RESET /* no reset for ide supported */ - -#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ - -#define CFG_ATA_BASE_ADDR 0x20200000 -#define CFG_ATA_IDE0_OFFSET 0x0000 - -#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */ -#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */ -#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */ - -#define CFG_ATA_STRIDE 2 -#endif - -/* - * SDRAM settings - * - */ - -#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */ -#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */ -#define CONFIG_MEM_MT48LC64M4A2FB_7E 1 - -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */ -#define CFG_LOAD_ADDR 0x01000000 /* default load address */ - -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_MAX_RAM_SIZE 0x08000000 - -#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN) - -#if ( CONFIG_CLKIN_HALF == 0 ) -#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) -#else -#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 ) -#endif - -#if (CONFIG_PLL_BYPASS == 0) -#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV ) -#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV ) -#else -#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ -#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ -#endif - -/* - * Miscellaneous configurable options - */ -#define CFG_HZ 1000 /* 1ms time tick */ - -#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ -#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) -#define CFG_GBL_DATA_SIZE 0x4000 -#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) -#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4) - -#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ - -#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ - -/* - * Stack sizes - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ - -/* - * FLASH organization and environment definitions - */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* 0xFF, 0xBBC3BBc3, 0x99B39983 */ -/*#define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) -#define AMBCTL0VAL (B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \ - B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN) -#define AMBCTL1VAL (B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \ - B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN) -*/ -#define AMGCTLVAL 0xFF -#define AMBCTL0VAL 0xBBC3BBC3 -#define AMBCTL1VAL 0x99B39983 -#define CF_AMBCTL1VAL 0x99B3ffc2 - -#ifdef CONFIG_VDSP -#define ET_EXEC_VDSP 0x8 -#define SHT_STRTAB_VDSP 0x1 -#define ELFSHDRSIZE_VDSP 0x2C -#define VDSP_ENTRY_ADDR 0xFFA00000 -#endif - -#endif diff --git a/include/configs/yellowstone.h b/include/configs/taishan.h index ba27f37f6..2b28f93a0 100644 --- a/include/configs/yellowstone.h +++ b/include/configs/taishan.h @@ -1,10 +1,7 @@ /* - * (C) Copyright 2005-2006 + * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * See file CREDITS for list of people who contributed to this - * project. - * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -12,7 +9,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -22,64 +19,66 @@ */ /************************************************************************ - * yellowstone.h - configuration for YELLOWSTONE board + * TAISHAN.h - configuration for AMCC 440GX Ref ***********************************************************************/ + #ifndef __CONFIG_H #define __CONFIG_H /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_YOLLOWSTONE 1 /* Board is Yellowstone */ -#define CONFIG_440GR 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ +#define CONFIG_TAISHAN 1 /* Board is taishan */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ -#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN) -#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ -#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ -#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 -#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 -#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 - -/*Don't change either of these*/ -#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CFG_PCI_BASE 0xe0000000 /* internal PCI regs*/ -/*Don't change either of these*/ - -#define CFG_USB_DEVICE 0x50000000 -#define CFG_NVRAM_BASE_ADDR 0x80000000 -#define CFG_BCSR_BASE (CFG_NVRAM_BASE_ADDR | 0x2000) -#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE +#define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000) +#define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000) +#define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000) + +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) /*----------------------------------------------------------------------- - * Initial RAM & stack pointer (placed in SDRAM) + * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ -#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ -#define CFG_INIT_RAM_END (8 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ + #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CFG_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ +#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */ +#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -87,70 +86,81 @@ /*----------------------------------------------------------------------- * Environment *----------------------------------------------------------------------*/ -/* - * Define here the location of the environment variables (FLASH or EEPROM). - * Note: DENX encourages to use redundant environment in FLASH. - */ -#if 1 #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#else -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#endif /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_FLASH_CFI /* The flash is CFI compatible */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ +#undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ - -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) -#endif /* CFG_ENV_IS_IN_FLASH */ /*----------------------------------------------------------------------- - * DDR SDRAM + * E2PROM bootstrap configure value *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ -#define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ -#define CFG_SDRAM_BANKS (2) +/* + * 800/133/66 + * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00 + */ + +/* + * 800/160/80 + * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00 + */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ +#define CFG_SDRAM0_TR0 0xC10A401A +#undef CONFIG_SDRAM_ECC /* enable ECC support */ /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_MULTI_EEPROMS -#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#undef CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_BITS 3 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 -#ifdef CFG_ENV_IS_IN_EEPROM -#define CFG_ENV_SIZE 0x200 /* Size of Environment vars */ -#define CFG_ENV_OFFSET 0x0 -#endif /* CFG_ENV_IS_IN_EEPROM */ +#define CFG_BOOTSTRAP_IIC_ADDR 0x50 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ #define CONFIG_PREBOOT "echo;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ @@ -160,14 +170,14 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "hostname=yellowstone\0" \ + "hostname=taishan\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ "flash_nfs=run nfsargs addip addtty;" \ "bootm ${kernel_addr}\0" \ "flash_self=run ramargs addip addtty;" \ @@ -175,14 +185,19 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yellowstone/uImage\0" \ + "bootfile=/tftpboot/taishan/uImage\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "load=tftp 100000 /tftpboot/yellowstone/u-boot.bin\0" \ - "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ + "initrd_high=30000000\0" \ + "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \ + "kozio=bootm 0xffe00000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -193,44 +208,39 @@ #endif #define CONFIG_BAUDRATE 115200 - #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_NET_MULTI 1 /* required for netconsole */ -#define CONFIG_PHY1_ADDR 3 -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ -#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ - +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x1 +#define CONFIG_PHY3_ADDR 0x3 +#define CONFIG_ET1011C_PHY 1 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ #define CONFIG_NETCONSOLE /* include NetConsole support */ -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -#ifdef CONFIG_440EP -/* USB */ -#define CONFIG_USB_OHCI -#define CONFIG_USB_STORAGE - -/*Comment this out to enable USB 1.1 device*/ -#define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ - -#ifdef DEBUG -#define CONFIG_PANIC_HANG -#else -#define CONFIG_HW_WATCHDOG /* watchdog */ -#endif - +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_ASKENV | \ CFG_CMD_DHCP | \ CFG_CMD_DIAG | \ + CFG_CMD_DTT | \ CFG_CMD_ELF | \ CFG_CMD_EEPROM | \ CFG_CMD_I2C | \ @@ -240,15 +250,16 @@ CFG_CMD_NFS | \ CFG_CMD_PCI | \ CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM) + CFG_CMD_REGINFO) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -/* +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- * Miscellaneous configurable options - */ + *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) @@ -260,14 +271,13 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_LYNXKDI 1 /* support kdi files */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ @@ -280,18 +290,18 @@ *----------------------------------------------------------------------- */ /* General PCI */ -#define CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ -#define CFG_PCI_TARGET_INIT -#define CFG_PCI_MASTER_INIT +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ -#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ /* * For booting Linux, the board info and command line data @@ -302,8 +312,8 @@ /*----------------------------------------------------------------------- * Cache Configuration - */ -#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ @@ -321,5 +331,4 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - #endif /* __CONFIG_H */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h new file mode 100644 index 000000000..8cd8e9be7 --- /dev/null +++ b/include/configs/uc101.h @@ -0,0 +1,353 @@ +/* + * (C) Copyright 2003-2006 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_UC101 1 /* UC101 board */ + +#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CONFIG_BOARD_EARLY_INIT_R + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DATE | \ + CFG_CMD_DISPLAY | \ + CFG_CMD_DHCP | \ + CFG_CMD_PING | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_DTT | \ + CFG_CMD_IDE | \ + CFG_CMD_FAT | \ + CFG_CMD_NFS | \ + CFG_CMD_MII | \ + CFG_CMD_SNTP ) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +#if (TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CFG_LOWBOOT 1 +#endif + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addwdt=setenv bootargs ${bootargs} wdt=off" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_MISC_INIT_R 1 + +/* + * IPB Bus clocking configuration. + */ +#define CFG_IPBSPEED_133 /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CFG_I2C_SPEED 100000 /* 100 kHz */ +#define CFG_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CFG_I2C_EEPROM_ADDR 0x58 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +/* for LM81 */ +#define CFG_EEPROM_PAGE_WRITE_ENABLE + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/* + * Flash configuration + */ +#define CFG_FLASH_BASE 0xFF800000 + +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_MAX_FLASH_SECT 140 /* max num of sects on one chip */ + +#define CFG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ + +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_CFI +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x4000 +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SRAM_BASE 0x80100000 /* CS 1 */ +#define CFG_DISPLAY_BASE 0x80600000 /* CS 3 */ +#define CFG_IB_MASTER 0xc0510000 /* CS 6 */ +#define CFG_IB_EPLD 0xc0500000 /* CS 7 */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* SRAM */ +#define SRAM_BASE CFG_SRAM_BASE /* SRAM base address */ +#define SRAM_LEN 0x1fffff +#define SRAM_END (SRAM_BASE + SRAM_LEN) + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +# define CFG_RAMBOOT 1 +#endif + +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ +#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/* + * GPIO configuration + */ +#define CFG_GPS_PORT_CONFIG 0x4d558044 + +/*use Hardware WDT */ +#define CONFIG_HW_WATCHDOG + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +/* Enable an alternate, more extensive memory test */ +#define CFG_ALT_MEMTEST + +#define CFG_MEMTEST_START 0x00300000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x300000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +/* + * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, + * which is normally part of the default commands (CFV_CMD_DFL) + */ +#define CONFIG_LOOPW + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE +#else +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL 0 +#endif + +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00045D00 +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CFG_CS1_START CFG_SRAM_BASE +#define CFG_CS1_SIZE 0x00100000 +#define CFG_CS1_CFG 0x21D00 + +/* Display H1, Status Inputs, EPLD @0x80600000 8 Bit */ +#define CFG_CS3_START CFG_DISPLAY_BASE +#define CFG_CS3_SIZE 0x00000100 +#define CFG_CS3_CFG 0x00081802 + +/* Interbus Master 16 Bit */ +#define CFG_CS6_START CFG_IB_MASTER +#define CFG_CS6_SIZE 0x00010000 +#define CFG_CS6_CFG 0x00FF3500 + +/* Interbus EPLD 8 Bit */ +#define CFG_CS7_START CFG_IB_EPLD +#define CFG_CS7_SIZE 0x00010000 +#define CFG_CS7_CFG 0x00081800 + +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ + +#define CONFIG_IDE_PREINIT 1 +/* #define CONFIG_IDE_RESET 1 beispile siehe tqm5200.c */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CFG_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +/*---------------------------------------------------------------------*/ +/* Display addresses */ +/*---------------------------------------------------------------------*/ +#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38) +#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30) + +#endif /* __CONFIG_H */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 554a7a41b..e19591d29 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -39,6 +39,7 @@ #define CONFIG_NETCONSOLE 1 #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ #define CFG_XLB_PIPELINING 1 /* gives better performance */ @@ -101,7 +102,7 @@ CFG_CMD_IRQ | \ CFG_CMD_JFFS2 | \ CFG_CMD_MII | \ - CFG_CMD_SDRAMi | \ + CFG_CMD_SDRAM | \ CFG_CMD_DATE | \ CFG_CMD_USB | \ CFG_CMD_FAT) @@ -135,7 +136,7 @@ "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ "filesystem over NFS; echo\0" \ "netdev=eth0\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ "addip=setenv bootargs $(bootargs) " \ "ip=$(ipaddr):$(serverip):$(gatewayip):" \ "$(netmask):$(hostname):$(netdev):off panic=1\0" \ @@ -144,7 +145,7 @@ "$(ramdisk_addr)\0" \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath)\0" \ + "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ "hostname=v38b\0" \ "ethact=FEC ETHERNET\0" \ "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 28abd6e15..b34dc71d2 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -68,6 +68,7 @@ "bootfile=/tftpboot/walnut/uImage\0" \ "kernel_addr=fff80000\0" \ "ramdisk_addr=fff80000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 /tftpboot/walnut/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 9f98500a6..b59f75b9d 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2006 + * (C) Copyright 2005-2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -22,7 +22,7 @@ */ /************************************************************************ - * yosemite.h - configuration for YOSEMITE board + * yosemite.h - configuration for Yosemite & Yellowstone boards ***********************************************************************/ #ifndef __CONFIG_H #define __CONFIG_H @@ -30,13 +30,21 @@ /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ -#define CONFIG_440EP 1 /* Specific PPC440EP support */ -#define CONFIG_4xx 1 /* ... PPC4xx family */ +/* This config file is used for Yosemite (440EP) and Yellowstone (440GR)*/ +#ifndef CONFIG_YELLOWSTONE +#define CONFIG_YOSEMITE 1 /* Board is Yosemite */ +#define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_HOSTNAME yosemite +#else +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME yellowstone +#endif +#define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ +#define CONFIG_BOARD_RESET 1 /* call board_reset() */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -158,9 +166,21 @@ #undef CONFIG_BOOTARGS +/* Setup some board specific values for the default environment variables */ +#ifndef CONFIG_YELLOWSTONE +#define CONFIG_HOSTNAME yosemite +#define CFG_BOOTFILE "bootfile=/tftpboot/yosemite/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" +#else +#define CONFIG_HOSTNAME yellowstone +#define CFG_BOOTFILE "bootfile=/tftpboot/yellowstone/uImage\0" +#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xx\0" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + CFG_BOOTFILE \ + CFG_ROOTPATH \ "netdev=eth0\0" \ - "hostname=yosemite\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -174,13 +194,12 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ - "bootfile=/tftpboot/yosemite/uImage\0" \ + "bootfile=/tftpboot/${hostname}/uImage\0" \ "kernel_addr=fc000000\0" \ "ramdisk_addr=fc180000\0" \ - "load=tftp 100000 /tftpboot/yosemite/u-boot.bin\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ - "cp.b 100000 fff80000 80000;" \ + "cp.b 200000 fff80000 80000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ "" @@ -223,9 +242,15 @@ #define CFG_USB_OHCI_SLOT_NAME "ppc440" #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 -/*Comment this out to enable USB 1.1 device*/ +/* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE -#endif /*CONFIG_440EP*/ + +#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2) + +#define CONFIG_SUPPORT_VFAT +#else +#define CMD_USB 0 /* no USB on 440GR */ +#endif /* CONFIG_440EP */ #ifdef DEBUG #define CONFIG_PANIC_HANG @@ -248,11 +273,7 @@ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ CFG_CMD_SDRAM | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_USB ) - -#define CONFIG_SUPPORT_VFAT + CMD_USB) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> @@ -312,6 +333,20 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE +#define CFG_CPLD 0x80000000 + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03017300 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xda000) + +/* Memory Bank 2 (CPLD) initialization */ +#define CFG_EBC_PB2AP 0x04814500 +#define CFG_EBC_PB2CR (CFG_CPLD | 0x18000) + +/*----------------------------------------------------------------------- * Cache Configuration */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index a6532b5e8..eb4859c3e 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -45,11 +45,11 @@ #define EXTCLK_50 50000000 #define EXTCLK_83 83333333 -#define CONFIG_IBM_EMAC4_V4 1 -#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ #undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_STRESS -#undef ENABLE_ECC + /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -118,10 +118,9 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ -#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses */ -#define IIC0_DIMM0_ADDR 0x53 -#define IIC0_DIMM1_ADDR 0x52 +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/ +#undef CONFIG_DDR_ECC /* no ECC support for now */ /*----------------------------------------------------------------------- * I2C @@ -178,6 +177,7 @@ "bootfile=yucca/uImage\0" \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ + "initrd_high=30000000\0" \ "load=tftp 100000 yuca/u-boot.bin\0" \ "update=protect off 2:4-7;era 2:4-7;" \ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ @@ -210,6 +210,7 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> +#define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ #undef CONFIG_NET_MULTI #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |