diff options
Diffstat (limited to 'include')
43 files changed, 1383 insertions, 148 deletions
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h index c91e30c8f..8fd4e01b8 100644 --- a/include/asm-arm/arch-davinci/emif_defs.h +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -51,10 +51,7 @@ typedef struct { dv_reg NANDFCR; dv_reg NANDFSR; u_int8_t RSVD1[8]; - dv_reg NANDF1ECC; - dv_reg NANDF2ECC; - dv_reg NANDF3ECC; - dv_reg NANDF4ECC; + dv_reg NANDFECC[4]; u_int8_t RSVD2[60]; dv_reg NAND4BITECCLOAD; dv_reg NAND4BITECC1; @@ -68,4 +65,12 @@ typedef struct { } emif_registers; typedef emif_registers *emifregs; + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << (n-2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) ((n-2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + (n-2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) + #endif diff --git a/include/asm-arm/arch-davinci/gpio_defs.h b/include/asm-arm/arch-davinci/gpio_defs.h index ff629761b..1be2ac266 100644 --- a/include/asm-arm/arch-davinci/gpio_defs.h +++ b/include/asm-arm/arch-davinci/gpio_defs.h @@ -22,12 +22,21 @@ #ifndef _GPIO_DEFS_H_ #define _GPIO_DEFS_H_ +#ifndef CONFIG_SOC_DA8XX #define DAVINCI_GPIO_BINTEN 0x01C67008 #define DAVINCI_GPIO_BANK01 0x01C67010 #define DAVINCI_GPIO_BANK23 0x01C67038 #define DAVINCI_GPIO_BANK45 0x01C67060 #define DAVINCI_GPIO_BANK67 0x01C67088 +#else /* CONFIG_SOC_DA8XX */ +#define DAVINCI_GPIO_BINTEN 0x01E26008 +#define DAVINCI_GPIO_BANK01 0x01E26010 +#define DAVINCI_GPIO_BANK23 0x01E26038 +#define DAVINCI_GPIO_BANK45 0x01E26060 +#define DAVINCI_GPIO_BANK67 0x01E26088 +#endif /* CONFIG_SOC_DA8XX */ + struct davinci_gpio { unsigned int dir; unsigned int out_data; @@ -49,4 +58,9 @@ struct davinci_gpio_bank { unsigned long base; }; +#define davinci_gpio_bank01 ((struct davinci_gpio *)DAVINCI_GPIO_BANK01) +#define davinci_gpio_bank23 ((struct davinci_gpio *)DAVINCI_GPIO_BANK23) +#define davinci_gpio_bank45 ((struct davinci_gpio *)DAVINCI_GPIO_BANK45) +#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67) + #endif diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index f1f7d932a..289861858 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1772,7 +1772,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_WDG002 1785 #define MACH_TYPE_SG560ADSL 1786 #define MACH_TYPE_NEXTIO_N2800_ICA 1787 -#define MACH_TYPE_MACH_MARVELL_NEW1 1788 +#define MACH_TYPE_DOVE_DB 1788 #define MACH_TYPE_MARVELL_NEWDB 1789 #define MACH_TYPE_VANDIHUD 1790 #define MACH_TYPE_MAGX_E8 1791 @@ -2532,7 +2532,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_C3AX03 2549 #define MACH_TYPE_MXT_TD60 2550 #define MACH_TYPE_ESYX 2551 -#define MACH_TYPE_DOVE_DB 2552 +#define MACH_TYPE_DOVE_DB2 2552 #define MACH_TYPE_BULLDOG 2553 #define MACH_TYPE_DERELL_ME2000 2554 #define MACH_TYPE_BCMRING_BASE 2555 @@ -2547,6 +2547,53 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_BCMRING_SP_WQVGA 2564 #define MACH_TYPE_BCMRING_CUSTOM 2565 #define MACH_TYPE_ACER_S200 2566 +#define MACH_TYPE_BT270 2567 +#define MACH_TYPE_ISEO 2568 +#define MACH_TYPE_CEZANNE 2569 +#define MACH_TYPE_LUCCA 2570 +#define MACH_TYPE_SUPERSMART 2571 +#define MACH_TYPE_CS_MISANO 2572 +#define MACH_TYPE_MAGNOLIA2 2573 +#define MACH_TYPE_EMXX 2574 +#define MACH_TYPE_OUTLAW 2575 +#define MACH_TYPE_RIOT_BEI2 2576 +#define MACH_TYPE_RIOT_VOX 2577 +#define MACH_TYPE_RIOT_X37 2578 +#define MACH_TYPE_MEGA25MX 2579 +#define MACH_TYPE_BENZINA2 2580 +#define MACH_TYPE_IGNITE 2581 +#define MACH_TYPE_FOGGIA 2582 +#define MACH_TYPE_AREZZO 2583 +#define MACH_TYPE_LEICA_SKYWALKER 2584 +#define MACH_TYPE_JACINTO2_JAMR 2585 +#define MACH_TYPE_GTS_NOVA 2586 +#define MACH_TYPE_P3600 2587 +#define MACH_TYPE_DLT2 2588 +#define MACH_TYPE_DF3120 2589 +#define MACH_TYPE_ECUCORE_9G20 2590 +#define MACH_TYPE_NAUTEL_LPC3240 2591 +#define MACH_TYPE_GLACIER 2592 +#define MACH_TYPE_PHRAZER_BULLDOG 2593 +#define MACH_TYPE_OMAP3_BULLDOG 2594 +#define MACH_TYPE_PCA101 2595 +#define MACH_TYPE_BUZZC 2596 +#define MACH_TYPE_SASIE2 2597 +#define MACH_TYPE_DAVINCI_CIO 2598 +#define MACH_TYPE_SMARTMETER_DL 2599 +#define MACH_TYPE_WZL6410 2600 +#define MACH_TYPE_WZL6410M 2601 +#define MACH_TYPE_WZL6410F 2602 +#define MACH_TYPE_WZL6410I 2603 +#define MACH_TYPE_SPACECOM1 2604 +#define MACH_TYPE_PINGU920 2605 +#define MACH_TYPE_BRAVOC 2606 +#define MACH_TYPE_CYBO2440 2607 +#define MACH_TYPE_VDSSW 2608 +#define MACH_TYPE_ROMULUS 2609 +#define MACH_TYPE_OMAP_MAGIC 2610 +#define MACH_TYPE_ELTD100 2611 +#define MACH_TYPE_CAPC7117 2612 +#define MACH_TYPE_SWAN 2613 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -23668,14 +23715,14 @@ extern unsigned int __machine_arch_type; # define machine_is_nextio_n2800_ica() (0) #endif -#ifdef CONFIG_MACH_MACH_MARVELL_NEW1 +#ifdef CONFIG_MACH_DOVE_DB # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_MACH_MARVELL_NEW1 +# define machine_arch_type MACH_TYPE_DOVE_DB # endif -# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_MACH_MARVELL_NEW1) +# define machine_is_dove_db() (machine_arch_type == MACH_TYPE_DOVE_DB) #else # define machine_is_dove_db() (0) #endif @@ -30851,9 +30898,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_SIENNA # endif -# define machine_is_sienna() (machine_arch_type == MACH_TYPE_SIENNA) +# define machine_is_siena() (machine_arch_type == MACH_TYPE_SIENNA) #else -# define machine_is_sienna() (0) +# define machine_is_siena() (0) #endif #ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 @@ -32788,14 +32835,14 @@ extern unsigned int __machine_arch_type; # define machine_is_esyx() (0) #endif -#ifdef CONFIG_MACH_DOVE_DB +#ifdef CONFIG_MACH_DOVE_DB2 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DOVE_DB +# define machine_arch_type MACH_TYPE_DOVE_DB2 # endif -# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB) +# define machine_is_dove_db2() (machine_arch_type == MACH_TYPE_DOVE_DB2) #else # define machine_is_dove_db2() (0) #endif @@ -32968,6 +33015,570 @@ extern unsigned int __machine_arch_type; # define machine_is_acer_s200() (0) #endif +#ifdef CONFIG_MACH_BT270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BT270 +# endif +# define machine_is_bt270() (machine_arch_type == MACH_TYPE_BT270) +#else +# define machine_is_bt270() (0) +#endif + +#ifdef CONFIG_MACH_ISEO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISEO +# endif +# define machine_is_iseo() (machine_arch_type == MACH_TYPE_ISEO) +#else +# define machine_is_iseo() (0) +#endif + +#ifdef CONFIG_MACH_CEZANNE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEZANNE +# endif +# define machine_is_cezanne() (machine_arch_type == MACH_TYPE_CEZANNE) +#else +# define machine_is_cezanne() (0) +#endif + +#ifdef CONFIG_MACH_LUCCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LUCCA +# endif +# define machine_is_lucca() (machine_arch_type == MACH_TYPE_LUCCA) +#else +# define machine_is_lucca() (0) +#endif + +#ifdef CONFIG_MACH_SUPERSMART +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUPERSMART +# endif +# define machine_is_supersmart() (machine_arch_type == MACH_TYPE_SUPERSMART) +#else +# define machine_is_supersmart() (0) +#endif + +#ifdef CONFIG_MACH_CS_MISANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CS_MISANO +# endif +# define machine_is_arm11_board() (machine_arch_type == MACH_TYPE_CS_MISANO) +#else +# define machine_is_arm11_board() (0) +#endif + +#ifdef CONFIG_MACH_MAGNOLIA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGNOLIA2 +# endif +# define machine_is_magnolia2() (machine_arch_type == MACH_TYPE_MAGNOLIA2) +#else +# define machine_is_magnolia2() (0) +#endif + +#ifdef CONFIG_MACH_EMXX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMXX +# endif +# define machine_is_emxx() (machine_arch_type == MACH_TYPE_EMXX) +#else +# define machine_is_emxx() (0) +#endif + +#ifdef CONFIG_MACH_OUTLAW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OUTLAW +# endif +# define machine_is_outlaw() (machine_arch_type == MACH_TYPE_OUTLAW) +#else +# define machine_is_outlaw() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_BEI2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_BEI2 +# endif +# define machine_is_riot_bei2() (machine_arch_type == MACH_TYPE_RIOT_BEI2) +#else +# define machine_is_riot_bei2() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_VOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_VOX +# endif +# define machine_is_riot_vox() (machine_arch_type == MACH_TYPE_RIOT_VOX) +#else +# define machine_is_riot_vox() (0) +#endif + +#ifdef CONFIG_MACH_RIOT_X37 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOT_X37 +# endif +# define machine_is_riot_x37() (machine_arch_type == MACH_TYPE_RIOT_X37) +#else +# define machine_is_riot_x37() (0) +#endif + +#ifdef CONFIG_MACH_MEGA25MX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEGA25MX +# endif +# define machine_is_mega25mx() (machine_arch_type == MACH_TYPE_MEGA25MX) +#else +# define machine_is_mega25mx() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA2 +# endif +# define machine_is_benzina2() (machine_arch_type == MACH_TYPE_BENZINA2) +#else +# define machine_is_benzina2() (0) +#endif + +#ifdef CONFIG_MACH_IGNITE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGNITE +# endif +# define machine_is_ignite() (machine_arch_type == MACH_TYPE_IGNITE) +#else +# define machine_is_ignite() (0) +#endif + +#ifdef CONFIG_MACH_FOGGIA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FOGGIA +# endif +# define machine_is_foggia() (machine_arch_type == MACH_TYPE_FOGGIA) +#else +# define machine_is_foggia() (0) +#endif + +#ifdef CONFIG_MACH_AREZZO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AREZZO +# endif +# define machine_is_arezzo() (machine_arch_type == MACH_TYPE_AREZZO) +#else +# define machine_is_arezzo() (0) +#endif + +#ifdef CONFIG_MACH_LEICA_SKYWALKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEICA_SKYWALKER +# endif +# define machine_is_leica_skywalker() (machine_arch_type == MACH_TYPE_LEICA_SKYWALKER) +#else +# define machine_is_leica_skywalker() (0) +#endif + +#ifdef CONFIG_MACH_JACINTO2_JAMR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JACINTO2_JAMR +# endif +# define machine_is_jacinto2_jamr() (machine_arch_type == MACH_TYPE_JACINTO2_JAMR) +#else +# define machine_is_jacinto2_jamr() (0) +#endif + +#ifdef CONFIG_MACH_GTS_NOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GTS_NOVA +# endif +# define machine_is_gts_nova() (machine_arch_type == MACH_TYPE_GTS_NOVA) +#else +# define machine_is_gts_nova() (0) +#endif + +#ifdef CONFIG_MACH_P3600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_P3600 +# endif +# define machine_is_p3600() (machine_arch_type == MACH_TYPE_P3600) +#else +# define machine_is_p3600() (0) +#endif + +#ifdef CONFIG_MACH_DLT2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DLT2 +# endif +# define machine_is_dlt2() (machine_arch_type == MACH_TYPE_DLT2) +#else +# define machine_is_dlt2() (0) +#endif + +#ifdef CONFIG_MACH_DF3120 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DF3120 +# endif +# define machine_is_df3120() (machine_arch_type == MACH_TYPE_DF3120) +#else +# define machine_is_df3120() (0) +#endif + +#ifdef CONFIG_MACH_ECUCORE_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECUCORE_9G20 +# endif +# define machine_is_ecucore_9g20() (machine_arch_type == MACH_TYPE_ECUCORE_9G20) +#else +# define machine_is_ecucore_9g20() (0) +#endif + +#ifdef CONFIG_MACH_NAUTEL_LPC3240 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAUTEL_LPC3240 +# endif +# define machine_is_nautel_lpc3240() (machine_arch_type == MACH_TYPE_NAUTEL_LPC3240) +#else +# define machine_is_nautel_lpc3240() (0) +#endif + +#ifdef CONFIG_MACH_GLACIER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GLACIER +# endif +# define machine_is_glacier() (machine_arch_type == MACH_TYPE_GLACIER) +#else +# define machine_is_glacier() (0) +#endif + +#ifdef CONFIG_MACH_PHRAZER_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHRAZER_BULLDOG +# endif +# define machine_is_phrazer_bulldog() (machine_arch_type == MACH_TYPE_PHRAZER_BULLDOG) +#else +# define machine_is_phrazer_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_BULLDOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_BULLDOG +# endif +# define machine_is_omap3_bulldog() (machine_arch_type == MACH_TYPE_OMAP3_BULLDOG) +#else +# define machine_is_omap3_bulldog() (0) +#endif + +#ifdef CONFIG_MACH_PCA101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA101 +# endif +# define machine_is_pca101() (machine_arch_type == MACH_TYPE_PCA101) +#else +# define machine_is_pca101() (0) +#endif + +#ifdef CONFIG_MACH_BUZZC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BUZZC +# endif +# define machine_is_buzzc() (machine_arch_type == MACH_TYPE_BUZZC) +#else +# define machine_is_buzzc() (0) +#endif + +#ifdef CONFIG_MACH_SASIE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SASIE2 +# endif +# define machine_is_sasie2() (machine_arch_type == MACH_TYPE_SASIE2) +#else +# define machine_is_sasie2() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_CIO +# endif +# define machine_is_davinci_cio() (machine_arch_type == MACH_TYPE_DAVINCI_CIO) +#else +# define machine_is_davinci_cio() (0) +#endif + +#ifdef CONFIG_MACH_SMARTMETER_DL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMARTMETER_DL +# endif +# define machine_is_smartmeter_dl() (machine_arch_type == MACH_TYPE_SMARTMETER_DL) +#else +# define machine_is_smartmeter_dl() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410 +# endif +# define machine_is_wzl6410() (machine_arch_type == MACH_TYPE_WZL6410) +#else +# define machine_is_wzl6410() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410M +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410M +# endif +# define machine_is_wzl6410m() (machine_arch_type == MACH_TYPE_WZL6410M) +#else +# define machine_is_wzl6410m() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410F +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410F +# endif +# define machine_is_wzl6410f() (machine_arch_type == MACH_TYPE_WZL6410F) +#else +# define machine_is_wzl6410f() (0) +#endif + +#ifdef CONFIG_MACH_WZL6410I +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL6410I +# endif +# define machine_is_wzl6410i() (machine_arch_type == MACH_TYPE_WZL6410I) +#else +# define machine_is_wzl6410i() (0) +#endif + +#ifdef CONFIG_MACH_SPACECOM1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPACECOM1 +# endif +# define machine_is_spacecom1() (machine_arch_type == MACH_TYPE_SPACECOM1) +#else +# define machine_is_spacecom1() (0) +#endif + +#ifdef CONFIG_MACH_PINGU920 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PINGU920 +# endif +# define machine_is_pingu920() (machine_arch_type == MACH_TYPE_PINGU920) +#else +# define machine_is_pingu920() (0) +#endif + +#ifdef CONFIG_MACH_BRAVOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BRAVOC +# endif +# define machine_is_bravoc() (machine_arch_type == MACH_TYPE_BRAVOC) +#else +# define machine_is_bravoc() (0) +#endif + +#ifdef CONFIG_MACH_CYBO2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYBO2440 +# endif +# define machine_is_cybo2440() (machine_arch_type == MACH_TYPE_CYBO2440) +#else +# define machine_is_cybo2440() (0) +#endif + +#ifdef CONFIG_MACH_VDSSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VDSSW +# endif +# define machine_is_vdssw() (machine_arch_type == MACH_TYPE_VDSSW) +#else +# define machine_is_vdssw() (0) +#endif + +#ifdef CONFIG_MACH_ROMULUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ROMULUS +# endif +# define machine_is_romulus() (machine_arch_type == MACH_TYPE_ROMULUS) +#else +# define machine_is_romulus() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_MAGIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_MAGIC +# endif +# define machine_is_omap_magic() (machine_arch_type == MACH_TYPE_OMAP_MAGIC) +#else +# define machine_is_omap_magic() (0) +#endif + +#ifdef CONFIG_MACH_ELTD100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELTD100 +# endif +# define machine_is_eltd100() (machine_arch_type == MACH_TYPE_ELTD100) +#else +# define machine_is_eltd100() (0) +#endif + +#ifdef CONFIG_MACH_CAPC7117 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAPC7117 +# endif +# define machine_is_capc7117() (machine_arch_type == MACH_TYPE_CAPC7117) +#else +# define machine_is_capc7117() (0) +#endif + +#ifdef CONFIG_MACH_SWAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWAN +# endif +# define machine_is_swan() (machine_arch_type == MACH_TYPE_SWAN) +#else +# define machine_is_swan() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/asm-blackfin/mach-common/bits/usb.h b/include/asm-blackfin/mach-common/bits/usb.h new file mode 100644 index 000000000..c6390589b --- /dev/null +++ b/include/asm-blackfin/mach-common/bits/usb.h @@ -0,0 +1,264 @@ +/* + * USB Masks + */ + +#ifndef __BFIN_PERIPHERAL_USB__ +#define __BFIN_PERIPHERAL_USB__ + +/* Bit masks for USB_FADDR */ + +#define FUNCTION_ADDRESS 0x7f /* Function address */ + +/* Bit masks for USB_POWER */ + +#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */ +#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */ +#define RESUME_MODE 0x4 /* DMA Mode */ +#define RESET 0x8 /* Reset indicator */ +#define HS_MODE 0x10 /* High Speed mode indicator */ +#define HS_ENABLE 0x20 /* high Speed Enable */ +#define SOFT_CONN 0x40 /* Soft connect */ +#define ISO_UPDATE 0x80 /* Isochronous update */ + +/* Bit masks for USB_INTRTX */ + +#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */ +#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */ +#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */ +#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */ +#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */ +#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */ +#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */ +#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRRX */ + +#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */ +#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */ +#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */ +#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */ +#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */ +#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */ +#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */ + +/* Bit masks for USB_INTRTXE */ + +#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */ +#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt enable */ +#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt enable */ +#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt enable */ +#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt enable */ +#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt enable */ +#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt enable */ +#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt enable */ + +/* Bit masks for USB_INTRRXE */ + +#define EP1_RX_E 0x02 /* Rx Endpoint 1 interrupt enable */ +#define EP2_RX_E 0x04 /* Rx Endpoint 2 interrupt enable */ +#define EP3_RX_E 0x08 /* Rx Endpoint 3 interrupt enable */ +#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt enable */ +#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt enable */ +#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt enable */ +#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt enable */ + +/* Bit masks for USB_INTRUSB */ + +#define SUSPEND_B 0x01 /* Suspend indicator */ +#define RESUME_B 0x02 /* Resume indicator */ +#define RESET_OR_BABLE_B 0x04 /* Reset/babble indicator */ +#define SOF_B 0x08 /* Start of frame */ +#define CONN_B 0x10 /* Connection indicator */ +#define DISCON_B 0x20 /* Disconnect indicator */ +#define SESSION_REQ_B 0x40 /* Session Request */ +#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */ + +/* Bit masks for USB_INTRUSBE */ + +#define SUSPEND_BE 0x01 /* Suspend indicator int enable */ +#define RESUME_BE 0x02 /* Resume indicator int enable */ +#define RESET_OR_BABLE_BE 0x04 /* Reset/babble indicator int enable */ +#define SOF_BE 0x08 /* Start of frame int enable */ +#define CONN_BE 0x10 /* Connection indicator int enable */ +#define DISCON_BE 0x20 /* Disconnect indicator int enable */ +#define SESSION_REQ_BE 0x40 /* Session Request int enable */ +#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */ + +/* Bit masks for USB_FRAME */ + +#define FRAME_NUMBER 0x7ff /* Frame number */ + +/* Bit masks for USB_INDEX */ + +#define SELECTED_ENDPOINT 0xf /* selected endpoint */ + +/* Bit masks for USB_GLOBAL_CTL */ + +#define GLOBAL_ENA 0x0001 /* enables USB module */ +#define EP1_TX_ENA 0x0002 /* Transmit endpoint 1 enable */ +#define EP2_TX_ENA 0x0004 /* Transmit endpoint 2 enable */ +#define EP3_TX_ENA 0x0008 /* Transmit endpoint 3 enable */ +#define EP4_TX_ENA 0x0010 /* Transmit endpoint 4 enable */ +#define EP5_TX_ENA 0x0020 /* Transmit endpoint 5 enable */ +#define EP6_TX_ENA 0x0040 /* Transmit endpoint 6 enable */ +#define EP7_TX_ENA 0x0080 /* Transmit endpoint 7 enable */ +#define EP1_RX_ENA 0x0100 /* Receive endpoint 1 enable */ +#define EP2_RX_ENA 0x0200 /* Receive endpoint 2 enable */ +#define EP3_RX_ENA 0x0400 /* Receive endpoint 3 enable */ +#define EP4_RX_ENA 0x0800 /* Receive endpoint 4 enable */ +#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */ +#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */ +#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */ + +/* Bit masks for USB_OTG_DEV_CTL */ + +#define SESSION 0x1 /* session indicator */ +#define HOST_REQ 0x2 /* Host negotiation request */ +#define HOST_MODE 0x4 /* indicates USBDRC is a host */ +#define VBUS0 0x8 /* Vbus level indicator[0] */ +#define VBUS1 0x10 /* Vbus level indicator[1] */ +#define LSDEV 0x20 /* Low-speed indicator */ +#define FSDEV 0x40 /* Full or High-speed indicator */ +#define B_DEVICE 0x80 /* A' or 'B' device indicator */ + +/* Bit masks for USB_OTG_VBUS_IRQ */ + +#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */ +#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */ +#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */ +#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */ +#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */ +#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */ + +/* Bit masks for USB_OTG_VBUS_MASK */ + +#define DRIVE_VBUS_ON_ENA 0x01 /* enable DRIVE_VBUS_ON interrupt */ +#define DRIVE_VBUS_OFF_ENA 0x02 /* enable DRIVE_VBUS_OFF interrupt */ +#define CHRG_VBUS_START_ENA 0x04 /* enable CHRG_VBUS_START interrupt */ +#define CHRG_VBUS_END_ENA 0x08 /* enable CHRG_VBUS_END interrupt */ +#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */ +#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */ + +/* Bit masks for USB_CSR0 */ + +#define RXPKTRDY 0x1 /* data packet receive indicator */ +#define TXPKTRDY 0x2 /* data packet in FIFO indicator */ +#define STALL_SENT 0x4 /* STALL handshake sent */ +#define DATAEND 0x8 /* Data end indicator */ +#define SETUPEND 0x10 /* Setup end */ +#define SENDSTALL 0x20 /* Send STALL handshake */ +#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */ +#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */ +#define FLUSHFIFO 0x100 /* flush endpoint FIFO */ +#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */ +#define SETUPPKT_H 0x8 /* send Setup token host mode */ +#define ERROR_H 0x10 /* timeout error indicator host mode */ +#define REQPKT_H 0x20 /* Request an IN transaction host mode */ +#define STATUSPKT_H 0x40 /* Status stage transaction host mode */ +#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */ + +/* Bit masks for USB_COUNT0 */ + +#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */ + +/* Bit masks for USB_NAKLIMIT0 */ + +#define EP0_NAK_LIMIT 0x1f /* frames/micro frames count after which EP0 timeouts */ + +/* Bit masks for USB_TX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_RX_MAX_PACKET */ + +#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */ + +/* Bit masks for USB_TXCSR */ + +#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */ +#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */ +#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */ +#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */ +#define STALL_SEND_T 0x10 /* issue a Stall handshake */ +#define STALL_SENT_T 0x20 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */ +#define INCOMPTX_T 0x80 /* indicates that a large packet is split */ +#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */ +#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */ +#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */ +#define ISO_T 0x4000 /* enable Isochronous transfers */ +#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_TH 0x4 /* error condition host mode */ +#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */ +#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */ + +/* Bit masks for USB_TXCOUNT */ + +#define TX_COUNT 0x1fff /* Byte len for the selected endpoint Tx FIFO */ + +/* Bit masks for USB_RXCSR */ + +#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */ +#define FIFO_FULL_R 0x2 /* FIFO not empty */ +#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */ +#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */ +#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */ +#define STALL_SEND_R 0x20 /* issue a Stall handshake */ +#define STALL_SENT_R 0x40 /* Stall handshake transmitted */ +#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */ +#define INCOMPRX_R 0x100 /* indicates that a large packet is split */ +#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */ +#define DISNYET_R 0x1000 /* disable Nyet handshakes */ +#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */ +#define ISO_R 0x4000 /* enable Isochronous transfers */ +#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */ +#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */ +#define REQPKT_RH 0x20 /* request an IN transaction host mode */ +#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */ +#define INCOMPRX_RH 0x100 /* large packet is split host mode */ +#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */ +#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */ + +/* Bit masks for USB_RXCOUNT */ + +#define RX_COUNT 0x1fff /* Packet byte len in the Rx FIFO */ + +/* Bit masks for USB_TXTYPE */ + +#define TARGET_EP_NO_T 0xf /* EP number */ +#define PROTOCOL_T 0xc /* transfer type */ + +/* Bit masks for USB_TXINTERVAL */ + +#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */ + +/* Bit masks for USB_RXTYPE */ + +#define TARGET_EP_NO_R 0xf /* EP number */ +#define PROTOCOL_R 0xc /* transfer type */ + +/* Bit masks for USB_RXINTERVAL */ + +#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */ + +/* Bit masks for USB_DMA_INTERRUPT */ + +#define DMA0_INT 0x1 /* DMA0 pending interrupt */ +#define DMA1_INT 0x2 /* DMA1 pending interrupt */ +#define DMA2_INT 0x4 /* DMA2 pending interrupt */ +#define DMA3_INT 0x8 /* DMA3 pending interrupt */ +#define DMA4_INT 0x10 /* DMA4 pending interrupt */ +#define DMA5_INT 0x20 /* DMA5 pending interrupt */ +#define DMA6_INT 0x40 /* DMA6 pending interrupt */ +#define DMA7_INT 0x80 /* DMA7 pending interrupt */ + +/* Bit masks for USB_DMAxCONTROL */ + +#define DMA_ENA 0x1 /* DMA enable */ +#define DIRECTION 0x2 /* direction of DMA transfer */ +#define MODE 0x4 /* DMA Bus error */ +#define INT_ENA 0x8 /* Interrupt enable */ +#define EPNUM 0xf0 /* EP number */ +#define BUSERROR 0x100 /* DMA Bus error */ + +#endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index af0853b0d..796707eaf 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -57,6 +57,19 @@ #endif #endif +/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */ +#if defined(CONFIG_TSEC_ENET) && \ + (defined(CONFIG_P1020) || defined(CONFIG_P1011)) +#define CONFIG_TSECV2 +#endif + +/* Number of TLB CAM entries we have on FSL Book-E chips */ +#if defined(CONFIG_E500MC) +#define CONFIG_SYS_NUM_TLBCAMS 64 +#elif defined(CONFIG_E500) +#define CONFIG_SYS_NUM_TLBCAMS 16 +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 69b857b41..3216a5063 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -1,5 +1,5 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2008-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -177,6 +177,11 @@ typedef struct memctl_options_s { unsigned int clk_adjust; /* */ unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + + unsigned int wrlvl_override; + unsigned int wrlvl_sample; /* Write leveling */ + unsigned int wrlvl_start; + unsigned int half_strength_driver_enable; unsigned int twoT_en; unsigned int threeT_en; @@ -187,6 +192,7 @@ typedef struct memctl_options_s { /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ /* Automatic self refresh */ unsigned int auto_self_refresh_en; diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 31bb7545b..34c56a259 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -46,6 +46,8 @@ enum law_size { LAW_SIZE_32G, }; +#define law_size_bits(sz) (__ilog2_u64(sz) - 1) + #ifdef CONFIG_FSL_CORENET enum law_trgt_if { LAW_TRGT_IF_PCIE_1 = 0x00, @@ -78,6 +80,7 @@ enum law_trgt_if { LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, + LAW_TRGT_IF_RIO_2 = 0x0d, LAW_TRGT_IF_DDR = 0x0f, LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */ }; diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index a5f72f5cd..db61e7e9c 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -1,4 +1,5 @@ -/* (C) Copyright 2007 Freescale Semiconductor, Inc. +/* + * Copyright 2007,2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -22,9 +23,9 @@ #include <asm/fsl_law.h> -int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); +int fsl_setup_hose(struct pci_controller *hose, unsigned long addr); int fsl_is_pci_agent(struct pci_controller *hose); void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index 55e7e2066..3f1191874 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -107,6 +107,9 @@ typedef struct global_data { #if defined(CONFIG_FSL_LAW) u32 used_laws; #endif +#if defined(CONFIG_E500) + u32 used_tlb_cams[(CONFIG_SYS_NUM_TLBCAMS+31)/32]; +#endif #if defined(CONFIG_MPC5xxx) unsigned long ipb_clk; unsigned long pci_clk; diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index c60a7d21c..6b42a73f3 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2009 Freescale Semiconductor, Inc. + * Copyright 2004-2009 Freescale Semiconductor, Inc. * * MPC83xx Internal Memory Map * @@ -868,4 +868,10 @@ typedef struct immap { #endif #define CONFIG_SYS_MPC83xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET) + +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 41942954b..957ad76a7 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -6,6 +6,23 @@ * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao@motorola.com) * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA */ #ifndef __IMMAP_85xx__ @@ -1545,6 +1562,78 @@ typedef struct par_io { u8 res[8]; } par_io_t; +#ifdef CONFIG_SYS_FSL_CPC +/* + * Define a single offset that is the start of all the CPC register + * blocks - if there is more than one CPC, we expect these to be + * contiguous 4k regions + */ + +typedef struct cpc_corenet { + u32 cpccsr0; /* Config/status reg */ + u32 res1; + u32 cpccfg0; /* Configuration register */ + u32 res2; + u32 cpcewcr0; /* External Write reg 0 */ + u32 cpcewabr0; /* External write base reg 0 */ + u32 res3[2]; + u32 cpcewcr1; /* External Write reg 1 */ + u32 cpcewabr1; /* External write base reg 1 */ + u32 res4[54]; + u32 cpcsrcr1; /* SRAM control reg 1 */ + u32 cpcsrcr0; /* SRAM control reg 0 */ + u32 res5[62]; + struct { + u32 id; /* partition ID */ + u32 res; + u32 alloc; /* partition allocation */ + u32 way; /* partition way */ + } partition_regs[16]; + u32 res6[704]; + u32 cpcerrinjhi; /* Error injection high */ + u32 cpcerrinjlo; /* Error injection lo */ + u32 cpcerrinjctl; /* Error injection control */ + u32 res7[5]; + u32 cpccaptdatahi; /* capture data high */ + u32 cpccaptdatalo; /* capture data low */ + u32 cpcaptecc; /* capture ECC */ + u32 res8[5]; + u32 cpcerrdet; /* error detect */ + u32 cpcerrdis; /* error disable */ + u32 cpcerrinten; /* errir interrupt enable */ + u32 cpcerrattr; /* error attribute */ + u32 cpcerreaddr; /* error extended address */ + u32 cpcerraddr; /* error address */ + u32 cpcerrctl; /* error control */ + u32 res9[105]; /* pad out to 4k */ +} cpc_corenet_t; + +#define CPC_CSR0_CE 0x80000000 /* Cache Enable */ +#define CPC_CSR0_PE 0x40000000 /* Enable ECC */ +#define CPC_CSR0_FI 0x00200000 /* Cache Flash Invalidate */ +#define CPC_CSR0_WT 0x00080000 /* Write-through mode */ +#define CPC_CSR0_FL 0x00000800 /* Hardware cache flush */ +#define CPC_CSR0_LFC 0x00000400 /* Cache Lock Flash Clear */ +#define CPC_CFG0_SZ_MASK 0x00003fff +#define CPC_CFG0_SZ_K(x) ((x & CPC_CFG0_SZ_MASK) << 6) +#define CPC_CFG0_NUM_WAYS(x) (((x >> 14) & 0x1f) + 1) +#define CPC_CFG0_LINE_SZ(x) ((((x >> 23) & 0x3) + 1) * 32) +#define CPC_SRCR1_SRBARU_MASK 0x0000ffff +#define CPC_SRCR1_SRBARU(x) (((unsigned long long)x >> 32) \ + & CPC_SRCR1_SRBARU_MASK) +#define CPC_SRCR0_SRBARL_MASK 0xffff8000 +#define CPC_SRCR0_SRBARL(x) (x & CPC_SRCR0_SRBARL_MASK) +#define CPC_SRCR0_INTLVEN 0x00000100 +#define CPC_SRCR0_SRAMSZ_1_WAY 0x00000000 +#define CPC_SRCR0_SRAMSZ_2_WAY 0x00000002 +#define CPC_SRCR0_SRAMSZ_4_WAY 0x00000004 +#define CPC_SRCR0_SRAMSZ_8_WAY 0x00000006 +#define CPC_SRCR0_SRAMSZ_16_WAY 0x00000008 +#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a +#define CPC_SRCR0_SRAMEN 0x00000001 +#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */ +#endif /* CONFIG_SYS_FSL_CPC */ + /* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { @@ -1847,17 +1936,86 @@ typedef struct ccsr_gur { } ccsr_gur_t; #endif +typedef struct serdes_corenet { + struct { + u32 rstctl; /* Reset Control Register */ +#define SRDS_RSTCTL_RST 0x80000000 +#define SRDS_RSTCTL_RSTDONE 0x40000000 +#define SRDS_RSTCTL_RSTERR 0x20000000 + u32 pllcr0; /* PLL Control Register 0 */ + u32 pllcr1; /* PLL Control Register 1 */ +#define SRDS_PLLCR1_PLL_BWSEL 0x08000000 + u32 res[5]; + } bank[3]; + u32 res1[12]; + u32 srdstcalcr; /* TX Calibration Control */ + u32 res2[3]; + u32 srdsrcalcr; /* RX Calibration Control */ + u32 res3[3]; + u32 srdsgr0; /* General Register 0 */ + u32 res4[11]; + u32 srdspccr0; /* Protocol Converter Config 0 */ + u32 srdspccr1; /* Protocol Converter Config 1 */ + u32 srdspccr2; /* Protocol Converter Config 2 */ +#define SRDS_PCCR2_RST_XGMII1 0x00800000 +#define SRDS_PCCR2_RST_XGMII2 0x00400000 + u32 res5[197]; + struct { + u32 gcr0; /* General Control Register 0 */ +#define SRDS_GCR0_RRST 0x00400000 +#define SRDS_GCR0_1STLANE 0x00010000 + u32 gcr1; /* General Control Register 1 */ +#define SRDS_GCR1_REIDL_CTL_MASK 0x001f0000 +#define SRDS_GCR1_REIDL_CTL_PCIE 0x00100000 +#define SRDS_GCR1_REIDL_CTL_SRIO 0x00000000 +#define SRDS_GCR1_REIDL_CTL_SGMII 0x00040000 +#define SRDS_GCR1_OPAD_CTL 0x04000000 + u32 res1[4]; + u32 tecr0; /* TX Equalization Control Reg 0 */ +#define SRDS_TECR0_TEQ_TYPE_MASK 0x30000000 +#define SRDS_TECR0_TEQ_TYPE_2LVL 0x10000000 + u32 res3; + u32 ttlcr0; /* Transition Tracking Loop Ctrl 0 */ + u32 res4[7]; + } lane[24]; + u32 res6[384]; +} serdes_corenet_t; + +enum { + FSL_SRDS_B1_LANE_A = 0, + FSL_SRDS_B1_LANE_B = 1, + FSL_SRDS_B1_LANE_C = 2, + FSL_SRDS_B1_LANE_D = 3, + FSL_SRDS_B1_LANE_E = 4, + FSL_SRDS_B1_LANE_F = 5, + FSL_SRDS_B1_LANE_G = 6, + FSL_SRDS_B1_LANE_H = 7, + FSL_SRDS_B1_LANE_I = 8, + FSL_SRDS_B1_LANE_J = 9, + FSL_SRDS_B2_LANE_A = 16, + FSL_SRDS_B2_LANE_B = 17, + FSL_SRDS_B2_LANE_C = 18, + FSL_SRDS_B2_LANE_D = 19, + FSL_SRDS_B3_LANE_A = 20, + FSL_SRDS_B3_LANE_B = 21, + FSL_SRDS_B3_LANE_C = 22, + FSL_SRDS_B3_LANE_D = 23, +}; + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 #define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000 #define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 #define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #else @@ -1874,6 +2032,12 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#ifdef CONFIG_TSECV2 +#define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#else +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#endif +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 @@ -1883,6 +2047,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CONFIG_SYS_FSL_CPC_ADDR \ + (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) #define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ @@ -1929,7 +2095,12 @@ typedef struct ccsr_gur { (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_85xx__*/ diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index fdfc654f2..098f25384 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1,7 +1,7 @@ /* * MPC86xx Internal Memory Map * - * Copyright(c) 2004 Freescale Semiconductor + * Copyright 2004 Freescale Semiconductor * Jeff Brown (Jeffrey@freescale.com) * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -1298,4 +1298,10 @@ extern immap_t *immr; #define CONFIG_SYS_MPC86xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_MDIO1_OFFSET 0x24000 + +#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) +#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) + #endif /*__IMMAP_86xx__*/ diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index ec22a5058..fd1024947 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -479,6 +479,8 @@ extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); extern int find_tlb_idx(void *addr, u8 tlbsel); +extern void init_used_tlb_cams(void); +extern int find_free_tlbcam(void); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f61778f86..c6da41163 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -992,6 +992,9 @@ #endif #endif +#define IS_SVR_REV(svr, maj, min) \ + ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min)) + /* * SVR_SOC_VER() Version Values */ diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index 91369a71e..49a86fd4c 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -243,27 +243,27 @@ */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 79376b3c5..cfed4ca9f 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -25,6 +25,11 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000 +#endif + /* * High Level Configuration Options */ @@ -51,20 +56,29 @@ HRCWL_SVCOD_DIV_2 |\ HRCWL_CSB_TO_CLKIN_2X1 |\ HRCWL_CORE_TO_CSB_3X1) -#define CONFIG_SYS_HRCW_HIGH (\ +#define CONFIG_SYS_HRCW_HIGH_BASE (\ HRCWH_PCI_HOST |\ HRCWH_PCI1_ARBITER_ENABLE |\ HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ HRCWH_BOOTSEQ_DISABLE |\ HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ HRCWH_TSEC1M_IN_RGMII |\ HRCWH_TSEC2M_IN_RGMII |\ HRCWH_BIG_ENDIAN |\ HRCWH_LALE_NORMAL) +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0XFFF00100 |\ + HRCWH_ROM_LOC_NAND_SP_8BIT |\ + HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY) +#endif + /* * System IO Config */ @@ -79,6 +93,10 @@ */ #define CONFIG_SYS_IMMR 0xE0000000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + /* * Arbiter Setup */ @@ -161,12 +179,6 @@ */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -200,10 +212,10 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ -#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ +#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ @@ -223,18 +235,31 @@ /* * NAND Flash on the Local Bus */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ + +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE0600000 +#endif + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -243,9 +268,31 @@ | OR_FCM_EHTR ) /* 0xFFFF8396 */ +#ifdef CONFIG_NAND_U_BOOT +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM +#endif + #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM + +#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ + !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + /* * Serial Port */ @@ -254,7 +301,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -408,7 +455,16 @@ /* * Environment */ -#ifndef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (512 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ @@ -442,7 +498,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_PCI -#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -504,7 +560,8 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ + BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 1e659e27a..e16f0e147 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -277,6 +277,10 @@ extern unsigned long get_clock_freq(void); #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F #define PLPDIR1_ESDHC_VAL 0x00000006 +#define PLPPAR1_UART0_BIT_MASK 0x00000fc0 +#define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 +#define PLPDIR1_UART0_BIT_MASK 0x00000fc0 +#define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 /* * General PCI diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 41e4a6e8a..78b73695b 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -98,7 +98,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index ddfe7aabd..15bfeefa4 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -149,8 +149,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00FF0000 -#define CONFIG_SYS_DDR_TLB_START 9 - /* * Memory map * diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index df9ab34e8..f4509bd09 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -101,7 +101,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ -#define CONFIG_SYS_DDR_TLB_START 9 #define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR3 1 #undef CONFIG_FSL_DDR_INTERACTIVE diff --git a/include/configs/apollon.h b/include/configs/apollon.h index ed14f7aa6..c1295de36 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -185,10 +185,8 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "Apollon # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "Apollon # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 38e2ce1f1..432cd57a7 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -149,6 +149,11 @@ #define CONFIG_SYS_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #endif +/* + * USB configuration + */ +#define CONFIG_USB_DA8XX /* Platform hookup to MUSB controller */ +#define CONFIG_MUSB_HCD /* * U-Boot general configuration @@ -234,10 +239,33 @@ #endif #ifdef CONFIG_USB_DA8XX -#define CONFIG_CMD_USB /* include support for usb */ -#define CONFIG_CMD_STORAGE /* include support for usb */ -#define CONFIG_CMD_FAT /* include support for FAT/storage*/ -#define CONFIG_DOS_PARTITION /* include support for FAT/storage*/ -#endif +#ifdef CONFIG_MUSB_HCD /* include support for usb host */ +#define CONFIG_CMD_USB /* include support for usb cmd */ + +#define CONFIG_USB_STORAGE /* MSC class support */ +#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */ +#define CONFIG_CMD_FAT /* inclue support for FAT/storage */ +#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */ + +#ifdef CONFIG_USB_KEYBOARD /* HID class support */ +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif /* CONFIG_USB_KEYBOARD */ + +#endif /* CONFIG_MUSB_HCD */ + +#ifdef CONFIG_MUSB_UDC +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "DA830EVM" +#endif /* CONFIG_MUSB_UDC */ + +#endif /* CONFIG_USB_DA8XX */ #endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index d092fb832..37011c093 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -66,6 +66,7 @@ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index ca3dea48f..e09fb7518 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -65,6 +65,7 @@ /* NAND */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_HW_ECC diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 491607766..c6e1d107f 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -74,6 +74,7 @@ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index ce2d7c4dd..ddc5990ce 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -75,6 +75,7 @@ #define CONFIG_SYS_NO_FLASH #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index f7d23990c..5774df5cf 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -114,6 +114,7 @@ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 47db2aa9c..3972ebce6 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -83,6 +83,7 @@ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index f24eb7a8b..94be9dcf4 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -78,6 +78,7 @@ #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ #define CONFIG_ENV_SECT_SIZE 2048 /* Env sector Size */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 5a55c569d..490821a0e 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -114,6 +114,7 @@ /*=====================*/ #ifdef CONFIG_SYS_USE_NAND #define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 #undef CONFIG_ENV_IS_IN_FLASH #define CONFIG_SYS_NO_FLASH #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index bec08dab1..b02332650 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -72,6 +72,14 @@ #define CONFIG_SYS_IMMR 0xE0000000 /* + * Bus Arbitration Configuration Register (ACR) + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* pipeline depth 4 transactions */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* 4 consecutive transactions */ +#define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */ +#define CONFIG_SYS_ACR_PARKM 3 /* parking master = QuiccEngine */ + +/* * DDR Setup */ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 6ab44387a..47437b09c 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -164,14 +164,12 @@ /* * Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ #ifdef CONFIG_APTIX -#define V_PROMPT "OMAP2420 Aptix # " +# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " #else -#define V_PROMPT "OMAP242x H4 # " +# define CONFIG_SYS_PROMPT "OMAP242x H4 # " #endif - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT V_PROMPT #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 4fe3bd8be..a8abb0e14 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -230,12 +230,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP3 beagleboard.org # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 630b00fae..a8d4105fb 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -234,12 +234,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP3_EVM # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "OMAP3_EVM # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 0c12b9fea..c72fb9d8e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -200,12 +200,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "Overo # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "Overo # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 154c0f4f3..f22fab579 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -191,12 +191,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "Pandora # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "Pandora # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index fa2ad5343..4d0193388 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -267,12 +267,11 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP34XX SDP # " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "OMAP34XX SDP # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index fa5828159..cdf95c044 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -215,12 +215,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "OMAP3 Zoom1# " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 5788d581a..568d9fc0c 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -282,8 +282,20 @@ /* USB */ #ifdef CONFIG_440EPX + +#undef CONFIG_USB_EHCI /* OHCI by default */ + +#ifdef CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_PPC4XX +#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#ifdef CONFIG_4xx_DCACHE +#define CONFIG_EHCI_DCACHE +#endif +#else /* CONFIG_USB_EHCI */ #define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE #define CONFIG_SYS_OHCI_BE_CONTROLLER #undef CONFIG_SYS_USB_OHCI_BOARD_INIT @@ -291,7 +303,9 @@ #define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 +#endif +#define CONFIG_USB_STORAGE /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f9db73b2d..dbc15b297 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -35,6 +35,13 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_caddy2 +#define VME_CADDY2 +#endif + +/* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ @@ -43,6 +50,8 @@ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_VME8349 1 /* ESD VME8349 board specific */ +#define CONFIG_MISC_INIT_R + #define CONFIG_PCI /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ @@ -75,7 +84,9 @@ */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#undef CONFIG_SPD_EEPROM /* dont use SPD EEPROM for DDR setup*/ +#define CONFIG_SPD_EEPROM +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_SYS_READ_SPD vme8349_read_spd #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ /* @@ -96,54 +107,40 @@ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ - -#if (CONFIG_SYS_DDR_SIZE == 512) -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_BANK_BIT_3) -#endif - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x39377322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9848ca /* P9-45, tuning? */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuf,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x07940242 -#define CONFIG_SYS_DDR_MODE2 0x00000000 -/* autocharge,no open page */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x63000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x04061000 +#define CONFIG_SYS_DDRCDR 0x80080001 /* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ -/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ +#ifdef VME_CADDY2 +#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 32bit */ \ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ +#else +#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ +#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ (2 << BR_PS_SHIFT) | /* 32bit */ \ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xF8006FF7 /* 128 MB flash size */ +#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001A /* 128 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ +#endif +/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ #define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) -#define CONFIG_SYS_OR1_PRELIM (0xffff8000 | 0x00000200) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) #define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x0000000e) +#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ @@ -157,7 +154,7 @@ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT #else -#undef CONFIG_SYS_RAMBOOT +#undef CONFIG_SYS_RAMBOOT #endif #define CONFIG_SYS_INIT_RAM_LOCK 1 @@ -174,11 +171,10 @@ /* * Local Bus LCRR and LBCR regs - * LCRR: DLL bypass, Clock divider is 4 + * LCRR: no DLL bypass, Clock divider is 4 * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 @@ -268,10 +264,10 @@ #undef PCI_ONE_PCI1 #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - +#ifndef VME_CADDY2 #define CONFIG_NET_MULTI +#endif +#define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -282,19 +278,26 @@ #define PCI_IDSEL_NUMBER 0xFIXME #endif +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ + #endif /* CONFIG_PCI */ /* * TSEC configuration */ +#ifdef VME_CADDY2 +#define CONFIG_E1000 +#else #define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#endif #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI #endif -#define CONFIG_GMII /* MII PHY management */ +#define CONFIG_GMII /* MII PHY management */ #define CONFIG_TSEC1 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 @@ -312,6 +315,12 @@ #endif /* CONFIG_TSEC_ENET */ +#if defined(CONFIG_E1000) +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif +#endif + /* * Environment */ @@ -560,7 +569,7 @@ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 9600 #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ @@ -605,4 +614,9 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +#ifndef __ASSEMBLY__ +int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, + unsigned char *buffer, int len); +#endif + #endif /* __CONFIG_H */ diff --git a/include/tsec.h b/include/tsec.h index 0ac303406..f56723a15 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -7,7 +7,7 @@ * terms of the GNU Public License, Version 2, incorporated * herein by reference. * - * Copyright 2004, 2007 Freescale Semiconductor, Inc. + * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. * (C) Copyright 2003, Motorola, Inc. * maintained by Xianghua Xiao (x.xiao@motorola.com) * author Andy Fleming @@ -20,22 +20,15 @@ #include <net.h> #include <config.h> -#ifndef CONFIG_SYS_TSEC1_OFFSET - #define CONFIG_SYS_TSEC1_OFFSET (0x24000) -#endif - -#define TSEC_SIZE 0x01000 - -/* FIXME: Should these be pushed back to 83xx and 85xx config files? */ -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ - || defined(CONFIG_MPC83xx) - #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#endif +#define TSEC_SIZE 0x01000 +#define TSEC_MDIO_OFFSET 0x01000 #define STD_TSEC_INFO(num) \ { \ .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ - .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ + .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ + .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + + (num - 1) * TSEC_MDIO_OFFSET), \ .devname = CONFIG_TSEC##num##_NAME, \ .phyaddr = TSEC##num##_PHY_ADDR, \ .flags = TSEC##num##_FLAGS \ @@ -44,7 +37,9 @@ #define SET_STD_TSEC_INFO(x, num) \ { \ x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ - x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ + x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ + x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ + + (num - 1) * TSEC_MDIO_OFFSET); \ x.devname = CONFIG_TSEC##num##_NAME; \ x.phyaddr = TSEC##num##_PHY_ADDR; \ x.flags = TSEC##num##_FLAGS;\ @@ -461,6 +456,22 @@ typedef struct tsec_hash_regs uint res2[24]; } tsec_hash_t; +typedef struct tsec_mdio { + uint res1[4]; + uint ieventm; + uint imaskm; + uint res2; + uint emapm; + uint res3[320]; + uint miimcfg; /* MII Management: Configuration */ + uint miimcom; /* MII Management: Command */ + uint miimadd; /* MII Management: Address */ + uint miimcon; /* MII Management: Control */ + uint miimstat; /* MII Management: Status */ + uint miimind; /* MII Management: Indicators */ + uint res4[690]; +} tsec_mdio_t; + typedef struct tsec { /* General Control and Status Registers (0x2_n000) */ @@ -526,12 +537,7 @@ typedef struct tsec uint res51c; - uint miimcfg; /* MII Management: Configuration */ - uint miimcom; /* MII Management: Command */ - uint miimadd; /* MII Management: Address */ - uint miimcon; /* MII Management: Control */ - uint miimstat; /* MII Management: Status */ - uint miimind; /* MII Management: Indicators */ + uint resmdio[6]; uint res538; @@ -571,7 +577,8 @@ typedef struct tsec struct tsec_private { volatile tsec_t *regs; - volatile tsec_t *phyregs; + volatile tsec_mdio_t *phyregs; + volatile tsec_mdio_t *phyregs_sgmii; struct phy_info *phyinfo; uint phyaddr; u32 flags; @@ -630,7 +637,8 @@ struct phy_info { struct tsec_info_struct { tsec_t *regs; - tsec_t *miiregs; + tsec_mdio_t *miiregs; + tsec_mdio_t *miiregs_sgmii; char *devname; unsigned int phyaddr; u32 flags; diff --git a/include/twl4030.h b/include/twl4030.h index feaec47b3..2b2f5ae6c 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -306,6 +306,10 @@ /* LED */ #define TWL4030_LED_LEDEN 0xEE +#define TWL4030_LED_LEDEN_LEDAON (1 << 0) +#define TWL4030_LED_LEDEN_LEDBON (1 << 1) +#define TWL4030_LED_LEDEN_LEDAPWM (1 << 4) +#define TWL4030_LED_LEDEN_LEDBPWM (1 << 5) /* Keypad */ #define TWL4030_KEYPAD_KEYP_CTRL_REG 0xD2 @@ -504,7 +508,7 @@ void twl4030_power_mmc_init(void); /* * LED */ -void twl4030_led_init(void); +void twl4030_led_init(unsigned char ledon_mask); /* * USB diff --git a/include/usb.h b/include/usb.h index 1cc3e4229..a1f09d4d7 100644 --- a/include/usb.h +++ b/include/usb.h @@ -132,7 +132,8 @@ struct usb_device { defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \ - defined(CONFIG_USB_OMAP3) + defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \ + defined(CONFIG_USB_BLACKFIN) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); |