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-rw-r--r--include/asm-m68k/fsl_i2c.h9
-rw-r--r--include/asm-sh/cpu_sh2.h40
-rw-r--r--include/asm-sh/cpu_sh4.h4
-rw-r--r--include/asm-sh/cpu_sh7203.h41
-rw-r--r--include/asm-sh/cpu_sh7723.h209
-rw-r--r--include/asm-sh/cpu_sh7785.h156
-rw-r--r--include/asm-sh/processor.h5
-rw-r--r--include/configs/M5235EVB.h7
-rw-r--r--include/configs/M5249EVB.h4
-rw-r--r--include/configs/M5253DEMO.h11
-rw-r--r--include/configs/M5271EVB.h2
-rw-r--r--include/configs/M5272C3.h5
-rw-r--r--include/configs/M5275EVB.h5
-rw-r--r--include/configs/M5282EVB.h4
-rw-r--r--include/configs/M54451EVB.h5
-rw-r--r--include/configs/M54455EVB.h5
-rw-r--r--include/configs/M5475EVB.h2
-rw-r--r--include/configs/M5485EVB.h2
-rw-r--r--include/configs/ads5121.h1
-rw-r--r--include/configs/ap325rxa.h177
-rw-r--r--include/configs/rsk7203.h107
-rw-r--r--include/configs/sequoia.h2
-rw-r--r--include/configs/sh7785lcr.h167
-rw-r--r--include/mpc512x.h1
-rw-r--r--include/mpc5xxx_sdma.h93
25 files changed, 1034 insertions, 30 deletions
diff --git a/include/asm-m68k/fsl_i2c.h b/include/asm-m68k/fsl_i2c.h
index 4f7134132..2bc9bf434 100644
--- a/include/asm-m68k/fsl_i2c.h
+++ b/include/asm-m68k/fsl_i2c.h
@@ -72,15 +72,6 @@ typedef struct fsl_i2c {
#define I2C_DR 0xFF
#define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR)
-
- u8 dfsrr; /* I2C digital filter sampling rate register */
- u8 res5[3];
-#define I2C_DFSRR 0x3F
-#define I2C_DFSRR_SHIFT 0
-#define I2C_DFSRR_RES ~(I2C_DR)
-
- /* Fill out the reserved block */
- u8 res6[0xE8];
} fsl_i2c_t;
#endif /* _ASM_I2C_H_ */
diff --git a/include/asm-sh/cpu_sh2.h b/include/asm-sh/cpu_sh2.h
new file mode 100644
index 000000000..8bc9bc64c
--- /dev/null
+++ b/include/asm-sh/cpu_sh2.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH2_H_
+#define _ASM_CPU_SH2_H_
+
+/* cache control */
+#define CCR_CACHE_STOP 0x00000008
+#define CCR_CACHE_ENABLE 0x00000005
+#define CCR_CACHE_ICI 0x00000008
+
+#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
+#define CACHE_OC_WAY_SHIFT 13
+#define CACHE_OC_NUM_ENTRIES 256
+#define CACHE_OC_ENTRY_SHIFT 4
+
+#if defined(CONFIG_CPU_SH7203)
+# include <asm/cpu_sh7203.h>
+#else
+# error "Unknown SH2 variant"
+#endif
+
+#endif /* _ASM_CPU_SH2_H_ */
diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h
index 5a8a5a149..b6cc6cfbd 100644
--- a/include/asm-sh/cpu_sh4.h
+++ b/include/asm-sh/cpu_sh4.h
@@ -35,10 +35,14 @@
# include <asm/cpu_sh7750.h>
#elif defined (CONFIG_CPU_SH7722)
# include <asm/cpu_sh7722.h>
+#elif defined (CONFIG_CPU_SH7723)
+# include <asm/cpu_sh7723.h>
#elif defined (CONFIG_CPU_SH7763)
# include <asm/cpu_sh7763.h>
#elif defined (CONFIG_CPU_SH7780)
# include <asm/cpu_sh7780.h>
+#elif defined (CONFIG_CPU_SH7785)
+# include <asm/cpu_sh7785.h>
#else
# error "Unknown SH4 variant"
#endif
diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h
new file mode 100644
index 000000000..77dcac43d
--- /dev/null
+++ b/include/asm-sh/cpu_sh7203.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_CPU_SH7203_H_
+#define _ASM_CPU_SH7203_H_
+
+/* Cache */
+#define CCR1 0xFFFC1000
+#define CCR CCR1
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PETCR 0xA4050106
+
+/* Port Data Registers */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+
+/* BSC */
+
+/* SDRAM controller */
+
+/* SCIF */
+#define SCSMR_0 0xFFFE8000
+#define SCIF0_BASE SCSMR_0
+
+/* Timer(CMT) */
+#define CMSTR 0xFFFEC000
+#define CMCSR_0 0xFFFEC002
+#define CMCNT_0 0xFFFEC004
+#define CMCOR_0 0xFFFEC006
+#define CMCSR_1 0xFFFEC008
+#define CMCNT_1 0xFFFEC00A
+#define CMCOR_1 0xFFFEC00C
+
+/* On chip oscillator circuits */
+#define FRQCR 0xA415FF80
+#define WTCNT 0xA415FF84
+#define WTCSR 0xA415FF86
+
+#endif /* _ASM_CPU_SH7203_H_ */
diff --git a/include/asm-sh/cpu_sh7723.h b/include/asm-sh/cpu_sh7723.h
new file mode 100644
index 000000000..6dac6e9a0
--- /dev/null
+++ b/include/asm-sh/cpu_sh7723.h
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2008 Renesas Solutions Corp.
+ *
+ * SH7723 Internal I/O register
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_CPU_SH7723_H_
+#define _ASM_CPU_SH7723_H_
+
+#define CACHE_OC_NUM_WAYS 4
+#define CCR_CACHE_INIT 0x0000090d
+
+/* EXP */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* MMU */
+#define PTEH 0xFF000000
+#define PTEL 0xFF000004
+#define TTB 0xFF000008
+#define TEA 0xFF00000C
+#define MMUCR 0xFF000010
+#define PASCR 0xFF000070
+#define IRMCR 0xFF000078
+
+/* CACHE */
+#define CCR 0xFF00001C
+#define RAMCR 0xFF000074
+
+/* INTC */
+
+/* BSC */
+#define CMNCR 0xFEC10000
+#define CS0BCR 0xFEC10004
+#define CS2BCR 0xFEC10008
+#define CS4BCR 0xFEC10010
+#define CS5ABCR 0xFEC10014
+#define CS5BBCR 0xFEC10018
+#define CS6ABCR 0xFEC1001C
+#define CS6BBCR 0xFEC10020
+#define CS0WCR 0xFEC10024
+#define CS2WCR 0xFEC10028
+#define CS4WCR 0xFEC10030
+#define CS5AWCR 0xFEC10034
+#define CS5BWCR 0xFEC10038
+#define CS6AWCR 0xFEC1003C
+#define CS6BWCR 0xFEC10040
+#define RBWTCNT 0xFEC10054
+
+/* SBSC */
+#define SBSC_SDCR 0xFE400008
+#define SBSC_SDWCR 0xFE40000C
+#define SBSC_SDPCR 0xFE400010
+#define SBSC_RTCSR 0xFE400014
+#define SBSC_RTCNT 0xFE400018
+#define SBSC_RTCOR 0xFE40001C
+#define SBSC_RFCR 0xFE400020
+
+/* DMAC */
+
+/* CPG */
+#define FRQCR 0xA4150000
+#define VCLKCR 0xA4150004
+#define SCLKACR 0xA4150008
+#define SCLKBCR 0xA415000C
+#define IRDACLKCR 0xA4150018
+#define PLLCR 0xA4150024
+#define DLLFRQ 0xA4150050
+
+/* LOW POWER MODE */
+#define STBCR 0xA4150020
+#define MSTPCR0 0xA4150030
+#define MSTPCR1 0xA4150034
+#define MSTPCR2 0xA4150038
+
+/* RWDT */
+#define RWTCNT 0xA4520000
+#define RWTCSR 0xA4520004
+#define WTCNT RWTCNT
+
+/* TMU */
+#define TSTR 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+
+/* TPU */
+
+/* CMT */
+#define CMSTR 0xA44A0000
+#define CMCSR 0xA44A0060
+#define CMCNT 0xA44A0064
+#define CMCOR 0xA44A0068
+
+/* MSIOF */
+
+/* SCIF */
+#define SCIF0_BASE 0xFFE00000
+#define SCIF1_BASE 0xFFE10000
+#define SCIF2_BASE 0xFFE20000
+#define SCIF3_BASE 0xa4e30000
+#define SCIF4_BASE 0xa4e40000
+#define SCIF5_BASE 0xa4e50000
+
+/* RTC */
+/* IrDA */
+/* KEYSC */
+/* USB */
+/* IIC */
+/* FLCTL */
+/* VPU */
+/* VIO(CEU) */
+/* VIO(VEU) */
+/* VIO(BEU) */
+/* 2DG */
+/* LCDC */
+/* VOU */
+/* TSIF */
+/* SIU */
+/* ATAPI */
+
+/* PFC */
+#define PACR 0xA4050100
+#define PBCR 0xA4050102
+#define PCCR 0xA4050104
+#define PDCR 0xA4050106
+#define PECR 0xA4050108
+#define PFCR 0xA405010A
+#define PGCR 0xA405010C
+#define PHCR 0xA405010E
+#define PJCR 0xA4050110
+#define PKCR 0xA4050112
+#define PLCR 0xA4050114
+#define PMCR 0xA4050116
+#define PNCR 0xA4050118
+#define PQCR 0xA405011A
+#define PRCR 0xA405011C
+#define PSCR 0xA405011E
+#define PTCR 0xA4050140
+#define PUCR 0xA4050142
+#define PVCR 0xA4050144
+#define PWCR 0xA4050146
+#define PXCR 0xA4050148
+#define PYCR 0xA405014A
+#define PZCR 0xA405014C
+#define PSELA 0xA405014E
+#define PSELB 0xA4050150
+#define PSELC 0xA4050152
+#define PSELD 0xA4050154
+#define HIZCRA 0xA4050158
+#define HIZCRB 0xA405015A
+#define HIZCRC 0xA405015C
+#define HIZCRD 0xA405015E
+#define MSELCRA 0xA4050180
+#define MSELCRB 0xA4050182
+#define PULCR 0xA4050184
+#define DRVCRA 0xA405018A
+#define DRVCRB 0xA405018C
+
+/* I/O Port */
+#define PADR 0xA4050120
+#define PBDR 0xA4050122
+#define PCDR 0xA4050124
+#define PDDR 0xA4050126
+#define PEDR 0xA4050128
+#define PFDR 0xA405012A
+#define PGDR 0xA405012C
+#define PHDR 0xA405012E
+#define PJDR 0xA4050130
+#define PKDR 0xA4050132
+#define PLDR 0xA4050134
+#define PMDR 0xA4050136
+#define PNDR 0xA4050138
+#define PQDR 0xA405013A
+#define PRDR 0xA405013C
+#define PSDR 0xA405013E
+#define PTDR 0xA4050160
+#define PUDR 0xA4050162
+#define PVDR 0xA4050164
+#define PWDR 0xA4050166
+#define PYDR 0xA4050168
+#define PZDR 0xA405016A
+
+/* UBC */
+/* H-UDI */
+
+#endif /* _ASM_CPU_SH7723_H_ */
diff --git a/include/asm-sh/cpu_sh7785.h b/include/asm-sh/cpu_sh7785.h
new file mode 100644
index 000000000..4a4dfc904
--- /dev/null
+++ b/include/asm-sh/cpu_sh7785.h
@@ -0,0 +1,156 @@
+#ifndef _ASM_CPU_SH7785_H_
+#define _ASM_CPU_SH7785_H_
+
+/*
+ * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+ * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
+ * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#define CACHE_OC_NUM_WAYS 1
+#define CCR_CACHE_INIT 0x0000090b
+
+/* Exceptions */
+#define TRA 0xFF000020
+#define EXPEVT 0xFF000024
+#define INTEVT 0xFF000028
+
+/* Cache Controller */
+#define CCR 0xFF00001C
+#define QACR0 0xFF000038
+#define QACR1 0xFF00003C
+#define RAMCR 0xFF000074
+
+/* Watchdog Timer and Reset */
+#define WTCNT WDTCNT
+#define WDTST 0xFFCC0000
+#define WDTCSR 0xFFCC0004
+#define WDTBST 0xFFCC0008
+#define WDTCNT 0xFFCC0010
+#define WDTBCNT 0xFFCC0018
+
+/* Timer Unit */
+#define TSTR TSTR0
+#define TOCR 0xFFD80000
+#define TSTR0 0xFFD80004
+#define TCOR0 0xFFD80008
+#define TCNT0 0xFFD8000C
+#define TCR0 0xFFD80010
+#define TCOR1 0xFFD80014
+#define TCNT1 0xFFD80018
+#define TCR1 0xFFD8001C
+#define TCOR2 0xFFD80020
+#define TCNT2 0xFFD80024
+#define TCR2 0xFFD80028
+#define TCPR2 0xFFD8002C
+#define TSTR1 0xFFDC0004
+#define TCOR3 0xFFDC0008
+#define TCNT3 0xFFDC000C
+#define TCR3 0xFFDC0010
+#define TCOR4 0xFFDC0014
+#define TCNT4 0xFFDC0018
+#define TCR4 0xFFDC001C
+#define TCOR5 0xFFDC0020
+#define TCNT5 0xFFDC0024
+#define TCR5 0xFFDC0028
+
+/* Serial Communication Interface with FIFO */
+#define SCIF1_BASE 0xffeb0000
+
+/* LBSC */
+#define MMSELR 0xfc400020
+#define LBSC_BASE 0xff800000
+#define BCR (LBSC_BASE + 0x1000)
+#define CS0BCR (LBSC_BASE + 0x2000)
+#define CS1BCR (LBSC_BASE + 0x2010)
+#define CS2BCR (LBSC_BASE + 0x2020)
+#define CS3BCR (LBSC_BASE + 0x2030)
+#define CS4BCR (LBSC_BASE + 0x2040)
+#define CS5BCR (LBSC_BASE + 0x2050)
+#define CS6BCR (LBSC_BASE + 0x2060)
+#define CS0WCR (LBSC_BASE + 0x2008)
+#define CS1WCR (LBSC_BASE + 0x2018)
+#define CS2WCR (LBSC_BASE + 0x2028)
+#define CS3WCR (LBSC_BASE + 0x2038)
+#define CS4WCR (LBSC_BASE + 0x2048)
+#define CS5WCR (LBSC_BASE + 0x2058)
+#define CS6WCR (LBSC_BASE + 0x2068)
+#define CS5PCR (LBSC_BASE + 0x2070)
+#define CS6PCR (LBSC_BASE + 0x2080)
+
+/* PCI Controller */
+#define SH7780_PCIECR 0xFE000008
+#define SH7780_PCIVID 0xFE040000
+#define SH7780_PCIDID 0xFE040002
+#define SH7780_PCICMD 0xFE040004
+#define SH7780_PCISTATUS 0xFE040006
+#define SH7780_PCIRID 0xFE040008
+#define SH7780_PCIPIF 0xFE040009
+#define SH7780_PCISUB 0xFE04000A
+#define SH7780_PCIBCC 0xFE04000B
+#define SH7780_PCICLS 0xFE04000C
+#define SH7780_PCILTM 0xFE04000D
+#define SH7780_PCIHDR 0xFE04000E
+#define SH7780_PCIBIST 0xFE04000F
+#define SH7780_PCIIBAR 0xFE040010
+#define SH7780_PCIMBAR0 0xFE040014
+#define SH7780_PCIMBAR1 0xFE040018
+#define SH7780_PCISVID 0xFE04002C
+#define SH7780_PCISID 0xFE04002E
+#define SH7780_PCICP 0xFE040034
+#define SH7780_PCIINTLINE 0xFE04003C
+#define SH7780_PCIINTPIN 0xFE04003D
+#define SH7780_PCIMINGNT 0xFE04003E
+#define SH7780_PCIMAXLAT 0xFE04003F
+#define SH7780_PCICID 0xFE040040
+#define SH7780_PCINIP 0xFE040041
+#define SH7780_PCIPMC 0xFE040042
+#define SH7780_PCIPMCSR 0xFE040044
+#define SH7780_PCIPMCSRBSE 0xFE040046
+#define SH7780_PCI_CDD 0xFE040047
+#define SH7780_PCICR 0xFE040100
+#define SH7780_PCILSR0 0xFE040104
+#define SH7780_PCILSR1 0xFE040108
+#define SH7780_PCILAR0 0xFE04010C
+#define SH7780_PCILAR1 0xFE040110
+#define SH7780_PCIIR 0xFE040114
+#define SH7780_PCIIMR 0xFE040118
+#define SH7780_PCIAIR 0xFE04011C
+#define SH7780_PCICIR 0xFE040120
+#define SH7780_PCIAINT 0xFE040130
+#define SH7780_PCIAINTM 0xFE040134
+#define SH7780_PCIBMIR 0xFE040138
+#define SH7780_PCIPAR 0xFE0401C0
+#define SH7780_PCIPINT 0xFE0401CC
+#define SH7780_PCIPINTM 0xFE0401D0
+#define SH7780_PCIMBR0 0xFE0401E0
+#define SH7780_PCIMBMR0 0xFE0401E4
+#define SH7780_PCIMBR1 0xFE0401E8
+#define SH7780_PCIMBMR1 0xFE0401EC
+#define SH7780_PCIMBR2 0xFE0401F0
+#define SH7780_PCIMBMR2 0xFE0401F4
+#define SH7780_PCIIOBR 0xFE0401F8
+#define SH7780_PCIIOBMR 0xFE0401FC
+#define SH7780_PCICSCR0 0xFE040210
+#define SH7780_PCICSCR1 0xFE040214
+#define SH7780_PCICSAR0 0xFE040218
+#define SH7780_PCICSAR1 0xFE04021C
+#define SH7780_PCIPDR 0xFE040220
+
+#endif /* _ASM_CPU_SH7780_H_ */
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 388aa69c6..938a89cff 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -1,6 +1,9 @@
#ifndef _ASM_SH_PROCESSOR_H_
#define _ASM_SH_PROCESSOR_H_
-#if defined CONFIG_SH3
+#if defined(CONFIG_SH2) || \
+ defined (CONFIG_SH2A)
+# include <asm/cpu_sh2.h>
+#elif defined (CONFIG_SH3)
# include <asm/cpu_sh3.h>
#elif defined (CONFIG_SH4) || \
defined (CONFIG_SH4A)
diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h
index e8361321f..b32eabe9a 100644
--- a/include/configs/M5235EVB.h
+++ b/include/configs/M5235EVB.h
@@ -102,12 +102,15 @@
/* I2C */
#define CONFIG_FSL_I2C
-#define CONFIG_HARD_I2C /* I2C with hw support */
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 80000
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (gpio->par_qspi)
+#define CFG_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
+#define CFG_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index c2f5dd9fa..6bf2d99c9 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -41,8 +41,8 @@
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index f2c2317f5..9f78f6ebc 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -118,6 +118,17 @@
#define CONFIG_HOSTNAME M5253DEMO
+/* I2C */
+#define CONFIG_FSL_I2C
+#define CONFIG_HARD_I2C /* I2C with hw support */
+#define CFG_I2C_SPEED 80000
+#define CFG_I2C_SLAVE 0x7F
+#define CFG_I2C_OFFSET 0x00000280
+#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (*(u32 *) (CFG_MBAR+0x19C))
+#define CFG_I2C_PINMUX_CLR (0xFFFFE7FF)
+#define CFG_I2C_PINMUX_SET (0)
+
#define CFG_PROMPT "=> "
#define CFG_LONGHELP /* undef to save memory */
diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h
index 12f9783ab..78a1b93cf 100644
--- a/include/configs/M5271EVB.h
+++ b/include/configs/M5271EVB.h
@@ -42,7 +42,7 @@
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG /* disable watchdog */
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index 7edd322bd..fc457e3bc 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -40,8 +40,8 @@
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
@@ -91,6 +91,7 @@
#ifdef CONFIG_MCFFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 8
# define CFG_FAULT_ECHO_LINK_DOWN
diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h
index 30c70e579..430af6bfa 100644
--- a/include/configs/M5275EVB.h
+++ b/include/configs/M5275EVB.h
@@ -45,7 +45,7 @@
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
+#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
/* Configuration for environment
@@ -118,6 +118,9 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_OFFSET 0x00000300
#define CFG_IMMR CFG_MBAR
+#define CFG_I2C_PINMUX_REG (gpio_reg->par_feci2c)
+#define CFG_I2C_PINMUX_CLR (0xFFF0)
+#define CFG_I2C_PINMUX_SET (0x000F)
#ifdef CONFIG_MCFFEC
#define CONFIG_ETHADDR 00:06:3b:01:41:55
diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h
index 279a12be7..eb59c250d 100644
--- a/include/configs/M5282EVB.h
+++ b/include/configs/M5282EVB.h
@@ -40,8 +40,8 @@
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
-#define CONFIG_BAUDRATE 19200
-#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
+#define CONFIG_BAUDRATE 115200
+#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 588c00c62..cf58239df 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -140,9 +140,8 @@
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 " MK_STR(CFG_UBOOT_END)\
- "; era 0 " MK_STR(CFG_UBOOT_END) \
- "2ffff;" \
+ "prog=prot off 0 " MK_STR(CFG_UBOOT_END) \
+ "; era 0 " MK_STR(CFG_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 476aba347..ad9c15eb9 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -157,7 +157,7 @@
" " MK_STR(CFG_UBOOT_END) ";" \
"era " MK_STR(CFG_FLASH_BASE) " " \
MK_STR(CFG_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\
+ "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE) \
" ${filesize}; save\0" \
""
#endif
@@ -388,9 +388,6 @@
#endif
#endif
-#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-#define CFG_FLASH_CHECKSUM
-
/*
* This is setting for JFFS2 support in u-boot.
* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index 4037efb73..af6723c63 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -226,7 +226,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
-#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CFG2 0x46770000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index a14c55bc3..248db53d9 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -212,7 +212,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_SDRAM_CFG1 0x73711630
-#define CFG_SDRAM_CFG2 0x46370000
+#define CFG_SDRAM_CFG2 0x46770000
#define CFG_SDRAM_CTRL 0xE10B0000
#define CFG_SDRAM_EMOD 0x40010000
#define CFG_SDRAM_MODE 0x018D0000
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index 5f74afb0d..f516c4602 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -210,6 +210,7 @@
#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */
#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */
+#define CFG_CS_ALETIMING 0x00000005 /* Use alternative CS timing for CS0 and CS2 */
/* Use SRAM for initial stack */
#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */
diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h
new file mode 100644
index 000000000..81a118dc5
--- /dev/null
+++ b/include/configs/ap325rxa.h
@@ -0,0 +1,177 @@
+/*
+ * Configuation settings for the Renesas Solutions AP-325RXA board
+ *
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __AP325RXA_H
+#define __AP325RXA_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4 1
+#define CONFIG_CPU_SH7723 1
+#define CONFIG_AP325RXA 1
+
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_BAUDRATE 38400
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC2,38400"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* SMC9118 */
+#define CONFIG_DRIVER_SMC911X 1
+#define CONFIG_DRIVER_SMC911X_32_BIT 1
+#define CONFIG_DRIVER_SMC911X_BASE 0xB6080000
+
+/* MEMORY */
+#define AP325RXA_SDRAM_BASE (0x88000000)
+#define AP325RXA_FLASH_BASE_1 (0xA0000000)
+#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
+
+/* undef to save memory */
+#define CFG_LONGHELP
+/* Monitor Command Prompt */
+#define CFG_PROMPT "=> "
+/* Buffer size for input from the Console */
+#define CFG_CBSIZE 256
+/* Buffer size for Console output */
+#define CFG_PBSIZE 256
+/* max args accepted for monitor commands */
+#define CFG_MAXARGS 16
+/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 38400 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
+#define CONFIG_CONS_SCIF5 1
+
+/* Suppress display of console information at boot */
+#undef CFG_CONSOLE_INFO_QUIET
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+#define CFG_MEMTEST_START (AP325RXA_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024))
+
+/* Enable alternate, more extensive, memory test */
+#undef CFG_ALT_MEMTEST
+/* Scratch address used by the alternate memory test */
+#undef CFG_MEMTEST_SCRATCH
+
+/* Enable temporary baudrate change while serial download */
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (AP325RXA_SDRAM_BASE)
+/* maybe more, but if so u-boot doesn't know about it... */
+#define CFG_SDRAM_SIZE (128 * 1024 * 1024)
+/* default load address for scripts ?!? */
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
+#define CFG_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
+/* Monitor size */
+#define CFG_MONITOR_LEN (128 * 1024)
+/* Size of DRAM reserved for malloc() use */
+#define CFG_MALLOC_LEN (256 * 1024)
+/* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER 1
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#undef CFG_FLASH_QUIET_TEST
+/* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO
+/* Physical start address of Flash memory */
+#define CFG_FLASH_BASE (AP325RXA_FLASH_BASE_1)
+/* Max number of sectors on each Flash chip */
+#define CFG_MAX_FLASH_SECT 512
+
+/*
+ * IDE support
+ */
+#define CONFIG_IDE_RESET 1
+#define CFG_PIO_MODE 1
+#define CFG_IDE_MAXBUS 1 /* IDE bus */
+#define CFG_IDE_MAXDEVICE 1
+#define CFG_ATA_BASE_ADDR 0xB4180000
+#define CFG_ATA_STRIDE 2 /* 1bit shift */
+#define CFG_ATA_DATA_OFFSET 0x200 /* data reg offset */
+#define CFG_ATA_REG_OFFSET 0x200 /* reg offset */
+#define CFG_ATA_ALT_OFFSET 0x210 /* alternate register offset */
+
+/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
+
+/* Timeout for Flash erase operations (in ms) */
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+/* Timeout for Flash write operations (in ms) */
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+/* Timeout for Flash set sector lock bit operations (in ms) */
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+/* Timeout for Flash clear lock bit operations (in ms) */
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+/*
+ * Use hardware flash sectors protection instead
+ * of U-Boot software protection
+ */
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (128 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+/* Offset of env Flash sector relative to CFG_FLASH_BASE */
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __AP325RXA_H */
diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h
new file mode 100644
index 000000000..23598f33c
--- /dev/null
+++ b/include/configs/rsk7203.h
@@ -0,0 +1,107 @@
+/*
+ * Configuation settings for the Renesas Technology RSK 7203
+ *
+ * Copyright (C) 2008 Nobuhiro Iwamatsu
+ * Copyright (C) 2008 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __RSK7203_H
+#define __RSK7203_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH2 1
+#define CONFIG_SH2A 1
+#define CONFIG_CPU_SH7203 1
+#define CONFIG_RSK7203 1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_CACHE
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTARGS "console=ttySC0,115200"
+#define CONFIG_LOADADDR 0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define RSK7203_SDRAM_BASE 0x0C000000
+#define RSK7203_FLASH_BASE_1 0x20000000 /* Non cache */
+#define RSK7203_FLASH_BANK_SIZE (4 * 1024 * 1024)
+
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#define CFG_CBSIZE 256 /* Buffer size for input from the Console */
+#define CFG_PBSIZE 256 /* Buffer size for Console output */
+#define CFG_MAXARGS 16 /* max args accepted for monitor commands */
+/* Buffer size for Boot Arguments passed to kernel */
+#define CFG_BARGSIZE 512
+/* List of legal baudrate settings for this board */
+#define CFG_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF0 1
+
+#define CFG_MEMTEST_START RSK7203_SDRAM_BASE
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + (3 * 1024 * 1024))
+
+#define CFG_SDRAM_BASE RSK7203_SDRAM_BASE
+#define CFG_SDRAM_SIZE (32 * 1024 * 1024)
+
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 1024 * 1024)
+#define CFG_MONITOR_BASE RSK7203_FLASH_BASE_1
+#define CFG_MONITOR_LEN (128 * 1024)
+#define CFG_MALLOC_LEN (256 * 1024)
+#define CFG_GBL_DATA_SIZE 256
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+#undef CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_BASE RSK7203_FLASH_BASE_1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
+#define CFG_MAX_FLASH_SECT 64
+#define CFG_MAX_FLASH_BANKS 1
+
+#define CFG_ENV_IS_IN_FLASH
+#define CFG_ENV_SECT_SIZE (64 * 1024)
+#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
+#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CFG_FLASH_ERASE_TOUT 12000
+#define CFG_FLASH_WRITE_TOUT 500
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ 33333333
+#define CMT_CLK_DIVIDER 32 /* 8 (default), 32, 128 or 512 */
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
+
+#endif /* __RSK7203_H */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 18675c2d5..74f6e3a89 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -179,7 +179,7 @@
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
*/
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
-#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
+#define CFG_NAND_U_BOOT_SIZE (512 << 10) /* Size of RAM U-Boot image */
/*
* Now the NAND chip has to be defined (no autodetection used!)
diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h
new file mode 100644
index 000000000..efdb163dd
--- /dev/null
+++ b/include/configs/sh7785lcr.h
@@ -0,0 +1,167 @@
+/*
+ * Configuation settings for the Renesas Technology R0P7785LC0011RL board
+ *
+ * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH7785LCR_H
+#define __SH7785LCR_H
+
+#undef DEBUG
+#define CONFIG_SH 1
+#define CONFIG_SH4A 1
+#define CONFIG_CPU_SH7785 1
+#define CONFIG_SH7785LCR 1
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_ENV
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "bootdevice=0:1\0" \
+ "usbload=usb reset;usbboot;usb stop;bootm\0"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define SH7785LCR_SDRAM_BASE (0x08000000)
+#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
+#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
+#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
+#define SH7785LCR_USB_BASE (0xb4000000)
+
+#define CFG_LONGHELP
+#define CFG_PROMPT "=> "
+#define CFG_CBSIZE 256
+#define CFG_PBSIZE 256
+#define CFG_MAXARGS 16
+#define CFG_BARGSIZE 512
+#define CFG_BAUDRATE_TABLE { 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE 1
+#define CONFIG_CONS_SCIF1 1
+#define CONFIG_SCIF_EXT_CLOCK 1
+#undef CFG_CONSOLE_INFO_QUIET
+#undef CFG_CONSOLE_OVERWRITE_ROUTINE
+#undef CFG_CONSOLE_ENV_OVERWRITE
+
+
+#define CFG_MEMTEST_START (SH7785LCR_SDRAM_BASE)
+#define CFG_MEMTEST_END (CFG_MEMTEST_START + \
+ (SH7785LCR_SDRAM_SIZE) - \
+ 4 * 1024 * 1024)
+#undef CFG_ALT_MEMTEST
+#undef CFG_MEMTEST_SCRATCH
+#undef CFG_LOADS_BAUD_CHANGE
+
+#define CFG_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
+#define CFG_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
+#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 16 * 1024 * 1024)
+
+#define CFG_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
+#define CFG_MONITOR_LEN (512 * 1024)
+#define CFG_MALLOC_LEN (512 * 1024)
+#define CFG_GBL_DATA_SIZE (256)
+#define CFG_BOOTMAPSZ (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CFG_FLASH_CFI
+#undef CFG_FLASH_QUIET_TEST
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
+#define CFG_MAX_FLASH_SECT 512
+
+#define CFG_MAX_FLASH_BANKS 1
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE + \
+ (0 * SH7785LCR_FLASH_BANK_SIZE) }
+
+#define CFG_FLASH_ERASE_TOUT (3 * 1000)
+#define CFG_FLASH_WRITE_TOUT (3 * 1000)
+#define CFG_FLASH_LOCK_TOUT (3 * 1000)
+#define CFG_FLASH_UNLOCK_TOUT (3 * 1000)
+
+#undef CFG_FLASH_PROTECTION
+#undef CFG_DIRECT_FLASH_TFTP
+
+/* R8A66597 */
+#define LITTLEENDIAN /* for include/usb.h */
+#define CONFIG_USB_R8A66597_HCD
+#define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
+#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
+#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
+#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
+
+/* PCI Controller */
+#define CONFIG_PCI
+#define CONFIG_SH4_PCI
+#define CONFIG_SH7780_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW 1
+
+#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
+#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
+
+#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
+#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
+
+/* Network device (RTL8169) support */
+#define CONFIG_NET_MULTI
+#define CONFIG_RTL8169
+
+/* ENV setting */
+#define CFG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE 1
+#define CFG_ENV_SECT_SIZE (256 * 1024)
+#define CFG_ENV_SIZE (CFG_ENV_SECT_SIZE)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN)
+#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SECT_SIZE)
+
+/* Board Clock */
+/* The SCIF used external clock. system clock only used timer. */
+#define CONFIG_SYS_CLK_FREQ 50000000
+#define TMU_CLK_DIVIDER 4
+#define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER)
+
+#endif /* __SH7785LCR_H */
diff --git a/include/mpc512x.h b/include/mpc512x.h
index a76b1ca21..cb418d1e9 100644
--- a/include/mpc512x.h
+++ b/include/mpc512x.h
@@ -58,6 +58,7 @@
#define CS5_CONFIG 0x00014
#define CS6_CONFIG 0x00018
#define CS7_CONFIG 0x0001C
+#define CS_ALE_TIMING_CONFIG 0x00034
#define CS_CTRL 0x00020
#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */
diff --git a/include/mpc5xxx_sdma.h b/include/mpc5xxx_sdma.h
new file mode 100644
index 000000000..8b740e4e6
--- /dev/null
+++ b/include/mpc5xxx_sdma.h
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * This file is based on code
+ * (C) Copyright Motorola, Inc., 2000
+ *
+ * odin smartdma header file
+ */
+
+#ifndef __MPC5XXX_SDMA_H
+#define __MPC5XXX_SDMA_H
+
+#include <common.h>
+#include <mpc5xxx.h>
+
+/* Task number assignment */
+#define FEC_RECV_TASK_NO 0
+#define FEC_XMIT_TASK_NO 1
+
+/*---------------------------------------------------------------------*/
+
+/* Stuff for Ethernet Tx/Rx tasks */
+
+/*---------------------------------------------------------------------*/
+
+/* Layout of Ethernet controller Parameter SRAM area:
+----------------------------------------------------------------
+0x00: TBD_BASE, base address of TX BD ring
+0x04: TBD_NEXT, address of next TX BD to be processed
+0x08: RBD_BASE, base address of RX BD ring
+0x0C: RBD_NEXT, address of next RX BD to be processed
+---------------------------------------------------------------
+ALL PARAMETERS ARE ALL LONGWORDS (FOUR BYTES EACH).
+*/
+
+/* base address of SRAM area to store parameters used by Ethernet tasks */
+#define FEC_PARAM_BASE (MPC5XXX_SRAM + 0x0800)
+
+/* base address of SRAM area for buffer descriptors */
+#define FEC_BD_BASE (MPC5XXX_SRAM + 0x0820)
+
+/*---------------------------------------------------------------------*/
+
+/* common shortcuts used by driver C code */
+
+/*---------------------------------------------------------------------*/
+
+/* Disable SmartDMA task */
+#define SDMA_TASK_DISABLE(tasknum) \
+{ \
+ volatile ushort *tcr = (ushort *)(MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
+ *tcr = (*tcr) & (~0x8000); \
+}
+
+/* Enable SmartDMA task */
+#define SDMA_TASK_ENABLE(tasknum) \
+{ \
+ volatile ushort *tcr = (ushort *) (MPC5XXX_SDMA + 0x0000001c + 2 * tasknum); \
+ *tcr = (*tcr) | 0x8000; \
+}
+
+/* Enable interrupt */
+#define SDMA_INT_ENABLE(tasknum) \
+{ \
+ struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+ sdma->IntMask &= ~(1 << tasknum); \
+}
+
+/* Disable interrupt */
+#define SDMA_INT_DISABLE(tasknum) \
+{ \
+ struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+ sdma->IntMask |= (1 << tasknum); \
+}
+
+
+/* Clear interrupt pending bits */
+#define SDMA_CLEAR_IEVENT(tasknum) \
+{ \
+ struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA; \
+ sdma->IntPend = (1 << tasknum); \
+}
+
+/* get interupt pending bit of a task */
+#define SDMA_GET_PENDINGBIT(tasknum) \
+ ((*(vu_long *)(MPC5XXX_SDMA + 0x14)) & (1<<(tasknum)))
+
+/* get interupt mask bit of a task */
+#define SDMA_GET_MASKBIT(tasknum) \
+ ((*(vu_long *)(MPC5XXX_SDMA + 0x18)) & (1<<(tasknum)))
+
+#endif /* __MPC5XXX_SDMA_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-02 00:01:31 +0000