diff options
Diffstat (limited to 'include')
325 files changed, 12730 insertions, 1690 deletions
diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index 4a03cecb5..69a217487 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -66,43 +66,6 @@ #define L2CR_L2OH_INV 0x00020000 /* bits 14-15 - output hold time = long */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/*---------------------------------------------------------------- - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #ifndef __ASSEMBLY__ /* cpu ids we detect */ typedef enum __cpu_t { diff --git a/include/api_public.h b/include/api_public.h index d3164f69c..5940d81fd 100644 --- a/include/api_public.h +++ b/include/api_public.h @@ -57,6 +57,7 @@ #define API_ENOMEM 3 /* no memory */ #define API_EBUSY 4 /* busy, occupied etc. */ #define API_EIO 5 /* I/O error */ +#define API_ESYSC 6 /* syscall error */ typedef int (*scp_t)(int, int *, ...); diff --git a/include/asm-arm/arch-at91rm9200/AT91RM9200.h b/include/asm-arm/arch-at91rm9200/AT91RM9200.h index 95db0177c..00bae1c4d 100644 --- a/include/asm-arm/arch-at91rm9200/AT91RM9200.h +++ b/include/asm-arm/arch-at91rm9200/AT91RM9200.h @@ -781,5 +781,32 @@ typedef struct _AT91S_PDC #define AT91C_PIOB_ODR ((AT91_REG *) 0xFFFFF614) /* (PIOB) Output Disable Registerr */ #define AT91C_PIOB_PDSR ((AT91_REG *) 0xFFFFF63C) /* (PIOB) Pin Data Status Register */ +#else +/* flash */ +#define AT91C_MC_PUIA 0xFFFFFF10 +#define AT91C_MC_PUP 0xFFFFFF50 +#define AT91C_MC_PUER 0xFFFFFF54 +#define AT91C_MC_ASR 0xFFFFFF04 +#define AT91C_MC_AASR 0xFFFFFF08 +#define AT91C_EBI_CFGR 0xFFFFFF64 +#define AT91C_SMC_CSR0 0xFFFFFF70 + +/* clocks */ +#define AT91C_PLLAR 0xFFFFFC28 +#define AT91C_PLLBR 0xFFFFFC2C +#define AT91C_MCKR 0xFFFFFC30 + +#define AT91C_BASE_CKGR 0xFFFFFC20 +#define AT91C_CKGR_MOR 0 + +/* sdram */ +#define AT91C_PIOC_ASR 0xFFFFF870 +#define AT91C_PIOC_BSR 0xFFFFF874 +#define AT91C_PIOC_PDR 0xFFFFF804 +#define AT91C_EBI_CSA 0xFFFFFF60 +#define AT91C_SDRC_CR 0xFFFFFF98 +#define AT91C_SDRC_MR 0xFFFFFF90 +#define AT91C_SDRC_TR 0xFFFFFF94 + #endif /* __ASSEMBLY__ */ #endif /* AT91RM9200_H */ diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index b04a718e6..3cdaa0247 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -34,7 +34,7 @@ #define CCM_PDR1 (CCM_BASE + 0x08) #define CCM_RCSR (CCM_BASE + 0x0c) #define CCM_MPCTL (CCM_BASE + 0x10) -#define CCM_UPCTL (CCM_BASE + 0x10) +#define CCM_UPCTL (CCM_BASE + 0x14) #define CCM_SPCTL (CCM_BASE + 0x18) #define CCM_COSR (CCM_BASE + 0x1C) #define CCM_CGR0 (CCM_BASE + 0x20) @@ -87,6 +87,16 @@ #define WDOG_BASE 0x53FDC000 /* + * GPIO + */ +#define GPIO1_BASE 0x53FCC000 +#define GPIO2_BASE 0x53FD0000 +#define GPIO3_BASE 0x53FA4000 +#define GPIO_DR 0x00000000 /* data register */ +#define GPIO_GDIR 0x00000004 /* direction register */ +#define GPIO_PSR 0x00000008 /* pad status register */ + +/* * Signal Multiplexing (IOMUX) */ diff --git a/include/asm-arm/arch-omap3/clocks.h b/include/asm-arm/arch-omap3/clocks.h new file mode 100644 index 000000000..71a0cb6ae --- /dev/null +++ b/include/asm-arm/arch-omap3/clocks.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_H_ +#define _CLOCKS_H_ + +#define LDELAY 12000000 + +#define S12M 12000000 +#define S13M 13000000 +#define S19_2M 19200000 +#define S24M 24000000 +#define S26M 26000000 +#define S38_4M 38400000 + +#define FCK_IVA2_ON 0x00000001 +#define FCK_CORE1_ON 0x03fffe29 +#define ICK_CORE1_ON 0x3ffffffb +#define ICK_CORE2_ON 0x0000001f +#define FCK_WKUP_ON 0x000000e9 +#define ICK_WKUP_ON 0x0000003f +#define FCK_DSS_ON 0x00000005 +#define ICK_DSS_ON 0x00000001 +#define FCK_CAM_ON 0x00000001 +#define ICK_CAM_ON 0x00000001 +#define FCK_PER_ON 0x0003ffff +#define ICK_PER_ON 0x0003ffff + +/* Used to index into DPLL parameter tables */ +typedef struct { + unsigned int m; + unsigned int n; + unsigned int fsel; + unsigned int m2; +} dpll_param; + +/* Following functions are exported from lowlevel_init.S */ +extern dpll_param *get_mpu_dpll_param(void); +extern dpll_param *get_iva_dpll_param(void); +extern dpll_param *get_core_dpll_param(void); +extern dpll_param *get_per_dpll_param(void); + +extern void *_end_vect, *_start; + +#endif diff --git a/include/asm-arm/arch-omap3/clocks_omap3.h b/include/asm-arm/arch-omap3/clocks_omap3.h new file mode 100644 index 000000000..661407b56 --- /dev/null +++ b/include/asm-arm/arch-omap3/clocks_omap3.h @@ -0,0 +1,285 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _CLOCKS_OMAP3_H_ +#define _CLOCKS_OMAP3_H_ + +#define PLL_STOP 1 /* PER & IVA */ +#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ +#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ +#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ + +/* + * The following configurations are OPP and SysClk value independant + * and hence are defined here. All the other DPLL related values are + * tabulated in lowlevel_init.S. + */ + +/* CORE DPLL */ +#define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ +#define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ +#define CORE_FUSB_DIV 2 /* 41.5MHz: */ +#define CORE_L4_DIV 2 /* 83MHz : L4 */ +#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ +#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ +#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ + +/* PER DPLL */ +#define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ +#define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ +#define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ +#define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ + +#define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) + +/* MPU DPLL */ + +#define MPU_M_12_ES1 0x0FE +#define MPU_N_12_ES1 0x07 +#define MPU_FSEL_12_ES1 0x05 +#define MPU_M2_12_ES1 0x01 + +#define MPU_M_12_ES2 0x0FA +#define MPU_N_12_ES2 0x05 +#define MPU_FSEL_12_ES2 0x07 +#define MPU_M2_ES2 0x01 + +#define MPU_M_12 0x085 +#define MPU_N_12 0x05 +#define MPU_FSEL_12 0x07 +#define MPU_M2_12 0x01 + +#define MPU_M_13_ES1 0x17D +#define MPU_N_13_ES1 0x0C +#define MPU_FSEL_13_ES1 0x03 +#define MPU_M2_13_ES1 0x01 + +#define MPU_M_13_ES2 0x1F4 +#define MPU_N_13_ES2 0x0C +#define MPU_FSEL_13_ES2 0x03 +#define MPU_M2_13_ES2 0x01 + +#define MPU_M_13 0x10A +#define MPU_N_13 0x0C +#define MPU_FSEL_13 0x03 +#define MPU_M2_13 0x01 + +#define MPU_M_19P2_ES1 0x179 +#define MPU_N_19P2_ES1 0x12 +#define MPU_FSEL_19P2_ES1 0x04 +#define MPU_M2_19P2_ES1 0x01 + +#define MPU_M_19P2_ES2 0x271 +#define MPU_N_19P2_ES2 0x17 +#define MPU_FSEL_19P2_ES2 0x03 +#define MPU_M2_19P2_ES2 0x01 + +#define MPU_M_19P2 0x14C +#define MPU_N_19P2 0x17 +#define MPU_FSEL_19P2 0x03 +#define MPU_M2_19P2 0x01 + +#define MPU_M_26_ES1 0x17D +#define MPU_N_26_ES1 0x19 +#define MPU_FSEL_26_ES1 0x03 +#define MPU_M2_26_ES1 0x01 + +#define MPU_M_26_ES2 0x0FA +#define MPU_N_26_ES2 0x0C +#define MPU_FSEL_26_ES2 0x07 +#define MPU_M2_26_ES2 0x01 + +#define MPU_M_26 0x085 +#define MPU_N_26 0x0C +#define MPU_FSEL_26 0x07 +#define MPU_M2_26 0x01 + +#define MPU_M_38P4_ES1 0x1FA +#define MPU_N_38P4_ES1 0x32 +#define MPU_FSEL_38P4_ES1 0x03 +#define MPU_M2_38P4_ES1 0x01 + +#define MPU_M_38P4_ES2 0x271 +#define MPU_N_38P4_ES2 0x2F +#define MPU_FSEL_38P4_ES2 0x03 +#define MPU_M2_38P4_ES2 0x01 + +#define MPU_M_38P4 0x14C +#define MPU_N_38P4 0x2F +#define MPU_FSEL_38P4 0x03 +#define MPU_M2_38P4 0x01 + +/* IVA DPLL */ + +#define IVA_M_12_ES1 0x07D +#define IVA_N_12_ES1 0x05 +#define IVA_FSEL_12_ES1 0x07 +#define IVA_M2_12_ES1 0x01 + +#define IVA_M_12_ES2 0x0B4 +#define IVA_N_12_ES2 0x05 +#define IVA_FSEL_12_ES2 0x07 +#define IVA_M2_12_ES2 0x01 + +#define IVA_M_12 0x085 +#define IVA_N_12 0x05 +#define IVA_FSEL_12 0x07 +#define IVA_M2_12 0x01 + +#define IVA_M_13_ES1 0x0FA +#define IVA_N_13_ES1 0x0C +#define IVA_FSEL_13_ES1 0x03 +#define IVA_M2_13_ES1 0x01 + +#define IVA_M_13_ES2 0x168 +#define IVA_N_13_ES2 0x0C +#define IVA_FSEL_13_ES2 0x03 +#define IVA_M2_13_ES2 0x01 + +#define IVA_M_13 0x10A +#define IVA_N_13 0x0C +#define IVA_FSEL_13 0x03 +#define IVA_M2_13 0x01 + +#define IVA_M_19P2_ES1 0x082 +#define IVA_N_19P2_ES1 0x09 +#define IVA_FSEL_19P2_ES1 0x07 +#define IVA_M2_19P2_ES1 0x01 + +#define IVA_M_19P2_ES2 0x0E1 +#define IVA_N_19P2_ES2 0x0B +#define IVA_FSEL_19P2_ES2 0x06 +#define IVA_M2_19P2_ES2 0x01 + +#define IVA_M_19P2 0x14C +#define IVA_N_19P2 0x17 +#define IVA_FSEL_19P2 0x03 +#define IVA_M2_19P2 0x01 + +#define IVA_M_26_ES1 0x07D +#define IVA_N_26_ES1 0x0C +#define IVA_FSEL_26_ES1 0x07 +#define IVA_M2_26_ES1 0x01 + +#define IVA_M_26_ES2 0x0B4 +#define IVA_N_26_ES2 0x0C +#define IVA_FSEL_26_ES2 0x07 +#define IVA_M2_26_ES2 0x01 + +#define IVA_M_26 0x085 +#define IVA_N_26 0x0C +#define IVA_FSEL_26 0x07 +#define IVA_M2_26 0x01 + +#define IVA_M_38P4_ES1 0x13F +#define IVA_N_38P4_ES1 0x30 +#define IVA_FSEL_38P4_ES1 0x03 +#define IVA_M2_38P4_ES1 0x01 + +#define IVA_M_38P4_ES2 0x0E1 +#define IVA_N_38P4_ES2 0x17 +#define IVA_FSEL_38P4_ES2 0x06 +#define IVA_M2_38P4_ES2 0x01 + +#define IVA_M_38P4 0x14C +#define IVA_N_38P4 0x2F +#define IVA_FSEL_38P4 0x03 +#define IVA_M2_38P4 0x01 + +/* CORE DPLL */ + +#define CORE_M_12 0xA6 +#define CORE_N_12 0x05 +#define CORE_FSEL_12 0x07 +#define CORE_M2_12 0x01 /* M3 of 2 */ + +#define CORE_M_12_ES1 0x19F +#define CORE_N_12_ES1 0x0E +#define CORE_FSL_12_ES1 0x03 +#define CORE_M2_12_ES1 0x1 /* M3 of 2 */ + +#define CORE_M_13 0x14C +#define CORE_N_13 0x0C +#define CORE_FSEL_13 0x03 +#define CORE_M2_13 0x01 /* M3 of 2 */ + +#define CORE_M_13_ES1 0x1B2 +#define CORE_N_13_ES1 0x10 +#define CORE_FSL_13_ES1 0x03 +#define CORE_M2_13_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_19P2 0x19F +#define CORE_N_19P2 0x17 +#define CORE_FSEL_19P2 0x03 +#define CORE_M2_19P2 0x01 /* M3 of 2 */ + +#define CORE_M_19P2_ES1 0x19F +#define CORE_N_19P2_ES1 0x17 +#define CORE_FSL_19P2_ES1 0x03 +#define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_26 0xA6 +#define CORE_N_26 0x0C +#define CORE_FSEL_26 0x07 +#define CORE_M2_26 0x01 /* M3 of 2 */ + +#define CORE_M_26_ES1 0x1B2 +#define CORE_N_26_ES1 0x21 +#define CORE_FSL_26_ES1 0x03 +#define CORE_M2_26_ES1 0x01 /* M3 of 2 */ + +#define CORE_M_38P4 0x19F +#define CORE_N_38P4 0x2F +#define CORE_FSEL_38P4 0x03 +#define CORE_M2_38P4 0x01 /* M3 of 2 */ + +#define CORE_M_38P4_ES1 0x19F +#define CORE_N_38P4_ES1 0x2F +#define CORE_FSL_38P4_ES1 0x03 +#define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ + +/* PER DPLL */ + +#define PER_M_12 0xD8 +#define PER_N_12 0x05 +#define PER_FSEL_12 0x07 +#define PER_M2_12 0x09 + +#define PER_M_13 0x1B0 +#define PER_N_13 0x0C +#define PER_FSEL_13 0x03 +#define PER_M2_13 0x09 + +#define PER_M_19P2 0xE1 +#define PER_N_19P2 0x09 +#define PER_FSEL_19P2 0x07 +#define PER_M2_19P2 0x09 + +#define PER_M_26 0xD8 +#define PER_N_26 0x0C +#define PER_FSEL_26 0x07 +#define PER_M2_26 0x09 + +#define PER_M_38P4 0xE1 +#define PER_N_38P4 0x13 +#define PER_FSEL_38P4 0x07 +#define PER_M2_38P4 0x09 + +#endif /* endif _CLOCKS_OMAP3_H_ */ diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h new file mode 100644 index 000000000..5b344f837 --- /dev/null +++ b/include/asm-arm/arch-omap3/cpu.h @@ -0,0 +1,422 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _CPU_H +#define _CPU_H + +/* Register offsets of common modules */ +/* Control */ +#ifndef __ASSEMBLY__ +typedef struct ctrl { + unsigned char res1[0xC0]; + unsigned short gpmc_nadv_ale; /* 0xC0 */ + unsigned short gpmc_noe; /* 0xC2 */ + unsigned short gpmc_nwe; /* 0xC4 */ + unsigned char res2[0x22A]; + unsigned int status; /* 0x2F0 */ + unsigned int gpstatus; /* 0x2F4 */ + unsigned char res3[0x08]; + unsigned int rpubkey_0; /* 0x300 */ + unsigned int rpubkey_1; /* 0x304 */ + unsigned int rpubkey_2; /* 0x308 */ + unsigned int rpubkey_3; /* 0x30C */ + unsigned int rpubkey_4; /* 0x310 */ + unsigned char res4[0x04]; + unsigned int randkey_0; /* 0x318 */ + unsigned int randkey_1; /* 0x31C */ + unsigned int randkey_2; /* 0x320 */ + unsigned int randkey_3; /* 0x324 */ + unsigned char res5[0x124]; + unsigned int ctrl_omap_stat; /* 0x44C */ +} ctrl_t; +#else /* __ASSEMBLY__ */ +#define CONTROL_STATUS 0x2F0 +#endif /* __ASSEMBLY__ */ + +/* cpu type */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + +/* device type */ +#define DEVICE_MASK (0x7 << 8) +#define SYSBOOT_MASK 0x1F +#define TST_DEVICE 0x0 +#define EMU_DEVICE 0x1 +#define HS_DEVICE 0x2 +#define GP_DEVICE 0x3 + +/* GPMC CS3/cs4/cs6 not avaliable */ +#define GPMC_BASE (OMAP34XX_GPMC_BASE) +#define GPMC_CONFIG_CS0 0x60 +#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) +#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_WP 0x10 + +#define GPMC_CONFIG_WIDTH 0x30 + +#ifndef __ASSEMBLY__ +typedef struct gpmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x4]; + unsigned int irqstatus; /* 0x18 */ + unsigned int irqenable; /* 0x1C */ + unsigned char res3[0x20]; + unsigned int timeout_control; /* 0x40 */ + unsigned char res4[0xC]; + unsigned int config; /* 0x50 */ + unsigned int status; /* 0x54 */ + unsigned char res5[0x19C]; + unsigned int ecc_config; /* 0x1F4 */ + unsigned int ecc_control; /* 0x1F8 */ + unsigned int ecc_size_config; /* 0x1FC */ + unsigned int ecc1_result; /* 0x200 */ + unsigned int ecc2_result; /* 0x204 */ + unsigned int ecc3_result; /* 0x208 */ + unsigned int ecc4_result; /* 0x20C */ + unsigned int ecc5_result; /* 0x210 */ + unsigned int ecc6_result; /* 0x214 */ + unsigned int ecc7_result; /* 0x218 */ + unsigned int ecc8_result; /* 0x21C */ + unsigned int ecc9_result; /* 0x220 */ +} gpmc_t; + +typedef struct gpmc_csx { + unsigned int config1; /* 0x00 */ + unsigned int config2; /* 0x04 */ + unsigned int config3; /* 0x08 */ + unsigned int config4; /* 0x0C */ + unsigned int config5; /* 0x10 */ + unsigned int config6; /* 0x14 */ + unsigned int config7; /* 0x18 */ + unsigned int nand_cmd; /* 0x1C */ + unsigned int nand_adr; /* 0x20 */ + unsigned int nand_dat; /* 0x24 */ +} gpmc_csx_t; +#else /* __ASSEMBLY__ */ +#define GPMC_CONFIG1 0x00 +#define GPMC_CONFIG2 0x04 +#define GPMC_CONFIG3 0x08 +#define GPMC_CONFIG4 0x0C +#define GPMC_CONFIG5 0x10 +#define GPMC_CONFIG6 0x14 +#define GPMC_CONFIG7 0x18 +#endif /* __ASSEMBLY__ */ + +/* GPMC Mapping */ +#define FLASH_BASE 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */ + /* aligned to 64 Meg */ +#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */ + /* aligned to 256 Meg */ +#define DEBUG_BASE 0x08000000 /* debug board */ +#define NAND_BASE 0x30000000 /* NAND addr */ + /* (actual size small port) */ +#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */ +#define ONENAND_MAP 0x20000000 /* OneNand addr */ + /* (actual size small port) */ +/* SMS */ +#ifndef __ASSEMBLY__ +typedef struct sms { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned char res2[0x34]; + unsigned int rg_att0; /* 0x48 */ + unsigned char res3[0x84]; + unsigned int class_arb0; /* 0xD0 */ +} sms_t; +#endif /* __ASSEMBLY__ */ + +#define BURSTCOMPLETE_GROUP7 (0x1 << 31) + +/* SDRC */ +#ifndef __ASSEMBLY__ +typedef struct sdrc_cs { + unsigned int mcfg; /* 0x80 || 0xB0 */ + unsigned int mr; /* 0x84 || 0xB4 */ + unsigned char res1[0x4]; + unsigned int emr2; /* 0x8C || 0xBC */ + unsigned char res2[0x14]; + unsigned int rfr_ctrl; /* 0x84 || 0xD4 */ + unsigned int manual; /* 0xA8 || 0xD8 */ + unsigned char res3[0x4]; +} sdrc_cs_t; + +typedef struct sdrc_actim { + unsigned int ctrla; /* 0x9C || 0xC4 */ + unsigned int ctrlb; /* 0xA0 || 0xC8 */ +} sdrc_actim_t; + +typedef struct sdrc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int status; /* 0x14 */ + unsigned char res2[0x28]; + unsigned int cs_cfg; /* 0x40 */ + unsigned int sharing; /* 0x44 */ + unsigned char res3[0x18]; + unsigned int dlla_ctrl; /* 0x60 */ + unsigned int dlla_status; /* 0x64 */ + unsigned int dllb_ctrl; /* 0x68 */ + unsigned int dllb_status; /* 0x6C */ + unsigned int power; /* 0x70 */ + unsigned char res4[0xC]; + sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */ +} sdrc_t; +#endif /* __ASSEMBLY__ */ + +#define DLLPHASE_90 (0x1 << 1) +#define LOADDLL (0x1 << 2) +#define ENADLL (0x1 << 3) +#define DLL_DELAY_MASK 0xFF00 +#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8)) + +#define PAGEPOLICY_HIGH (0x1 << 0) +#define SRFRONRESET (0x1 << 7) +#define WAKEUPPROC (0x1 << 26) + +#define DDR_SDRAM (0x1 << 0) +#define DEEPPD (0x1 << 3) +#define B32NOT16 (0x1 << 4) +#define BANKALLOCATION (0x2 << 6) +#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */ +#define ADDRMUXLEGACY (0x1 << 19) +#define CASWIDTH_10BITS (0x5 << 20) +#define RASWIDTH_13BITS (0x2 << 24) +#define BURSTLENGTH4 (0x2 << 0) +#define CASL3 (0x3 << 4) +#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C) +#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4) +#define ARE_ARCV_1 (0x1 << 0) +#define ARCV (0x4e2 << 8) /* Autorefresh count */ +#define OMAP34XX_SDRC_CS0 0x80000000 +#define OMAP34XX_SDRC_CS1 0xA0000000 +#define CMD_NOP 0x0 +#define CMD_PRECHARGE 0x1 +#define CMD_AUTOREFRESH 0x2 +#define CMD_ENTR_PWRDOWN 0x3 +#define CMD_EXIT_PWRDOWN 0x4 +#define CMD_ENTR_SRFRSH 0x5 +#define CMD_CKE_HIGH 0x6 +#define CMD_CKE_LOW 0x7 +#define SOFTRESET (0x1 << 1) +#define SMART_IDLE (0x2 << 3) +#define REF_ON_IDLE (0x1 << 6) + +/* timer regs offsets (32 bit regs) */ + +#ifndef __ASSEMBLY__ +typedef struct gptimer { + unsigned int tidr; /* 0x00 r */ + unsigned char res[0xc]; + unsigned int tiocp_cfg; /* 0x10 rw */ + unsigned int tistat; /* 0x14 r */ + unsigned int tisr; /* 0x18 rw */ + unsigned int tier; /* 0x1c rw */ + unsigned int twer; /* 0x20 rw */ + unsigned int tclr; /* 0x24 rw */ + unsigned int tcrr; /* 0x28 rw */ + unsigned int tldr; /* 0x2c rw */ + unsigned int ttgr; /* 0x30 rw */ + unsigned int twpc; /* 0x34 r*/ + unsigned int tmar; /* 0x38 rw*/ + unsigned int tcar1; /* 0x3c r */ + unsigned int tcicr; /* 0x40 rw */ + unsigned int tcar2; /* 0x44 r */ +} gptimer_t; +#endif /* __ASSEMBLY__ */ + +/* enable sys_clk NO-prescale /1 */ +#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0)) + +/* Watchdog */ +#ifndef __ASSEMBLY__ +typedef struct watchdog { + unsigned char res1[0x34]; + unsigned int wwps; /* 0x34 r */ + unsigned char res2[0x10]; + unsigned int wspr; /* 0x48 rw */ +} watchdog_t; +#endif /* __ASSEMBLY__ */ + +#define WD_UNLOCK1 0xAAAA +#define WD_UNLOCK2 0x5555 + +/* PRCM */ +#define PRCM_BASE 0x48004000 + +#ifndef __ASSEMBLY__ +typedef struct prcm { + unsigned int fclken_iva2; /* 0x00 */ + unsigned int clken_pll_iva2; /* 0x04 */ + unsigned char res1[0x1c]; + unsigned int idlest_pll_iva2; /* 0x24 */ + unsigned char res2[0x18]; + unsigned int clksel1_pll_iva2 ; /* 0x40 */ + unsigned int clksel2_pll_iva2; /* 0x44 */ + unsigned char res3[0x8bc]; + unsigned int clken_pll_mpu; /* 0x904 */ + unsigned char res4[0x1c]; + unsigned int idlest_pll_mpu; /* 0x924 */ + unsigned char res5[0x18]; + unsigned int clksel1_pll_mpu; /* 0x940 */ + unsigned int clksel2_pll_mpu; /* 0x944 */ + unsigned char res6[0xb8]; + unsigned int fclken1_core; /* 0xa00 */ + unsigned char res7[0xc]; + unsigned int iclken1_core; /* 0xa10 */ + unsigned int iclken2_core; /* 0xa14 */ + unsigned char res8[0x28]; + unsigned int clksel_core; /* 0xa40 */ + unsigned char res9[0xbc]; + unsigned int fclken_gfx; /* 0xb00 */ + unsigned char res10[0xc]; + unsigned int iclken_gfx; /* 0xb10 */ + unsigned char res11[0x2c]; + unsigned int clksel_gfx; /* 0xb40 */ + unsigned char res12[0xbc]; + unsigned int fclken_wkup; /* 0xc00 */ + unsigned char res13[0xc]; + unsigned int iclken_wkup; /* 0xc10 */ + unsigned char res14[0xc]; + unsigned int idlest_wkup; /* 0xc20 */ + unsigned char res15[0x1c]; + unsigned int clksel_wkup; /* 0xc40 */ + unsigned char res16[0xbc]; + unsigned int clken_pll; /* 0xd00 */ + unsigned char res17[0x1c]; + unsigned int idlest_ckgen; /* 0xd20 */ + unsigned char res18[0x1c]; + unsigned int clksel1_pll; /* 0xd40 */ + unsigned int clksel2_pll; /* 0xd44 */ + unsigned int clksel3_pll; /* 0xd48 */ + unsigned char res19[0xb4]; + unsigned int fclken_dss; /* 0xe00 */ + unsigned char res20[0xc]; + unsigned int iclken_dss; /* 0xe10 */ + unsigned char res21[0x2c]; + unsigned int clksel_dss; /* 0xe40 */ + unsigned char res22[0xbc]; + unsigned int fclken_cam; /* 0xf00 */ + unsigned char res23[0xc]; + unsigned int iclken_cam; /* 0xf10 */ + unsigned char res24[0x2c]; + unsigned int clksel_cam; /* 0xf40 */ + unsigned char res25[0xbc]; + unsigned int fclken_per; /* 0x1000 */ + unsigned char res26[0xc]; + unsigned int iclken_per; /* 0x1010 */ + unsigned char res27[0x2c]; + unsigned int clksel_per; /* 0x1040 */ + unsigned char res28[0xfc]; + unsigned int clksel1_emu; /* 0x1140 */ +} prcm_t; +#else /* __ASSEMBLY__ */ +#define CM_CLKSEL_CORE 0x48004a40 +#define CM_CLKSEL_GFX 0x48004b40 +#define CM_CLKSEL_WKUP 0x48004c40 +#define CM_CLKEN_PLL 0x48004d00 +#define CM_CLKSEL1_PLL 0x48004d40 +#define CM_CLKSEL1_EMU 0x48005140 +#endif /* __ASSEMBLY__ */ + +#define PRM_BASE 0x48306000 + +#ifndef __ASSEMBLY__ +typedef struct prm { + unsigned char res1[0xd40]; + unsigned int clksel; /* 0xd40 */ + unsigned char res2[0x50c]; + unsigned int rstctrl; /* 0x1250 */ + unsigned char res3[0x1c]; + unsigned int clksrc_ctrl; /* 0x1270 */ +} prm_t; +#else /* __ASSEMBLY__ */ +#define PRM_RSTCTRL 0x48307250 +#endif /* __ASSEMBLY__ */ + +#define SYSCLKDIV_1 (0x1 << 6) +#define SYSCLKDIV_2 (0x1 << 7) + +#define CLKSEL_GPT1 (0x1 << 0) + +#define EN_GPT1 (0x1 << 0) +#define EN_32KSYNC (0x1 << 2) + +#define ST_WDT2 (0x1 << 5) + +#define ST_MPU_CLK (0x1 << 0) + +#define ST_CORE_CLK (0x1 << 0) + +#define ST_PERIPH_CLK (0x1 << 1) + +#define ST_IVA2_CLK (0x1 << 0) + +#define RESETDONE (0x1 << 0) + +#define TCLR_ST (0x1 << 0) +#define TCLR_AR (0x1 << 1) +#define TCLR_PRE (0x1 << 5) + +/* SMX-APE */ +#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000) +#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400) +#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800) +#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000) + +#ifndef __ASSEMBLY__ +typedef struct pm { + unsigned char res1[0x48]; + unsigned int req_info_permission_0; /* 0x48 */ + unsigned char res2[0x4]; + unsigned int read_permission_0; /* 0x50 */ + unsigned char res3[0x4]; + unsigned int wirte_permission_0; /* 0x58 */ + unsigned char res4[0x4]; + unsigned int addr_match_1; /* 0x58 */ + unsigned char res5[0x4]; + unsigned int req_info_permission_1; /* 0x68 */ + unsigned char res6[0x14]; + unsigned int addr_match_2; /* 0x80 */ +} pm_t; +#endif /*__ASSEMBLY__ */ + +/* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + +#define NOT_EARLY 0 + +/* I2C base */ +#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000) +#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000) +#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000) + +#endif /* _CPU_H */ diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch-omap3/i2c.h new file mode 100644 index 000000000..3937f3525 --- /dev/null +++ b/include/asm-arm/arch-omap3/i2c.h @@ -0,0 +1,128 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _I2C_H_ +#define _I2C_H_ + +#define I2C_DEFAULT_BASE I2C_BASE1 + +#define I2C_REV (I2C_DEFAULT_BASE + 0x00) +#define I2C_IE (I2C_DEFAULT_BASE + 0x04) +#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) +#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) +#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) +#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) +#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) +#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) +#define I2C_CON (I2C_DEFAULT_BASE + 0x24) +#define I2C_OA (I2C_DEFAULT_BASE + 0x28) +#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) +#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) +#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) +#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) +#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) + +/* I2C masks */ + +/* I2C Interrupt Enable Register (I2C_IE): */ +#define I2C_IE_GC_IE (1 << 5) +#define I2C_IE_XRDY_IE (1 << 4) /* Transmit data ready interrupt enable */ +#define I2C_IE_RRDY_IE (1 << 3) /* Receive data ready interrupt enable */ +#define I2C_IE_ARDY_IE (1 << 2) /* Register access ready interrupt enable */ +#define I2C_IE_NACK_IE (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_IE_AL_IE (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Status Register (I2C_STAT): */ + +#define I2C_STAT_SBD (1 << 15) /* Single byte data */ +#define I2C_STAT_BB (1 << 12) /* Bus busy */ +#define I2C_STAT_ROVR (1 << 11) /* Receive overrun */ +#define I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ +#define I2C_STAT_AAS (1 << 9) /* Address as slave */ +#define I2C_STAT_GC (1 << 5) +#define I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ +#define I2C_STAT_RRDY (1 << 3) /* Receive data ready */ +#define I2C_STAT_ARDY (1 << 2) /* Register access ready */ +#define I2C_STAT_NACK (1 << 1) /* No acknowledgment interrupt enable */ +#define I2C_STAT_AL (1 << 0) /* Arbitration lost interrupt enable */ + +/* I2C Interrupt Code Register (I2C_INTCODE): */ + +#define I2C_INTCODE_MASK 7 +#define I2C_INTCODE_NONE 0 +#define I2C_INTCODE_AL 1 /* Arbitration lost */ +#define I2C_INTCODE_NAK 2 /* No acknowledgement/general call */ +#define I2C_INTCODE_ARDY 3 /* Register access ready */ +#define I2C_INTCODE_RRDY 4 /* Rcv data ready */ +#define I2C_INTCODE_XRDY 5 /* Xmit data ready */ + +/* I2C Buffer Configuration Register (I2C_BUF): */ + +#define I2C_BUF_RDMA_EN (1 << 15) /* Receive DMA channel enable */ +#define I2C_BUF_XDMA_EN (1 << 7) /* Transmit DMA channel enable */ + +/* I2C Configuration Register (I2C_CON): */ + +#define I2C_CON_EN (1 << 15) /* I2C module enable */ +#define I2C_CON_BE (1 << 14) /* Big endian mode */ +#define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */ +#define I2C_CON_MST (1 << 10) /* Master/slave mode */ +#define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */ + /* (master mode only) */ +#define I2C_CON_XA (1 << 8) /* Expand address */ +#define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */ +#define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */ + +/* I2C System Test Register (I2C_SYSTEST): */ + +#define I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ +#define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */ +#define I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ +#define I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense input value */ +#define I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive output value */ +#define I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense input value */ +#define I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive output value */ + +#define I2C_SCLL_SCLL 0 +#define I2C_SCLL_SCLL_M 0xFF +#define I2C_SCLL_HSSCLL 8 +#define I2C_SCLH_HSSCLL_M 0xFF +#define I2C_SCLH_SCLH 0 +#define I2C_SCLH_SCLH_M 0xFF +#define I2C_SCLH_HSSCLH 8 +#define I2C_SCLH_HSSCLH_M 0xFF + +#define OMAP_I2C_STANDARD 100 +#define OMAP_I2C_FAST_MODE 400 +#define OMAP_I2C_HIGH_SPEED 3400 + +#define SYSTEM_CLOCK_12 12000 +#define SYSTEM_CLOCK_13 13000 +#define SYSTEM_CLOCK_192 19200 +#define SYSTEM_CLOCK_96 96000 + +#define I2C_IP_CLK SYSTEM_CLOCK_96 +#define I2C_PSC_MAX 0x0f +#define I2C_PSC_MIN 0x00 + +#endif /* _I2C_H_ */ diff --git a/include/asm-arm/arch-omap3/mem.h b/include/asm-arm/arch-omap3/mem.h new file mode 100644 index 000000000..6f0f90b60 --- /dev/null +++ b/include/asm-arm/arch-omap3/mem.h @@ -0,0 +1,227 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _MEM_H_ +#define _MEM_H_ + +#define CS0 0x0 +#define CS1 0x1 /* mirror CS1 regs appear offset 0x30 from CS0 */ + +#ifndef __ASSEMBLY__ +typedef enum { + STACKED = 0, + IP_DDR = 1, + COMBO_DDR = 2, + IP_SDR = 3, +} mem_t; +#endif /* __ASSEMBLY__ */ + +#define EARLY_INIT 1 + +/* Slower full frequency range default timings for x32 operation*/ +#define SDP_SDRC_SHARING 0x00000100 +#define SDP_SDRC_MR_0_SDR 0x00000031 + +/* optimized timings good for current shipping parts */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ + +#define DLL_OFFSET 0 +#define DLL_WRITEDDRCLKX2DIS 1 +#define DLL_ENADLL 1 +#define DLL_LOCKDLL 0 +#define DLL_DLLPHASE_72 0 +#define DLL_DLLPHASE_90 1 + +/* rkw - need to find of 90/72 degree recommendation for speed like before */ +#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ + (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1)) + +/* Infineon part of 3430SDP (165MHz optimized) 6.06ns + * ACTIMA + * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 + * TDPL (Twr) = 15/6 = 2.5 -> 3 + * TRRD = 12/6 = 2 + * TRCD = 18/6 = 3 + * TRP = 18/6 = 3 + * TRAS = 42/6 = 7 + * TRC = 60/6 = 10 + * TRFC = 72/6 = 12 + * ACTIMB + * TCKE = 2 + * XSR = 120/6 = 20 + */ +#define TDAL_165 6 +#define TDPL_165 3 +#define TRRD_165 2 +#define TRCD_165 3 +#define TRP_165 3 +#define TRAS_165 7 +#define TRC_165 10 +#define TRFC_165 21 +#define V_ACTIMA_165 ((TRFC_165 << 27) | (TRC_165 << 22) | \ + (TRAS_165 << 18) | (TRP_165 << 15) | \ + (TRCD_165 << 12) | (TRRD_165 << 9) | \ + (TDPL_165 << 6) | (TDAL_165)) + +#define TWTR_165 1 +#define TCKE_165 1 +#define TXP_165 5 +#define XSR_165 23 +#define V_ACTIMB_165 (((TCKE_165 << 12) | (XSR_165 << 0)) | \ + (TXP_165 << 8) | (TWTR_165 << 16)) + +#define SDP_SDRC_ACTIM_CTRLA_0 V_ACTIMA_165 +#define SDP_SDRC_ACTIM_CTRLB_0 V_ACTIMB_165 +#define SDP_SDRC_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz + +/* + * GPMC settings - + * Definitions is as per the following format + * #define <PART>_GPMC_CONFIG<x> <value> + * Where: + * PART is the part name e.g. STNOR - Intel Strata Flash + * x is GPMC config registers from 1 to 6 (there will be 6 macros) + * Value is corresponding value + * + * For every valid PRCM configuration there should be only one definition of + * the same. if values are independent of the board, this definition will be + * present in this file if values are dependent on the board, then this should + * go into corresponding mem-boardName.h file + * + * Currently valid part Names are (PART): + * STNOR - Intel Strata Flash + * SMNAND - Samsung NAND + * MPDB - H4 MPDB board + * SBNOR - Sibley NOR + * MNAND - Micron Large page x16 NAND + * ONNAND - Samsung One NAND + * + * include/configs/file.h contains the defn - for all CS we are interested + * #define OMAP34XX_GPMC_CSx PART + * #define OMAP34XX_GPMC_CSx_SIZE Size + * #define OMAP34XX_GPMC_CSx_MAP Map + * Where: + * x - CS number + * PART - Part Name as defined above + * SIZE - how big is the mapping to be + * GPMC_SIZE_128M - 0x8 + * GPMC_SIZE_64M - 0xC + * GPMC_SIZE_32M - 0xE + * GPMC_SIZE_16M - 0xF + * MAP - Map this CS to which address(GPMC address space)- Absolute address + * >>24 before being used. + */ +#define GPMC_SIZE_128M 0x8 +#define GPMC_SIZE_64M 0xC +#define GPMC_SIZE_32M 0xE +#define GPMC_SIZE_16M 0xF + +#define SMNAND_GPMC_CONFIG1 0x00000800 +#define SMNAND_GPMC_CONFIG2 0x00141400 +#define SMNAND_GPMC_CONFIG3 0x00141400 +#define SMNAND_GPMC_CONFIG4 0x0F010F01 +#define SMNAND_GPMC_CONFIG5 0x010C1414 +#define SMNAND_GPMC_CONFIG6 0x1F0F0A80 +#define SMNAND_GPMC_CONFIG7 0x00000C44 + +#define M_NAND_GPMC_CONFIG1 0x00001800 +#define M_NAND_GPMC_CONFIG2 0x00141400 +#define M_NAND_GPMC_CONFIG3 0x00141400 +#define M_NAND_GPMC_CONFIG4 0x0F010F01 +#define M_NAND_GPMC_CONFIG5 0x010C1414 +#define M_NAND_GPMC_CONFIG6 0x1f0f0A80 +#define M_NAND_GPMC_CONFIG7 0x00000C44 + +#define STNOR_GPMC_CONFIG1 0x3 +#define STNOR_GPMC_CONFIG2 0x00151501 +#define STNOR_GPMC_CONFIG3 0x00060602 +#define STNOR_GPMC_CONFIG4 0x11091109 +#define STNOR_GPMC_CONFIG5 0x01141F1F +#define STNOR_GPMC_CONFIG6 0x000004c4 + +#define SIBNOR_GPMC_CONFIG1 0x1200 +#define SIBNOR_GPMC_CONFIG2 0x001f1f00 +#define SIBNOR_GPMC_CONFIG3 0x00080802 +#define SIBNOR_GPMC_CONFIG4 0x1C091C09 +#define SIBNOR_GPMC_CONFIG5 0x01131F1F +#define SIBNOR_GPMC_CONFIG6 0x1F0F03C2 + +#define SDPV2_MPDB_GPMC_CONFIG1 0x00611200 +#define SDPV2_MPDB_GPMC_CONFIG2 0x001F1F01 +#define SDPV2_MPDB_GPMC_CONFIG3 0x00080803 +#define SDPV2_MPDB_GPMC_CONFIG4 0x1D091D09 +#define SDPV2_MPDB_GPMC_CONFIG5 0x041D1F1F +#define SDPV2_MPDB_GPMC_CONFIG6 0x1D0904C4 + +#define MPDB_GPMC_CONFIG1 0x00011000 +#define MPDB_GPMC_CONFIG2 0x001f1f01 +#define MPDB_GPMC_CONFIG3 0x00080803 +#define MPDB_GPMC_CONFIG4 0x1c0b1c0a +#define MPDB_GPMC_CONFIG5 0x041f1F1F +#define MPDB_GPMC_CONFIG6 0x1F0F04C4 + +#define P2_GPMC_CONFIG1 0x0 +#define P2_GPMC_CONFIG2 0x0 +#define P2_GPMC_CONFIG3 0x0 +#define P2_GPMC_CONFIG4 0x0 +#define P2_GPMC_CONFIG5 0x0 +#define P2_GPMC_CONFIG6 0x0 + +#define ONENAND_GPMC_CONFIG1 0x00001200 +#define ONENAND_GPMC_CONFIG2 0x000F0F01 +#define ONENAND_GPMC_CONFIG3 0x00030301 +#define ONENAND_GPMC_CONFIG4 0x0F040F04 +#define ONENAND_GPMC_CONFIG5 0x010F1010 +#define ONENAND_GPMC_CONFIG6 0x1F060000 + +#define NET_GPMC_CONFIG1 0x00001000 +#define NET_GPMC_CONFIG2 0x001e1e01 +#define NET_GPMC_CONFIG3 0x00080300 +#define NET_GPMC_CONFIG4 0x1c091c09 +#define NET_GPMC_CONFIG5 0x04181f1f +#define NET_GPMC_CONFIG6 0x00000FCF +#define NET_GPMC_CONFIG7 0x00000f6c + +/* max number of GPMC Chip Selects */ +#define GPMC_MAX_CS 8 +/* max number of GPMC regs */ +#define GPMC_MAX_REG 7 + +#define PISMO1_NOR 1 +#define PISMO1_NAND 2 +#define PISMO2_CS0 3 +#define PISMO2_CS1 4 +#define PISMO1_ONENAND 5 +#define DBG_MPDB 6 +#define PISMO2_NAND_CS0 7 +#define PISMO2_NAND_CS1 8 + +/* make it readable for the gpmc_init */ +#define PISMO1_NOR_BASE FLASH_BASE +#define PISMO1_NAND_BASE NAND_BASE +#define PISMO2_CS0_BASE PISMO2_MAP1 +#define PISMO1_ONEN_BASE ONENAND_MAP +#define DBG_MPDB_BASE DEBUG_BASE + +#endif /* endif _MEM_H_ */ diff --git a/include/asm-arm/arch-omap3/mmc.h b/include/asm-arm/arch-omap3/mmc.h new file mode 100644 index 000000000..55584d9f7 --- /dev/null +++ b/include/asm-arm/arch-omap3/mmc.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_H +#define MMC_H + +#include "mmc_host_def.h" + +/* Responses */ +#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R1 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R1B (RSP_TYPE_LGHT48B | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R2 (RSP_TYPE_LGHT136 | CCCE_CHECK | CICE_NOCHECK) +#define RSP_TYPE_R3 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R4 (RSP_TYPE_LGHT48 | CCCE_NOCHECK | CICE_NOCHECK) +#define RSP_TYPE_R5 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R6 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) +#define RSP_TYPE_R7 (RSP_TYPE_LGHT48 | CCCE_CHECK | CICE_CHECK) + +/* All supported commands */ +#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD1 (INDEX(1) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD2 (INDEX(2) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD3 (INDEX(3) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_SDCMD3 (INDEX(3) | RSP_TYPE_R6 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD4 (INDEX(4) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD6 (INDEX(6) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_SELECT (INDEX(7) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD7_DESELECT (INDEX(7)| RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD8 (INDEX(8) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_SDCMD8 (INDEX(8) | RSP_TYPE_R7 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD9 (INDEX(9) | RSP_TYPE_R2 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD12 (INDEX(12) | RSP_TYPE_R1B | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD13 (INDEX(13) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD15 (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD16 (INDEX(16) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_CMD17 (INDEX(17) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD24 (INDEX(24) | RSP_TYPE_R1 | DP_DATA | DDIR_WRITE) +#define MMC_ACMD6 (INDEX(6) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD41 (INDEX(41) | RSP_TYPE_R3 | DP_NO_DATA | DDIR_WRITE) +#define MMC_ACMD51 (INDEX(51) | RSP_TYPE_R1 | DP_DATA | DDIR_READ) +#define MMC_CMD55 (INDEX(55) | RSP_TYPE_R1 | DP_NO_DATA | DDIR_WRITE) + +#define MMC_AC_CMD_RCA_MASK (unsigned int)(0xFFFF << 16) +#define MMC_BC_CMD_DSR_MASK (unsigned int)(0xFFFF << 16) +#define MMC_DSR_DEFAULT 0x0404 +#define SD_CMD8_CHECK_PATTERN 0xAA +#define SD_CMD8_2_7_3_6_V_RANGE (0x01 << 8) + +/* Clock Configurations and Macros */ + +#define MMC_CLOCK_REFERENCE 96 +#define MMC_RELATIVE_CARD_ADDRESS 0x1234 +#define MMC_INIT_SEQ_CLK (MMC_CLOCK_REFERENCE * 1000 / 80) +#define MMC_400kHz_CLK (MMC_CLOCK_REFERENCE * 1000 / 400) +#define CLKDR(r, f, u) ((((r)*100) / ((f)*(u))) + 1) +#define CLKD(f, u) (CLKDR(MMC_CLOCK_REFERENCE, f, u)) + +#define MMC_OCR_REG_ACCESS_MODE_MASK (0x3 << 29) +#define MMC_OCR_REG_ACCESS_MODE_BYTE (0x0 << 29) +#define MMC_OCR_REG_ACCESS_MODE_SECTOR (0x2 << 29) + +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK (0x1 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE (0x0 << 30) +#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR (0x1 << 30) + +#define MMC_SD2_CSD_C_SIZE_LSB_MASK 0xFFFF +#define MMC_SD2_CSD_C_SIZE_MSB_MASK 0x003F +#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET 16 +#define MMC_CSD_C_SIZE_LSB_MASK 0x0003 +#define MMC_CSD_C_SIZE_MSB_MASK 0x03FF +#define MMC_CSD_C_SIZE_MSB_OFFSET 2 + +#define MMC_CSD_TRAN_SPEED_UNIT_MASK (0x07 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_MASK (0x0F << 3) +#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ (0x3 << 0) +#define MMC_CSD_TRAN_SPEED_FACTOR_1_0 (0x01 << 3) +#define MMC_CSD_TRAN_SPEED_FACTOR_8_0 (0x0F << 3) + +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned ecc:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned content_prot_app:1; + unsigned reserved_1:4; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned default_ecc:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:5; + unsigned erase_grp_mult:5; + unsigned erase_grp_size:5; + unsigned c_size_mult:3; + unsigned vdd_w_curr_max:3; + unsigned vdd_w_curr_min:3; + unsigned vdd_r_curr_max:3; + unsigned vdd_r_curr_min:3; + unsigned c_size_lsb:2; + unsigned c_size_msb:10; + unsigned reserved_2:2; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_3:2; + unsigned spec_vers:4; + unsigned csd_structure:2; +} mmc_csd_reg_t; + +/* csd for sd2.0 */ +typedef struct { + unsigned not_used:1; + unsigned crc:7; + unsigned reserved_1:2; + unsigned file_format:2; + unsigned tmp_write_protect:1; + unsigned perm_write_protect:1; + unsigned copy:1; + unsigned file_format_grp:1; + unsigned reserved_2:5; + unsigned write_bl_partial:1; + unsigned write_bl_len:4; + unsigned r2w_factor:3; + unsigned reserved_3:2; + unsigned wp_grp_enable:1; + unsigned wp_grp_size:7; + unsigned sector_size:7; + unsigned erase_blk_len:1; + unsigned reserved_4:1; + unsigned c_size_lsb:16; + unsigned c_size_msb:6; + unsigned reserved_5:6; + unsigned dsr_imp:1; + unsigned read_blk_misalign:1; + unsigned write_blk_misalign:1; + unsigned read_bl_partial:1; + unsigned read_bl_len:4; + unsigned ccc:12; + unsigned tran_speed:8; + unsigned nsac:8; + unsigned taac:8; + unsigned reserved_6:6; + unsigned csd_structure:2; +} mmc_sd2_csd_reg_t; + +/* extended csd - 512 bytes long */ +typedef struct { + unsigned char reserved_1[181]; + unsigned char erasedmemorycontent; + unsigned char reserved_2; + unsigned char buswidthmode; + unsigned char reserved_3; + unsigned char highspeedinterfacetiming; + unsigned char reserved_4; + unsigned char powerclass; + unsigned char reserved_5; + unsigned char commandsetrevision; + unsigned char reserved_6; + unsigned char commandset; + unsigned char extendedcsdrevision; + unsigned char reserved_7; + unsigned char csdstructureversion; + unsigned char reserved_8; + unsigned char cardtype; + unsigned char reserved_9[3]; + unsigned char powerclass_52mhz_1_95v; + unsigned char powerclass_26mhz_1_95v; + unsigned char powerclass_52mhz_3_6v; + unsigned char powerclass_26mhz_3_6v; + unsigned char reserved_10; + unsigned char minreadperf_4b_26mhz; + unsigned char minwriteperf_4b_26mhz; + unsigned char minreadperf_8b_26mhz_4b_52mhz; + unsigned char minwriteperf_8b_26mhz_4b_52mhz; + unsigned char minreadperf_8b_52mhz; + unsigned char minwriteperf_8b_52mhz; + unsigned char reserved_11; + unsigned int sectorcount; + unsigned char reserved_12[288]; + unsigned char supportedcommandsets; + unsigned char reserved_13[7]; +} mmc_extended_csd_reg_t; + +/* mmc sd responce */ +typedef struct { + unsigned int ocr; +} mmc_resp_r3; + +typedef struct { + unsigned short cardstatus; + unsigned short newpublishedrca; +} mmc_resp_r6; + +extern mmc_card_data mmc_dev; + +unsigned char mmc_lowlevel_init(void); +unsigned char mmc_send_command(unsigned int cmd, unsigned int arg, + unsigned int *response); +unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd); +unsigned char mmc_set_opendrain(unsigned char state); +unsigned char mmc_read_data(unsigned int *output_buf); + +#endif /* MMC_H */ diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/include/asm-arm/arch-omap3/mmc_host_def.h new file mode 100644 index 000000000..aa751c9a3 --- /dev/null +++ b/include/asm-arm/arch-omap3/mmc_host_def.h @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation's version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef MMC_HOST_DEF_H +#define MMC_HOST_DEF_H + +/* T2 Register definitions */ +#define T2_BASE 0x48002000 + +typedef struct t2 { + unsigned char res1[0x274]; + unsigned int devconf0; /* 0x274 */ + unsigned char res2[0x2A8]; + unsigned int pbias_lite; /* 0x520 */ +} t2_t; + +#define MMCSDIO1ADPCLKISEL (1 << 24) + +#define PBIASLITEPWRDNZ0 (1 << 1) +#define PBIASSPEEDCTRL0 (1 << 2) +#define PBIASLITEPWRDNZ1 (1 << 9) + +/* + * OMAP HSMMC register definitions + */ +#define OMAP_HSMMC_BASE 0x4809C000 + +typedef struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +} hsmmc_t; + +/* + * OMAP HS MMC Bit definitions + */ +#define MMC_SOFTRESET (0x1 << 1) +#define RESETDONE (0x1 << 0) +#define NOOPENDRAIN (0x0 << 0) +#define OPENDRAIN (0x1 << 0) +#define OD (0x1 << 0) +#define INIT_NOINIT (0x0 << 1) +#define INIT_INITSTREAM (0x1 << 1) +#define HR_NOHOSTRESP (0x0 << 2) +#define STR_BLOCK (0x0 << 3) +#define MODE_FUNC (0x0 << 4) +#define DW8_1_4BITMODE (0x0 << 5) +#define MIT_CTO (0x0 << 6) +#define CDP_ACTIVEHIGH (0x0 << 7) +#define WPP_ACTIVEHIGH (0x0 << 8) +#define RESERVED_MASK (0x3 << 9) +#define CTPL_MMC_SD (0x0 << 11) +#define BLEN_512BYTESLEN (0x200 << 0) +#define NBLK_STPCNT (0x0 << 16) +#define DE_DISABLE (0x0 << 0) +#define BCE_DISABLE (0x0 << 1) +#define ACEN_DISABLE (0x0 << 2) +#define DDIR_OFFSET (4) +#define DDIR_MASK (0x1 << 4) +#define DDIR_WRITE (0x0 << 4) +#define DDIR_READ (0x1 << 4) +#define MSBS_SGLEBLK (0x0 << 5) +#define RSP_TYPE_OFFSET (16) +#define RSP_TYPE_MASK (0x3 << 16) +#define RSP_TYPE_NORSP (0x0 << 16) +#define RSP_TYPE_LGHT136 (0x1 << 16) +#define RSP_TYPE_LGHT48 (0x2 << 16) +#define RSP_TYPE_LGHT48B (0x3 << 16) +#define CCCE_NOCHECK (0x0 << 19) +#define CCCE_CHECK (0x1 << 19) +#define CICE_NOCHECK (0x0 << 20) +#define CICE_CHECK (0x1 << 20) +#define DP_OFFSET (21) +#define DP_MASK (0x1 << 21) +#define DP_NO_DATA (0x0 << 21) +#define DP_DATA (0x1 << 21) +#define CMD_TYPE_NORMAL (0x0 << 22) +#define INDEX_OFFSET (24) +#define INDEX_MASK (0x3f << 24) +#define INDEX(i) (i << 24) +#define DATI_MASK (0x1 << 1) +#define DATI_CMDDIS (0x1 << 1) +#define DTW_1_BITMODE (0x0 << 1) +#define DTW_4_BITMODE (0x1 << 1) +#define SDBP_PWROFF (0x0 << 8) +#define SDBP_PWRON (0x1 << 8) +#define SDVS_1V8 (0x5 << 9) +#define SDVS_3V0 (0x6 << 9) +#define ICE_MASK (0x1 << 0) +#define ICE_STOP (0x0 << 0) +#define ICS_MASK (0x1 << 1) +#define ICS_NOTREADY (0x0 << 1) +#define ICE_OSCILLATE (0x1 << 0) +#define CEN_MASK (0x1 << 2) +#define CEN_DISABLE (0x0 << 2) +#define CEN_ENABLE (0x1 << 2) +#define CLKD_OFFSET (6) +#define CLKD_MASK (0x3FF << 6) +#define DTO_MASK (0xF << 16) +#define DTO_15THDTO (0xE << 16) +#define SOFTRESETALL (0x1 << 24) +#define CC_MASK (0x1 << 0) +#define TC_MASK (0x1 << 1) +#define BWR_MASK (0x1 << 4) +#define BRR_MASK (0x1 << 5) +#define ERRI_MASK (0x1 << 15) +#define IE_CC (0x01 << 0) +#define IE_TC (0x01 << 1) +#define IE_BWR (0x01 << 4) +#define IE_BRR (0x01 << 5) +#define IE_CTO (0x01 << 16) +#define IE_CCRC (0x01 << 17) +#define IE_CEB (0x01 << 18) +#define IE_CIE (0x01 << 19) +#define IE_DTO (0x01 << 20) +#define IE_DCRC (0x01 << 21) +#define IE_DEB (0x01 << 22) +#define IE_CERR (0x01 << 28) +#define IE_BADA (0x01 << 29) + +#define VS30_3V0SUP (1 << 25) +#define VS18_1V8SUP (1 << 26) + +/* Driver definitions */ +#define MMCSD_SECTOR_SIZE 512 +#define MMC_CARD 0 +#define SD_CARD 1 +#define BYTE_MODE 0 +#define SECTOR_MODE 1 +#define CLK_INITSEQ 0 +#define CLK_400KHZ 1 +#define CLK_MISC 2 + +typedef struct { + unsigned int card_type; + unsigned int version; + unsigned int mode; + unsigned int size; + unsigned int RCA; +} mmc_card_data; + +#define mmc_reg_out(addr, mask, val)\ + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) + +#endif /* MMC_HOST_DEF_H */ diff --git a/include/asm-arm/arch-omap3/mux.h b/include/asm-arm/arch-omap3/mux.h new file mode 100644 index 000000000..0c01c7316 --- /dev/null +++ b/include/asm-arm/arch-omap3/mux.h @@ -0,0 +1,412 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MUX_H_ +#define _MUX_H_ + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + */ + +#define IEN (1 << 8) + +#define IDIS (0 << 8) +#define PTU (1 << 4) +#define PTD (0 << 4) +#define EN (1 << 3) +#define DIS (0 << 3) + +#define M0 0 +#define M1 1 +#define M2 2 +#define M3 3 +#define M4 4 +#define M5 5 +#define M6 6 +#define M7 7 + +/* + * To get the actual address the offset has to added + * with OMAP34XX_CTRL_BASE to get the actual address + */ + +/*SDRC*/ +#define CONTROL_PADCONF_SDRC_D0 0x0030 +#define CONTROL_PADCONF_SDRC_D1 0x0032 +#define CONTROL_PADCONF_SDRC_D2 0x0034 +#define CONTROL_PADCONF_SDRC_D3 0x0036 +#define CONTROL_PADCONF_SDRC_D4 0x0038 +#define CONTROL_PADCONF_SDRC_D5 0x003A +#define CONTROL_PADCONF_SDRC_D6 0x003C +#define CONTROL_PADCONF_SDRC_D7 0x003E +#define CONTROL_PADCONF_SDRC_D8 0x0040 +#define CONTROL_PADCONF_SDRC_D9 0x0042 +#define CONTROL_PADCONF_SDRC_D10 0x0044 +#define CONTROL_PADCONF_SDRC_D11 0x0046 +#define CONTROL_PADCONF_SDRC_D12 0x0048 +#define CONTROL_PADCONF_SDRC_D13 0x004A +#define CONTROL_PADCONF_SDRC_D14 0x004C +#define CONTROL_PADCONF_SDRC_D15 0x004E +#define CONTROL_PADCONF_SDRC_D16 0x0050 +#define CONTROL_PADCONF_SDRC_D17 0x0052 +#define CONTROL_PADCONF_SDRC_D18 0x0054 +#define CONTROL_PADCONF_SDRC_D19 0x0056 +#define CONTROL_PADCONF_SDRC_D20 0x0058 +#define CONTROL_PADCONF_SDRC_D21 0x005A +#define CONTROL_PADCONF_SDRC_D22 0x005C +#define CONTROL_PADCONF_SDRC_D23 0x005E +#define CONTROL_PADCONF_SDRC_D24 0x0060 +#define CONTROL_PADCONF_SDRC_D25 0x0062 +#define CONTROL_PADCONF_SDRC_D26 0x0064 +#define CONTROL_PADCONF_SDRC_D27 0x0066 +#define CONTROL_PADCONF_SDRC_D28 0x0068 +#define CONTROL_PADCONF_SDRC_D29 0x006A +#define CONTROL_PADCONF_SDRC_D30 0x006C +#define CONTROL_PADCONF_SDRC_D31 0x006E +#define CONTROL_PADCONF_SDRC_CLK 0x0070 +#define CONTROL_PADCONF_SDRC_DQS0 0x0072 +#define CONTROL_PADCONF_SDRC_DQS1 0x0074 +#define CONTROL_PADCONF_SDRC_DQS2 0x0076 +#define CONTROL_PADCONF_SDRC_DQS3 0x0078 +/*GPMC*/ +#define CONTROL_PADCONF_GPMC_A1 0x007A +#define CONTROL_PADCONF_GPMC_A2 0x007C +#define CONTROL_PADCONF_GPMC_A3 0x007E +#define CONTROL_PADCONF_GPMC_A4 0x0080 +#define CONTROL_PADCONF_GPMC_A5 0x0082 +#define CONTROL_PADCONF_GPMC_A6 0x0084 +#define CONTROL_PADCONF_GPMC_A7 0x0086 +#define CONTROL_PADCONF_GPMC_A8 0x0088 +#define CONTROL_PADCONF_GPMC_A9 0x008A +#define CONTROL_PADCONF_GPMC_A10 0x008C +#define CONTROL_PADCONF_GPMC_D0 0x008E +#define CONTROL_PADCONF_GPMC_D1 0x0090 +#define CONTROL_PADCONF_GPMC_D2 0x0092 +#define CONTROL_PADCONF_GPMC_D3 0x0094 +#define CONTROL_PADCONF_GPMC_D4 0x0096 +#define CONTROL_PADCONF_GPMC_D5 0x0098 +#define CONTROL_PADCONF_GPMC_D6 0x009A +#define CONTROL_PADCONF_GPMC_D7 0x009C +#define CONTROL_PADCONF_GPMC_D8 0x009E +#define CONTROL_PADCONF_GPMC_D9 0x00A0 +#define CONTROL_PADCONF_GPMC_D10 0x00A2 +#define CONTROL_PADCONF_GPMC_D11 0x00A4 +#define CONTROL_PADCONF_GPMC_D12 0x00A6 +#define CONTROL_PADCONF_GPMC_D13 0x00A8 +#define CONTROL_PADCONF_GPMC_D14 0x00AA +#define CONTROL_PADCONF_GPMC_D15 0x00AC +#define CONTROL_PADCONF_GPMC_NCS0 0x00AE +#define CONTROL_PADCONF_GPMC_NCS1 0x00B0 +#define CONTROL_PADCONF_GPMC_NCS2 0x00B2 +#define CONTROL_PADCONF_GPMC_NCS3 0x00B4 +#define CONTROL_PADCONF_GPMC_NCS4 0x00B6 +#define CONTROL_PADCONF_GPMC_NCS5 0x00B8 +#define CONTROL_PADCONF_GPMC_NCS6 0x00BA +#define CONTROL_PADCONF_GPMC_NCS7 0x00BC +#define CONTROL_PADCONF_GPMC_CLK 0x00BE +#define CONTROL_PADCONF_GPMC_NADV_ALE 0x00C0 +#define CONTROL_PADCONF_GPMC_NOE 0x00C2 +#define CONTROL_PADCONF_GPMC_NWE 0x00C4 +#define CONTROL_PADCONF_GPMC_NBE0_CLE 0x00C6 +#define CONTROL_PADCONF_GPMC_NBE1 0x00C8 +#define CONTROL_PADCONF_GPMC_NWP 0x00CA +#define CONTROL_PADCONF_GPMC_WAIT0 0x00CC +#define CONTROL_PADCONF_GPMC_WAIT1 0x00CE +#define CONTROL_PADCONF_GPMC_WAIT2 0x00D0 +#define CONTROL_PADCONF_GPMC_WAIT3 0x00D2 +/*DSS*/ +#define CONTROL_PADCONF_DSS_PCLK 0x00D4 +#define CONTROL_PADCONF_DSS_HSYNC 0x00D6 +#define CONTROL_PADCONF_DSS_VSYNC 0x00D8 +#define CONTROL_PADCONF_DSS_ACBIAS 0x00DA +#define CONTROL_PADCONF_DSS_DATA0 0x00DC +#define CONTROL_PADCONF_DSS_DATA1 0x00DE +#define CONTROL_PADCONF_DSS_DATA2 0x00E0 +#define CONTROL_PADCONF_DSS_DATA3 0x00E2 +#define CONTROL_PADCONF_DSS_DATA4 0x00E4 +#define CONTROL_PADCONF_DSS_DATA5 0x00E6 +#define CONTROL_PADCONF_DSS_DATA6 0x00E8 +#define CONTROL_PADCONF_DSS_DATA7 0x00EA +#define CONTROL_PADCONF_DSS_DATA8 0x00EC +#define CONTROL_PADCONF_DSS_DATA9 0x00EE +#define CONTROL_PADCONF_DSS_DATA10 0x00F0 +#define CONTROL_PADCONF_DSS_DATA11 0x00F2 +#define CONTROL_PADCONF_DSS_DATA12 0x00F4 +#define CONTROL_PADCONF_DSS_DATA13 0x00F6 +#define CONTROL_PADCONF_DSS_DATA14 0x00F8 +#define CONTROL_PADCONF_DSS_DATA15 0x00FA +#define CONTROL_PADCONF_DSS_DATA16 0x00FC +#define CONTROL_PADCONF_DSS_DATA17 0x00FE +#define CONTROL_PADCONF_DSS_DATA18 0x0100 +#define CONTROL_PADCONF_DSS_DATA19 0x0102 +#define CONTROL_PADCONF_DSS_DATA20 0x0104 +#define CONTROL_PADCONF_DSS_DATA21 0x0106 +#define CONTROL_PADCONF_DSS_DATA22 0x0108 +#define CONTROL_PADCONF_DSS_DATA23 0x010A +/*CAMERA*/ +#define CONTROL_PADCONF_CAM_HS 0x010C +#define CONTROL_PADCONF_CAM_VS 0x010E +#define CONTROL_PADCONF_CAM_XCLKA 0x0110 +#define CONTROL_PADCONF_CAM_PCLK 0x0112 +#define CONTROL_PADCONF_CAM_FLD 0x0114 +#define CONTROL_PADCONF_CAM_D0 0x0116 +#define CONTROL_PADCONF_CAM_D1 0x0118 +#define CONTROL_PADCONF_CAM_D2 0x011A +#define CONTROL_PADCONF_CAM_D3 0x011C +#define CONTROL_PADCONF_CAM_D4 0x011E +#define CONTROL_PADCONF_CAM_D5 0x0120 +#define CONTROL_PADCONF_CAM_D6 0x0122 +#define CONTROL_PADCONF_CAM_D7 0x0124 +#define CONTROL_PADCONF_CAM_D8 0x0126 +#define CONTROL_PADCONF_CAM_D9 0x0128 +#define CONTROL_PADCONF_CAM_D10 0x012A +#define CONTROL_PADCONF_CAM_D11 0x012C +#define CONTROL_PADCONF_CAM_XCLKB 0x012E +#define CONTROL_PADCONF_CAM_WEN 0x0130 +#define CONTROL_PADCONF_CAM_STROBE 0x0132 +#define CONTROL_PADCONF_CSI2_DX0 0x0134 +#define CONTROL_PADCONF_CSI2_DY0 0x0136 +#define CONTROL_PADCONF_CSI2_DX1 0x0138 +#define CONTROL_PADCONF_CSI2_DY1 0x013A +/*Audio Interface */ +#define CONTROL_PADCONF_MCBSP2_FSX 0x013C +#define CONTROL_PADCONF_MCBSP2_CLKX 0x013E +#define CONTROL_PADCONF_MCBSP2_DR 0x0140 +#define CONTROL_PADCONF_MCBSP2_DX 0x0142 +#define CONTROL_PADCONF_MMC1_CLK 0x0144 +#define CONTROL_PADCONF_MMC1_CMD 0x0146 +#define CONTROL_PADCONF_MMC1_DAT0 0x0148 +#define CONTROL_PADCONF_MMC1_DAT1 0x014A +#define CONTROL_PADCONF_MMC1_DAT2 0x014C +#define CONTROL_PADCONF_MMC1_DAT3 0x014E +#define CONTROL_PADCONF_MMC1_DAT4 0x0150 +#define CONTROL_PADCONF_MMC1_DAT5 0x0152 +#define CONTROL_PADCONF_MMC1_DAT6 0x0154 +#define CONTROL_PADCONF_MMC1_DAT7 0x0156 +/*Wireless LAN */ +#define CONTROL_PADCONF_MMC2_CLK 0x0158 +#define CONTROL_PADCONF_MMC2_CMD 0x015A +#define CONTROL_PADCONF_MMC2_DAT0 0x015C +#define CONTROL_PADCONF_MMC2_DAT1 0x015E +#define CONTROL_PADCONF_MMC2_DAT2 0x0160 +#define CONTROL_PADCONF_MMC2_DAT3 0x0162 +#define CONTROL_PADCONF_MMC2_DAT4 0x0164 +#define CONTROL_PADCONF_MMC2_DAT5 0x0166 +#define CONTROL_PADCONF_MMC2_DAT6 0x0168 +#define CONTROL_PADCONF_MMC2_DAT7 0x016A +/*Bluetooth*/ +#define CONTROL_PADCONF_MCBSP3_DX 0x016C +#define CONTROL_PADCONF_MCBSP3_DR 0x016E +#define CONTROL_PADCONF_MCBSP3_CLKX 0x0170 +#define CONTROL_PADCONF_MCBSP3_FSX 0x0172 +#define CONTROL_PADCONF_UART2_CTS 0x0174 +#define CONTROL_PADCONF_UART2_RTS 0x0176 +#define CONTROL_PADCONF_UART2_TX 0x0178 +#define CONTROL_PADCONF_UART2_RX 0x017A +/*Modem Interface */ +#define CONTROL_PADCONF_UART1_TX 0x017C +#define CONTROL_PADCONF_UART1_RTS 0x017E +#define CONTROL_PADCONF_UART1_CTS 0x0180 +#define CONTROL_PADCONF_UART1_RX 0x0182 +#define CONTROL_PADCONF_MCBSP4_CLKX 0x0184 +#define CONTROL_PADCONF_MCBSP4_DR 0x0186 +#define CONTROL_PADCONF_MCBSP4_DX 0x0188 +#define CONTROL_PADCONF_MCBSP4_FSX 0x018A +#define CONTROL_PADCONF_MCBSP1_CLKR 0x018C +#define CONTROL_PADCONF_MCBSP1_FSR 0x018E +#define CONTROL_PADCONF_MCBSP1_DX 0x0190 +#define CONTROL_PADCONF_MCBSP1_DR 0x0192 +#define CONTROL_PADCONF_MCBSP_CLKS 0x0194 +#define CONTROL_PADCONF_MCBSP1_FSX 0x0196 +#define CONTROL_PADCONF_MCBSP1_CLKX 0x0198 +/*Serial Interface*/ +#define CONTROL_PADCONF_UART3_CTS_RCTX 0x019A +#define CONTROL_PADCONF_UART3_RTS_SD 0x019C +#define CONTROL_PADCONF_UART3_RX_IRRX 0x019E +#define CONTROL_PADCONF_UART3_TX_IRTX 0x01A0 +#define CONTROL_PADCONF_HSUSB0_CLK 0x01A2 +#define CONTROL_PADCONF_HSUSB0_STP 0x01A4 +#define CONTROL_PADCONF_HSUSB0_DIR 0x01A6 +#define CONTROL_PADCONF_HSUSB0_NXT 0x01A8 +#define CONTROL_PADCONF_HSUSB0_DATA0 0x01AA +#define CONTROL_PADCONF_HSUSB0_DATA1 0x01AC +#define CONTROL_PADCONF_HSUSB0_DATA2 0x01AE +#define CONTROL_PADCONF_HSUSB0_DATA3 0x01B0 +#define CONTROL_PADCONF_HSUSB0_DATA4 0x01B2 +#define CONTROL_PADCONF_HSUSB0_DATA5 0x01B4 +#define CONTROL_PADCONF_HSUSB0_DATA6 0x01B6 +#define CONTROL_PADCONF_HSUSB0_DATA7 0x01B8 +#define CONTROL_PADCONF_I2C1_SCL 0x01BA +#define CONTROL_PADCONF_I2C1_SDA 0x01BC +#define CONTROL_PADCONF_I2C2_SCL 0x01BE +#define CONTROL_PADCONF_I2C2_SDA 0x01C0 +#define CONTROL_PADCONF_I2C3_SCL 0x01C2 +#define CONTROL_PADCONF_I2C3_SDA 0x01C4 +#define CONTROL_PADCONF_I2C4_SCL 0x0A00 +#define CONTROL_PADCONF_I2C4_SDA 0x0A02 +#define CONTROL_PADCONF_HDQ_SIO 0x01C6 +#define CONTROL_PADCONF_MCSPI1_CLK 0x01C8 +#define CONTROL_PADCONF_MCSPI1_SIMO 0x01CA +#define CONTROL_PADCONF_MCSPI1_SOMI 0x01CC +#define CONTROL_PADCONF_MCSPI1_CS0 0x01CE +#define CONTROL_PADCONF_MCSPI1_CS1 0x01D0 +#define CONTROL_PADCONF_MCSPI1_CS2 0x01D2 +#define CONTROL_PADCONF_MCSPI1_CS3 0x01D4 +#define CONTROL_PADCONF_MCSPI2_CLK 0x01D6 +#define CONTROL_PADCONF_MCSPI2_SIMO 0x01D8 +#define CONTROL_PADCONF_MCSPI2_SOMI 0x01DA +#define CONTROL_PADCONF_MCSPI2_CS0 0x01DC +#define CONTROL_PADCONF_MCSPI2_CS1 0x01DE +/*Control and debug */ +#define CONTROL_PADCONF_SYS_32K 0x0A04 +#define CONTROL_PADCONF_SYS_CLKREQ 0x0A06 +#define CONTROL_PADCONF_SYS_NIRQ 0x01E0 +#define CONTROL_PADCONF_SYS_BOOT0 0x0A0A +#define CONTROL_PADCONF_SYS_BOOT1 0x0A0C +#define CONTROL_PADCONF_SYS_BOOT2 0x0A0E +#define CONTROL_PADCONF_SYS_BOOT3 0x0A10 +#define CONTROL_PADCONF_SYS_BOOT4 0x0A12 +#define CONTROL_PADCONF_SYS_BOOT5 0x0A14 +#define CONTROL_PADCONF_SYS_BOOT6 0x0A16 +#define CONTROL_PADCONF_SYS_OFF_MODE 0x0A18 +#define CONTROL_PADCONF_SYS_CLKOUT1 0x0A1A +#define CONTROL_PADCONF_SYS_CLKOUT2 0x01E2 +#define CONTROL_PADCONF_JTAG_nTRST 0x0A1C +#define CONTROL_PADCONF_JTAG_TCK 0x0A1E +#define CONTROL_PADCONF_JTAG_TMS 0x0A20 +#define CONTROL_PADCONF_JTAG_TDI 0x0A22 +#define CONTROL_PADCONF_JTAG_EMU0 0x0A24 +#define CONTROL_PADCONF_JTAG_EMU1 0x0A26 +#define CONTROL_PADCONF_ETK_CLK 0x0A28 +#define CONTROL_PADCONF_ETK_CTL 0x0A2A +#define CONTROL_PADCONF_ETK_D0 0x0A2C +#define CONTROL_PADCONF_ETK_D1 0x0A2E +#define CONTROL_PADCONF_ETK_D2 0x0A30 +#define CONTROL_PADCONF_ETK_D3 0x0A32 +#define CONTROL_PADCONF_ETK_D4 0x0A34 +#define CONTROL_PADCONF_ETK_D5 0x0A36 +#define CONTROL_PADCONF_ETK_D6 0x0A38 +#define CONTROL_PADCONF_ETK_D7 0x0A3A +#define CONTROL_PADCONF_ETK_D8 0x0A3C +#define CONTROL_PADCONF_ETK_D9 0x0A3E +#define CONTROL_PADCONF_ETK_D10 0x0A40 +#define CONTROL_PADCONF_ETK_D11 0x0A42 +#define CONTROL_PADCONF_ETK_D12 0x0A44 +#define CONTROL_PADCONF_ETK_D13 0x0A46 +#define CONTROL_PADCONF_ETK_D14 0x0A48 +#define CONTROL_PADCONF_ETK_D15 0x0A4A +#define CONTROL_PADCONF_ETK_CLK_ES2 0x05D8 +#define CONTROL_PADCONF_ETK_CTL_ES2 0x05DA +#define CONTROL_PADCONF_ETK_D0_ES2 0x05DC +#define CONTROL_PADCONF_ETK_D1_ES2 0x05DE +#define CONTROL_PADCONF_ETK_D2_ES2 0x05E0 +#define CONTROL_PADCONF_ETK_D3_ES2 0x05E2 +#define CONTROL_PADCONF_ETK_D4_ES2 0x05E4 +#define CONTROL_PADCONF_ETK_D5_ES2 0x05E6 +#define CONTROL_PADCONF_ETK_D6_ES2 0x05E8 +#define CONTROL_PADCONF_ETK_D7_ES2 0x05EA +#define CONTROL_PADCONF_ETK_D8_ES2 0x05EC +#define CONTROL_PADCONF_ETK_D9_ES2 0x05EE +#define CONTROL_PADCONF_ETK_D10_ES2 0x05F0 +#define CONTROL_PADCONF_ETK_D11_ES2 0x05F2 +#define CONTROL_PADCONF_ETK_D12_ES2 0x05F4 +#define CONTROL_PADCONF_ETK_D13_ES2 0x05F6 +#define CONTROL_PADCONF_ETK_D14_ES2 0x05F8 +#define CONTROL_PADCONF_ETK_D15_ES2 0x05FA +/*Die to Die */ +#define CONTROL_PADCONF_D2D_MCAD0 0x01E4 +#define CONTROL_PADCONF_D2D_MCAD1 0x01E6 +#define CONTROL_PADCONF_D2D_MCAD2 0x01E8 +#define CONTROL_PADCONF_D2D_MCAD3 0x01EA +#define CONTROL_PADCONF_D2D_MCAD4 0x01EC +#define CONTROL_PADCONF_D2D_MCAD5 0x01EE +#define CONTROL_PADCONF_D2D_MCAD6 0x01F0 +#define CONTROL_PADCONF_D2D_MCAD7 0x01F2 +#define CONTROL_PADCONF_D2D_MCAD8 0x01F4 +#define CONTROL_PADCONF_D2D_MCAD9 0x01F6 +#define CONTROL_PADCONF_D2D_MCAD10 0x01F8 +#define CONTROL_PADCONF_D2D_MCAD11 0x01FA +#define CONTROL_PADCONF_D2D_MCAD12 0x01FC +#define CONTROL_PADCONF_D2D_MCAD13 0x01FE +#define CONTROL_PADCONF_D2D_MCAD14 0x0200 +#define CONTROL_PADCONF_D2D_MCAD15 0x0202 +#define CONTROL_PADCONF_D2D_MCAD16 0x0204 +#define CONTROL_PADCONF_D2D_MCAD17 0x0206 +#define CONTROL_PADCONF_D2D_MCAD18 0x0208 +#define CONTROL_PADCONF_D2D_MCAD19 0x020A +#define CONTROL_PADCONF_D2D_MCAD20 0x020C +#define CONTROL_PADCONF_D2D_MCAD21 0x020E +#define CONTROL_PADCONF_D2D_MCAD22 0x0210 +#define CONTROL_PADCONF_D2D_MCAD23 0x0212 +#define CONTROL_PADCONF_D2D_MCAD24 0x0214 +#define CONTROL_PADCONF_D2D_MCAD25 0x0216 +#define CONTROL_PADCONF_D2D_MCAD26 0x0218 +#define CONTROL_PADCONF_D2D_MCAD27 0x021A +#define CONTROL_PADCONF_D2D_MCAD28 0x021C +#define CONTROL_PADCONF_D2D_MCAD29 0x021E +#define CONTROL_PADCONF_D2D_MCAD30 0x0220 +#define CONTROL_PADCONF_D2D_MCAD31 0x0222 +#define CONTROL_PADCONF_D2D_MCAD32 0x0224 +#define CONTROL_PADCONF_D2D_MCAD33 0x0226 +#define CONTROL_PADCONF_D2D_MCAD34 0x0228 +#define CONTROL_PADCONF_D2D_MCAD35 0x022A +#define CONTROL_PADCONF_D2D_MCAD36 0x022C +#define CONTROL_PADCONF_D2D_CLK26MI 0x022E +#define CONTROL_PADCONF_D2D_NRESPWRON 0x0230 +#define CONTROL_PADCONF_D2D_NRESWARM 0x0232 +#define CONTROL_PADCONF_D2D_ARM9NIRQ 0x0234 +#define CONTROL_PADCONF_D2D_UMA2P6FIQ 0x0236 +#define CONTROL_PADCONF_D2D_SPINT 0x0238 +#define CONTROL_PADCONF_D2D_FRINT 0x023A +#define CONTROL_PADCONF_D2D_DMAREQ0 0x023C +#define CONTROL_PADCONF_D2D_DMAREQ1 0x023E +#define CONTROL_PADCONF_D2D_DMAREQ2 0x0240 +#define CONTROL_PADCONF_D2D_DMAREQ3 0x0242 +#define CONTROL_PADCONF_D2D_N3GTRST 0x0244 +#define CONTROL_PADCONF_D2D_N3GTDI 0x0246 +#define CONTROL_PADCONF_D2D_N3GTDO 0x0248 +#define CONTROL_PADCONF_D2D_N3GTMS 0x024A +#define CONTROL_PADCONF_D2D_N3GTCK 0x024C +#define CONTROL_PADCONF_D2D_N3GRTCK 0x024E +#define CONTROL_PADCONF_D2D_MSTDBY 0x0250 +#define CONTROL_PADCONF_D2D_SWAKEUP 0x0A4C +#define CONTROL_PADCONF_D2D_IDLEREQ 0x0252 +#define CONTROL_PADCONF_D2D_IDLEACK 0x0254 +#define CONTROL_PADCONF_D2D_MWRITE 0x0256 +#define CONTROL_PADCONF_D2D_SWRITE 0x0258 +#define CONTROL_PADCONF_D2D_MREAD 0x025A +#define CONTROL_PADCONF_D2D_SREAD 0x025C +#define CONTROL_PADCONF_D2D_MBUSFLAG 0x025E +#define CONTROL_PADCONF_D2D_SBUSFLAG 0x0260 +#define CONTROL_PADCONF_SDRC_CKE0 0x0262 +#define CONTROL_PADCONF_SDRC_CKE1 0x0264 + +#define MUX_VAL(OFFSET,VALUE)\ + writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET)); + +#define CP(x) (CONTROL_PADCONF_##x) + +#endif diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h new file mode 100644 index 000000000..02e36d7e3 --- /dev/null +++ b/include/asm-arm/arch-omap3/omap3.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _OMAP3_H_ +#define _OMAP3_H_ + +/* Stuff on L3 Interconnect */ +#define SMX_APE_BASE 0x68000000 + +/* GPMC */ +#define OMAP34XX_GPMC_BASE 0x6E000000 + +/* SMS */ +#define OMAP34XX_SMS_BASE 0x6C000000 + +/* SDRC */ +#define OMAP34XX_SDRC_BASE 0x6D000000 + +/* + * L4 Peripherals - L4 Wakeup and L4 Core now + */ +#define OMAP34XX_CORE_L4_IO_BASE 0x48000000 +#define OMAP34XX_WAKEUP_L4_IO_BASE 0x48300000 +#define OMAP34XX_L4_PER 0x49000000 +#define OMAP34XX_L4_IO_BASE OMAP34XX_CORE_L4_IO_BASE + +/* CONTROL */ +#define OMAP34XX_CTRL_BASE (OMAP34XX_L4_IO_BASE + 0x2000) + +/* UART */ +#define OMAP34XX_UART1 (OMAP34XX_L4_IO_BASE + 0x6a000) +#define OMAP34XX_UART2 (OMAP34XX_L4_IO_BASE + 0x6c000) +#define OMAP34XX_UART3 (OMAP34XX_L4_PER + 0x20000) + +/* General Purpose Timers */ +#define OMAP34XX_GPT1 0x48318000 +#define OMAP34XX_GPT2 0x49032000 +#define OMAP34XX_GPT3 0x49034000 +#define OMAP34XX_GPT4 0x49036000 +#define OMAP34XX_GPT5 0x49038000 +#define OMAP34XX_GPT6 0x4903A000 +#define OMAP34XX_GPT7 0x4903C000 +#define OMAP34XX_GPT8 0x4903E000 +#define OMAP34XX_GPT9 0x49040000 +#define OMAP34XX_GPT10 0x48086000 +#define OMAP34XX_GPT11 0x48088000 +#define OMAP34XX_GPT12 0x48304000 + +/* WatchDog Timers (1 secure, 3 GP) */ +#define WD1_BASE 0x4830C000 +#define WD2_BASE 0x48314000 +#define WD3_BASE 0x49030000 + +/* 32KTIMER */ +#define SYNC_32KTIMER_BASE 0x48320000 + +#ifndef __ASSEMBLY__ + +typedef struct s32ktimer { + unsigned char res[0x10]; + unsigned int s32k_cr; /* 0x10 */ +} s32ktimer_t; + +#endif /* __ASSEMBLY__ */ + +/* OMAP3 GPIO registers */ +#define OMAP34XX_GPIO1_BASE 0x48310000 +#define OMAP34XX_GPIO2_BASE 0x49050000 +#define OMAP34XX_GPIO3_BASE 0x49052000 +#define OMAP34XX_GPIO4_BASE 0x49054000 +#define OMAP34XX_GPIO5_BASE 0x49056000 +#define OMAP34XX_GPIO6_BASE 0x49058000 + +#ifndef __ASSEMBLY__ +typedef struct gpio { + unsigned char res1[0x34]; + unsigned int oe; /* 0x34 */ + unsigned int datain; /* 0x38 */ + unsigned char res2[0x54]; + unsigned int cleardataout; /* 0x90 */ + unsigned int setdataout; /* 0x94 */ +} gpio_t; +#endif /* __ASSEMBLY__ */ + +#define GPIO0 (0x1 << 0) +#define GPIO1 (0x1 << 1) +#define GPIO2 (0x1 << 2) +#define GPIO3 (0x1 << 3) +#define GPIO4 (0x1 << 4) +#define GPIO5 (0x1 << 5) +#define GPIO6 (0x1 << 6) +#define GPIO7 (0x1 << 7) +#define GPIO8 (0x1 << 8) +#define GPIO9 (0x1 << 9) +#define GPIO10 (0x1 << 10) +#define GPIO11 (0x1 << 11) +#define GPIO12 (0x1 << 12) +#define GPIO13 (0x1 << 13) +#define GPIO14 (0x1 << 14) +#define GPIO15 (0x1 << 15) +#define GPIO16 (0x1 << 16) +#define GPIO17 (0x1 << 17) +#define GPIO18 (0x1 << 18) +#define GPIO19 (0x1 << 19) +#define GPIO20 (0x1 << 20) +#define GPIO21 (0x1 << 21) +#define GPIO22 (0x1 << 22) +#define GPIO23 (0x1 << 23) +#define GPIO24 (0x1 << 24) +#define GPIO25 (0x1 << 25) +#define GPIO26 (0x1 << 26) +#define GPIO27 (0x1 << 27) +#define GPIO28 (0x1 << 28) +#define GPIO29 (0x1 << 29) +#define GPIO30 (0x1 << 30) +#define GPIO31 (0x1 << 31) + +/* base address for indirect vectors (internal boot mode) */ +#define SRAM_OFFSET0 0x40000000 +#define SRAM_OFFSET1 0x00200000 +#define SRAM_OFFSET2 0x0000F800 +#define SRAM_VECT_CODE (SRAM_OFFSET0 | SRAM_OFFSET1 | \ + SRAM_OFFSET2) + +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define DEBUG_LED1 149 /* gpio */ +#define DEBUG_LED2 150 /* gpio */ + +#define XDR_POP 5 /* package on package part */ +#define SDR_DISCRETE 4 /* 128M memory SDR module */ +#define DDR_STACKED 3 /* stacked part on 2422 */ +#define DDR_COMBO 2 /* combo part on cpu daughter card */ +#define DDR_DISCRETE 1 /* 2x16 parts on daughter card */ + +#define DDR_100 100 /* type found on most mem d-boards */ +#define DDR_111 111 /* some combo parts */ +#define DDR_133 133 /* most combo, some mem d-boards */ +#define DDR_165 165 /* future parts */ + +#define CPU_3430 0x3430 + +/* + * 343x real hardware: + * ES1 = rev 0 + * + * 343x code defines: + * ES1 = 0+1 = 1 + * ES1 = 1+1 = 1 + */ +#define CPU_3430_ES1 1 +#define CPU_3430_ES2 2 + +#define WIDTH_8BIT 0x0000 +#define WIDTH_16BIT 0x1000 /* bit pos for 16 bit in gpmc */ + +/* SDP definitions according to FPGA Rev. Is this OK?? */ +#define SDP_3430_V1 0x1 +#define SDP_3430_V2 0x2 + +/* EVM definitions */ +#define OMAP3EVM_V1 0x1 +#define OMAP3EVM_V2 0x2 + +/* I2C power management companion definitions */ +#define PWRMGT_ADDR_ID1 0x48 +#define PWRMGT_ADDR_ID2 0x49 +#define PWRMGT_ADDR_ID3 0x4A +#define PWRMGT_ADDR_ID4 0x4B + +/* I2C ID3 (slave3) register */ +#define LEDEN 0xEE + +#define LEDAON (0x1 << 0) +#define LEDBON (0x1 << 1) +#define LEDAPWM (0x1 << 4) +#define LEDBPWM (0x1 << 5) + +/* I2C ID4 (slave4) register */ +#define VAUX2_DEV_GRP 0x76 +#define VAUX2_DEDICATED 0x79 +#define VAUX3_DEV_GRP 0x7A +#define VAUX3_DEDICATED 0x7D +#define VMMC1_DEV_GRP 0x82 +#define VMMC1_DEDICATED 0x85 +#define VPLL2_DEV_GRP 0x8E +#define VPLL2_DEDICATED 0x91 +#define VDAC_DEV_GRP 0x96 +#define VDAC_DEDICATED 0x99 + +#define DEV_GRP_P1 0x20 +#define DEV_GRP_ALL 0xE0 + +#define VAUX2_VSEL_28 0x09 +#define VAUX3_VSEL_28 0x03 +#define VPLL2_VSEL_18 0x05 +#define VDAC_VSEL_18 0x03 +#define VMMC1_VSEL_30 0x02 + +#endif diff --git a/include/asm-arm/arch-omap3/omap_gpmc.h b/include/asm-arm/arch-omap3/omap_gpmc.h new file mode 100644 index 000000000..bd22bce83 --- /dev/null +++ b/include/asm-arm/arch-omap3/omap_gpmc.h @@ -0,0 +1,83 @@ +/* + * (C) Copyright 2004-2008 Texas Instruments, <www.ti.com> + * Rohit Choraria <rohitkc@ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +#define ECCSIZE512BYTE 0xFF +#define ECCSIZE1 (ECCSIZE512BYTE << 22) +#define ECCSIZE0 (ECCSIZE512BYTE << 12) +#define ECCSIZE0SEL (0x000 << 0) + +/* Generic ECC Layouts */ +/* Large Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ + 9, 10, 11, 12},\ + .oobfree = {\ + {.offset = 13,\ + .length = 51 } } \ +} +#endif + +/* Large Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 12,\ + .eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13},\ + .oobfree = {\ + {.offset = 14,\ + .length = 50 } } \ +} +#endif + +/* Small Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {1, 2, 3},\ + .oobfree = {\ + {.offset = 4,\ + .length = 12 } } \ +} +#endif + +/* Small Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT {\ + .eccbytes = 3,\ + .eccpos = {2, 3, 4},\ + .oobfree = {\ + {.offset = 5,\ + .length = 11 } } \ +} +#endif + +#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h new file mode 100644 index 000000000..ab3e1683f --- /dev/null +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2004-2008 + * Texas Instruments, <www.ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +typedef struct { + u32 board_type_v1; + u32 board_type_v2; + u32 mtype; + char *board_string; + char *nand_string; +} omap3_sysinfo; + +void prcm_init(void); +void per_clocks_enable(void); + +void memif_init(void); +void sdrc_init(void); +void do_sdrc_init(u32, u32); +void gpmc_init(void); + +void watchdog_init(void); +void set_muxconf_regs(void); + +u32 get_cpu_rev(void); +u32 get_mem_type(void); +u32 get_sysboot_value(void); +u32 is_gpmc_muxed(void); +u32 get_gpmc0_type(void); +u32 get_gpmc0_width(void); +u32 get_board_type(void); +void display_board_info(u32); +u32 get_sdr_cs_size(u32); +u32 get_sdr_cs_offset(u32); +u32 is_running_in_sdram(void); +u32 is_running_in_sram(void); +u32 is_running_in_flash(void); +u32 get_device_type(void); +void l2cache_enable(void); +void secureworld_exit(void); +void setup_auxcr(void); +void try_unlock_memory(void); +u32 get_boot_type(void); +void v7_flush_dcache_all(u32); +void sr32(void *, u32, u32, u32); +u32 wait_on_value(u32, u32, void *, u32); +void sdelay(unsigned long); +void make_cs1_contiguous(void); +void omap_nand_switch_ecc(int); +void power_init_r(void); + +#endif diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h deleted file mode 100644 index 85e144b68..000000000 --- a/include/asm-arm/arch-pxa/mmc.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * linux/drivers/mmc/mmc_pxa.h - * - * Author: Vladimir Shebordaev, Igor Oblakov - * Copyright: MontaVista Software Inc. - * - * $Id: mmc_pxa.h,v 0.3.1.6 2002/09/25 19:25:48 ted Exp ted $ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -#ifndef __MMC_PXA_P_H__ -#define __MMC_PXA_P_H__ - -/* PXA-250 MMC controller registers */ - -/* MMC_STRPCL */ -#define MMC_STRPCL_STOP_CLK (0x0001UL) -#define MMC_STRPCL_START_CLK (0x0002UL) - -/* MMC_STAT */ -#define MMC_STAT_END_CMD_RES (0x0001UL << 13) -#define MMC_STAT_PRG_DONE (0x0001UL << 12) -#define MMC_STAT_DATA_TRAN_DONE (0x0001UL << 11) -#define MMC_STAT_CLK_EN (0x0001UL << 8) -#define MMC_STAT_RECV_FIFO_FULL (0x0001UL << 7) -#define MMC_STAT_XMIT_FIFO_EMPTY (0x0001UL << 6) -#define MMC_STAT_RES_CRC_ERROR (0x0001UL << 5) -#define MMC_STAT_SPI_READ_ERROR_TOKEN (0x0001UL << 4) -#define MMC_STAT_CRC_READ_ERROR (0x0001UL << 3) -#define MMC_STAT_CRC_WRITE_ERROR (0x0001UL << 2) -#define MMC_STAT_TIME_OUT_RESPONSE (0x0001UL << 1) -#define MMC_STAT_READ_TIME_OUT (0x0001UL) - -#define MMC_STAT_ERRORS (MMC_STAT_RES_CRC_ERROR|MMC_STAT_SPI_READ_ERROR_TOKEN\ - |MMC_STAT_CRC_READ_ERROR|MMC_STAT_TIME_OUT_RESPONSE\ - |MMC_STAT_READ_TIME_OUT|MMC_STAT_CRC_WRITE_ERROR) - -/* MMC_CLKRT */ -#define MMC_CLKRT_20MHZ (0x0000UL) -#define MMC_CLKRT_10MHZ (0x0001UL) -#define MMC_CLKRT_5MHZ (0x0002UL) -#define MMC_CLKRT_2_5MHZ (0x0003UL) -#define MMC_CLKRT_1_25MHZ (0x0004UL) -#define MMC_CLKRT_0_625MHZ (0x0005UL) -#define MMC_CLKRT_0_3125MHZ (0x0006UL) - -/* MMC_SPI */ -#define MMC_SPI_DISABLE (0x00UL) -#define MMC_SPI_EN (0x01UL) -#define MMC_SPI_CS_EN (0x01UL << 2) -#define MMC_SPI_CS_ADDRESS (0x01UL << 3) -#define MMC_SPI_CRC_ON (0x01UL << 1) - -/* MMC_CMDAT */ -#define MMC_CMDAT_SD_4DAT (0x0001UL << 8) -#define MMC_CMDAT_MMC_DMA_EN (0x0001UL << 7) -#define MMC_CMDAT_INIT (0x0001UL << 6) -#define MMC_CMDAT_BUSY (0x0001UL << 5) -#define MMC_CMDAT_BCR (0x0003UL << 5) -#define MMC_CMDAT_STREAM (0x0001UL << 4) -#define MMC_CMDAT_BLOCK (0x0000UL << 4) -#define MMC_CMDAT_WRITE (0x0001UL << 3) -#define MMC_CMDAT_READ (0x0000UL << 3) -#define MMC_CMDAT_DATA_EN (0x0001UL << 2) -#define MMC_CMDAT_R0 (0) -#define MMC_CMDAT_R1 (0x0001UL) -#define MMC_CMDAT_R2 (0x0002UL) -#define MMC_CMDAT_R3 (0x0003UL) - -/* MMC_RESTO */ -#define MMC_RES_TO_MAX (0x007fUL) /* [6:0] */ - -/* MMC_RDTO */ -#define MMC_READ_TO_MAX (0x0ffffUL) /* [15:0] */ - -/* MMC_BLKLEN */ -#define MMC_BLK_LEN_MAX (0x03ffUL) /* [9:0] */ - -/* MMC_PRTBUF */ -#define MMC_PRTBUF_BUF_PART_FULL (0x01UL) -#define MMC_PRTBUF_BUF_FULL (0x00UL ) - -/* MMC_I_MASK */ -#define MMC_I_MASK_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_MASK_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_MASK_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_MASK_STOP_CMD (0x01UL << 3) -#define MMC_I_MASK_END_CMD_RES (0x01UL << 2) -#define MMC_I_MASK_PRG_DONE (0x01UL << 1) -#define MMC_I_MASK_DATA_TRAN_DONE (0x01UL) -#define MMC_I_MASK_ALL (0x07fUL) - - -/* MMC_I_REG */ -#define MMC_I_REG_TXFIFO_WR_REQ (0x01UL << 6) -#define MMC_I_REG_RXFIFO_RD_REQ (0x01UL << 5) -#define MMC_I_REG_CLK_IS_OFF (0x01UL << 4) -#define MMC_I_REG_STOP_CMD (0x01UL << 3) -#define MMC_I_REG_END_CMD_RES (0x01UL << 2) -#define MMC_I_REG_PRG_DONE (0x01UL << 1) -#define MMC_I_REG_DATA_TRAN_DONE (0x01UL) -#define MMC_I_REG_ALL (0x007fUL) - -/* MMC_CMD */ -#define MMC_CMD_INDEX_MAX (0x006fUL) /* [5:0] */ -#define CMD(x) (x) - -#define MMC_DEFAULT_RCA 1 - -#define MMC_BLOCK_SIZE 512 -#define MMC_MAX_BLOCK_SIZE 512 - -#define MMC_R1_IDLE_STATE 0x01 -#define MMC_R1_ERASE_STATE 0x02 -#define MMC_R1_ILLEGAL_CMD 0x04 -#define MMC_R1_COM_CRC_ERR 0x08 -#define MMC_R1_ERASE_SEQ_ERR 0x01 -#define MMC_R1_ADDR_ERR 0x02 -#define MMC_R1_PARAM_ERR 0x04 - -#define MMC_R1B_WP_ERASE_SKIP 0x0002 -#define MMC_R1B_ERR 0x0004 -#define MMC_R1B_CC_ERR 0x0008 -#define MMC_R1B_CARD_ECC_ERR 0x0010 -#define MMC_R1B_WP_VIOLATION 0x0020 -#define MMC_R1B_ERASE_PARAM 0x0040 -#define MMC_R1B_OOR 0x0080 -#define MMC_R1B_IDLE_STATE 0x0100 -#define MMC_R1B_ERASE_RESET 0x0200 -#define MMC_R1B_ILLEGAL_CMD 0x0400 -#define MMC_R1B_COM_CRC_ERR 0x0800 -#define MMC_R1B_ERASE_SEQ_ERR 0x1000 -#define MMC_R1B_ADDR_ERR 0x2000 -#define MMC_R1B_PARAM_ERR 0x4000 - -typedef struct mmc_cid -{ -/* FIXME: BYTE_ORDER */ - uchar year:4, - month:4; - uchar sn[3]; - uchar fwrev:4, - hwrev:4; - uchar name[6]; - uchar id[3]; -} mmc_cid_t; - -typedef struct mmc_csd -{ - uint8_t csd_structure:2, - spec_ver:4, - rsvd1:2; - uint8_t taac; - uint8_t nsac; - uint8_t tran_speed; - uint16_t ccc:12, - read_bl_len:4; - uint64_t read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - erase_blk_en:1, - sector_size:7, - wp_grp_size:7, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:4, - content_prot_app:1; - uint8_t file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; -} mmc_csd_t; - -#endif /* __MMC_PXA_P_H__ */ diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/config.h index e664a5f67..049c44eaf 100644 --- a/include/asm-arm/arch-lpc2292/mmc.h +++ b/include/asm-arm/config.h @@ -1,6 +1,5 @@ /* - * A dummy header file for use with the LPC2292 port to keep the - * compiler happy. + * Copyright 2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -9,14 +8,17 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA + * */ -#ifndef _MMC_ARM_TDM_H_ -#define _MMC_ARM_TDM_H_ -#endif /* _MMC_ARM_TDM_H_ */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index ce6d25f9e..2c1e69be3 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1376,7 +1376,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OLIP8 1378 #define MACH_TYPE_GHI270HG 1379 #define MACH_TYPE_DAVINCI_DM6467_EVM 1380 -#define MACH_TYPE_DAVINCI_DM350_EVM 1381 +#define MACH_TYPE_DAVINCI_DM355_EVM 1381 #define MACH_TYPE_BLACKRIVER 1383 #define MACH_TYPE_SANDGATEWP 1384 #define MACH_TYPE_CDOTBWSG 1385 @@ -1806,7 +1806,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_PILZ_PMI5 1820 #define MACH_TYPE_JADE 1821 #define MACH_TYPE_KS8695_SOFTPLC 1822 -#define MACH_TYPE_GPRISC4 1823 +#define MACH_TYPE_GPRISC3 1823 #define MACH_TYPE_STAMP9260 1824 #define MACH_TYPE_SMDK6430 1825 #define MACH_TYPE_SMDKC100 1826 @@ -1857,6 +1857,139 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_IMX27IPCAM 1871 #define MACH_TYPE_NEMOC 1872 #define MACH_TYPE_GENEVA 1873 +#define MACH_TYPE_HTCPHAROS 1874 +#define MACH_TYPE_NEONC 1875 +#define MACH_TYPE_NAS7100 1876 +#define MACH_TYPE_TEUPHONE 1877 +#define MACH_TYPE_ANNAX_ETH2 1878 +#define MACH_TYPE_CSB733 1879 +#define MACH_TYPE_BK3 1880 +#define MACH_TYPE_OMAP_EM32 1881 +#define MACH_TYPE_ET9261CP 1882 +#define MACH_TYPE_JASPERC 1883 +#define MACH_TYPE_ISSI_ARM9 1884 +#define MACH_TYPE_UED 1885 +#define MACH_TYPE_ESIBLADE 1886 +#define MACH_TYPE_EYE02 1887 +#define MACH_TYPE_IMX27KBD 1888 +#define MACH_TYPE_SST61VC010_FPGA 1889 +#define MACH_TYPE_KIXVP435 1890 +#define MACH_TYPE_KIXNP435 1891 +#define MACH_TYPE_AFRICA 1892 +#define MACH_TYPE_NH233 1893 +#define MACH_TYPE_RD88F6183AP_GE 1894 +#define MACH_TYPE_BCM4760 1895 +#define MACH_TYPE_EDDY_V2 1896 +#define MACH_TYPE_REALVIEW_PBA8 1897 +#define MACH_TYPE_HID_A7 1898 +#define MACH_TYPE_HERO 1899 +#define MACH_TYPE_OMAP_POSEIDON 1900 +#define MACH_TYPE_REALVIEW_PBX 1901 +#define MACH_TYPE_MICRO9S 1902 +#define MACH_TYPE_MAKO 1903 +#define MACH_TYPE_XDAFLAME 1904 +#define MACH_TYPE_PHIDGET_SBC2 1905 +#define MACH_TYPE_LIMESTONE 1906 +#define MACH_TYPE_IPROBE_C32 1907 +#define MACH_TYPE_RUT100 1908 +#define MACH_TYPE_ASUSP535 1909 +#define MACH_TYPE_HTCRAPHAEL 1910 +#define MACH_TYPE_SYGDG1 1911 +#define MACH_TYPE_SYGDG2 1912 +#define MACH_TYPE_SEOUL 1913 +#define MACH_TYPE_SALERNO 1914 +#define MACH_TYPE_UCN_S3C64XX 1915 +#define MACH_TYPE_MSM7201A 1916 +#define MACH_TYPE_LPR1 1917 +#define MACH_TYPE_ARMADILLO500FX 1918 +#define MACH_TYPE_G3EVM 1919 +#define MACH_TYPE_Z3_DM355 1920 +#define MACH_TYPE_W90P910EVB 1921 +#define MACH_TYPE_W90P920EVB 1922 +#define MACH_TYPE_W90P950EVB 1923 +#define MACH_TYPE_W90N960EVB 1924 +#define MACH_TYPE_CAMHD 1925 +#define MACH_TYPE_MVC100 1926 +#define MACH_TYPE_ELECTRUM_200 1927 +#define MACH_TYPE_HTCJADE 1928 +#define MACH_TYPE_MEMPHIS 1929 +#define MACH_TYPE_IMX27SBC 1930 +#define MACH_TYPE_LEXTAR 1931 +#define MACH_TYPE_MV88F6281GTW_GE 1932 +#define MACH_TYPE_NCP 1933 +#define MACH_TYPE_Z32AN 1934 +#define MACH_TYPE_TMQ_CAPD 1935 +#define MACH_TYPE_OMAP3_WL 1936 +#define MACH_TYPE_CHUMBY 1937 +#define MACH_TYPE_ATSARM9 1938 +#define MACH_TYPE_DAVINCI_DM365_EVM 1939 +#define MACH_TYPE_BAHAMAS 1940 +#define MACH_TYPE_DAS 1941 +#define MACH_TYPE_MINIDAS 1942 +#define MACH_TYPE_VK1000 1943 +#define MACH_TYPE_CENTRO 1944 +#define MACH_TYPE_CTERA_2BAY 1945 +#define MACH_TYPE_EDGECONNECT 1946 +#define MACH_TYPE_ND27000 1947 +#define MACH_TYPE_GEMALTO_COBRA 1948 +#define MACH_TYPE_INGELABS_COMET 1949 +#define MACH_TYPE_POLLUX_WIZ 1950 +#define MACH_TYPE_BLACKSTONE 1951 +#define MACH_TYPE_TOPAZ 1952 +#define MACH_TYPE_AIXLE 1953 +#define MACH_TYPE_MW998 1954 +#define MACH_TYPE_NOKIA_RX51 1955 +#define MACH_TYPE_VSC5605EV 1956 +#define MACH_TYPE_NT98700DK 1957 +#define MACH_TYPE_ICONTACT 1958 +#define MACH_TYPE_SWARCO_FRCPU 1959 +#define MACH_TYPE_SWARCO_SCPU 1960 +#define MACH_TYPE_BBOX_P16 1961 +#define MACH_TYPE_BSTD 1962 +#define MACH_TYPE_SBC2440II 1963 +#define MACH_TYPE_PCM034 1964 +#define MACH_TYPE_NESO 1965 +#define MACH_TYPE_WLNX_9G20 1966 +#define MACH_TYPE_OMAP_ZOOM2 1967 +#define MACH_TYPE_TOTEMNOVA 1968 +#define MACH_TYPE_C5000 1969 +#define MACH_TYPE_UNIPO_AT91SAM9263 1970 +#define MACH_TYPE_ETHERNUT5 1971 +#define MACH_TYPE_ARM11 1972 +#define MACH_TYPE_CPUAT9260 1973 +#define MACH_TYPE_CPUPXA255 1974 +#define MACH_TYPE_CPUIMX27 1975 +#define MACH_TYPE_CHEFLUX 1976 +#define MACH_TYPE_EB_CPUX9K2 1977 +#define MACH_TYPE_OPCOTEC 1978 +#define MACH_TYPE_YT 1979 +#define MACH_TYPE_MOTOQ 1980 +#define MACH_TYPE_BSB1 1981 +#define MACH_TYPE_ACS5K 1982 +#define MACH_TYPE_MILAN 1983 +#define MACH_TYPE_QUARTZV2 1984 +#define MACH_TYPE_RSVP 1985 +#define MACH_TYPE_RMP200 1986 +#define MACH_TYPE_SNAPPER_9260 1987 +#define MACH_TYPE_DSM320 1988 +#define MACH_TYPE_ADSGCM 1989 +#define MACH_TYPE_ASE2_400 1990 +#define MACH_TYPE_PIZZA 1991 +#define MACH_TYPE_SPOT_NGPL 1992 +#define MACH_TYPE_ARMATA 1993 +#define MACH_TYPE_EXEDA 1994 +#define MACH_TYPE_MX31SF005 1995 +#define MACH_TYPE_F5D8231_4_V2 1996 +#define MACH_TYPE_Q2440 1997 +#define MACH_TYPE_QQ2440 1998 +#define MACH_TYPE_MINI2440 1999 +#define MACH_TYPE_COLIBRI300 2000 +#define MACH_TYPE_JADES 2001 +#define MACH_TYPE_SPARK 2002 +#define MACH_TYPE_BENZINA 2003 +#define MACH_TYPE_BLAZE 2004 +#define MACH_TYPE_LINKSTATION_LS_HGL 2005 +#define MACH_TYPE_HTCVENUS 2006 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -18226,14 +18359,14 @@ extern unsigned int __machine_arch_type; # define machine_is_davinci_dm6467_evm() (0) #endif -#ifdef CONFIG_MACH_DAVINCI_DM350_EVM +#ifdef CONFIG_MACH_DAVINCI_DM355_EVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DAVINCI_DM350_EVM +# define machine_arch_type MACH_TYPE_DAVINCI_DM355_EVM # endif -# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM350_EVM) +# define machine_is_davinci_dm355_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM355_EVM) #else # define machine_is_davinci_dm355_evm() (0) #endif @@ -22925,9 +23058,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_AT572D940HFEB # endif -# define machine_is_at572d940hfeb() (machine_arch_type == MACH_TYPE_AT572D940HFEB) +# define machine_is_at572d940hfek() (machine_arch_type == MACH_TYPE_AT572D940HFEB) #else -# define machine_is_at572d940hfeb() (0) +# define machine_is_at572d940hfek() (0) #endif #ifdef CONFIG_MACH_CYBOOK3 @@ -23386,14 +23519,14 @@ extern unsigned int __machine_arch_type; # define machine_is_ks8695_softplc() (0) #endif -#ifdef CONFIG_MACH_GPRISC4 +#ifdef CONFIG_MACH_GPRISC3 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_GPRISC4 +# define machine_arch_type MACH_TYPE_GPRISC3 # endif -# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC4) +# define machine_is_gprisc3() (machine_arch_type == MACH_TYPE_GPRISC3) #else # define machine_is_gprisc3() (0) #endif @@ -23981,9 +24114,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_NEMOC # endif -# define machine_is_nenoc() (machine_arch_type == MACH_TYPE_NEMOC) +# define machine_is_nemoc() (machine_arch_type == MACH_TYPE_NEMOC) #else -# define machine_is_nenoc() (0) +# define machine_is_nemoc() (0) #endif #ifdef CONFIG_MACH_GENEVA @@ -23998,6 +24131,1602 @@ extern unsigned int __machine_arch_type; # define machine_is_geneva() (0) #endif +#ifdef CONFIG_MACH_HTCPHAROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPHAROS +# endif +# define machine_is_htcpharos() (machine_arch_type == MACH_TYPE_HTCPHAROS) +#else +# define machine_is_htcpharos() (0) +#endif + +#ifdef CONFIG_MACH_NEONC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NEONC +# endif +# define machine_is_neonc() (machine_arch_type == MACH_TYPE_NEONC) +#else +# define machine_is_neonc() (0) +#endif + +#ifdef CONFIG_MACH_NAS7100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NAS7100 +# endif +# define machine_is_nas7100() (machine_arch_type == MACH_TYPE_NAS7100) +#else +# define machine_is_nas7100() (0) +#endif + +#ifdef CONFIG_MACH_TEUPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TEUPHONE +# endif +# define machine_is_teuphone() (machine_arch_type == MACH_TYPE_TEUPHONE) +#else +# define machine_is_teuphone() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_ETH2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_ETH2 +# endif +# define machine_is_annax_eth2() (machine_arch_type == MACH_TYPE_ANNAX_ETH2) +#else +# define machine_is_annax_eth2() (0) +#endif + +#ifdef CONFIG_MACH_CSB733 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB733 +# endif +# define machine_is_csb733() (machine_arch_type == MACH_TYPE_CSB733) +#else +# define machine_is_csb733() (0) +#endif + +#ifdef CONFIG_MACH_BK3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BK3 +# endif +# define machine_is_bk3() (machine_arch_type == MACH_TYPE_BK3) +#else +# define machine_is_bk3() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_EM32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_EM32 +# endif +# define machine_is_omap_em32() (machine_arch_type == MACH_TYPE_OMAP_EM32) +#else +# define machine_is_omap_em32() (0) +#endif + +#ifdef CONFIG_MACH_ET9261CP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ET9261CP +# endif +# define machine_is_et9261cp() (machine_arch_type == MACH_TYPE_ET9261CP) +#else +# define machine_is_et9261cp() (0) +#endif + +#ifdef CONFIG_MACH_JASPERC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JASPERC +# endif +# define machine_is_jasperc() (machine_arch_type == MACH_TYPE_JASPERC) +#else +# define machine_is_jasperc() (0) +#endif + +#ifdef CONFIG_MACH_ISSI_ARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ISSI_ARM9 +# endif +# define machine_is_issi_arm9() (machine_arch_type == MACH_TYPE_ISSI_ARM9) +#else +# define machine_is_issi_arm9() (0) +#endif + +#ifdef CONFIG_MACH_UED +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UED +# endif +# define machine_is_ued() (machine_arch_type == MACH_TYPE_UED) +#else +# define machine_is_ued() (0) +#endif + +#ifdef CONFIG_MACH_ESIBLADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ESIBLADE +# endif +# define machine_is_esiblade() (machine_arch_type == MACH_TYPE_ESIBLADE) +#else +# define machine_is_esiblade() (0) +#endif + +#ifdef CONFIG_MACH_EYE02 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EYE02 +# endif +# define machine_is_eye02() (machine_arch_type == MACH_TYPE_EYE02) +#else +# define machine_is_eye02() (0) +#endif + +#ifdef CONFIG_MACH_IMX27KBD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27KBD +# endif +# define machine_is_imx27kbd() (machine_arch_type == MACH_TYPE_IMX27KBD) +#else +# define machine_is_imx27kbd() (0) +#endif + +#ifdef CONFIG_MACH_SST61VC010_FPGA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SST61VC010_FPGA +# endif +# define machine_is_sst61vc010_fpga() (machine_arch_type == MACH_TYPE_SST61VC010_FPGA) +#else +# define machine_is_sst61vc010_fpga() (0) +#endif + +#ifdef CONFIG_MACH_KIXVP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXVP435 +# endif +# define machine_is_kixvp435() (machine_arch_type == MACH_TYPE_KIXVP435) +#else +# define machine_is_kixvp435() (0) +#endif + +#ifdef CONFIG_MACH_KIXNP435 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KIXNP435 +# endif +# define machine_is_kixnp435() (machine_arch_type == MACH_TYPE_KIXNP435) +#else +# define machine_is_kixnp435() (0) +#endif + +#ifdef CONFIG_MACH_AFRICA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AFRICA +# endif +# define machine_is_africa() (machine_arch_type == MACH_TYPE_AFRICA) +#else +# define machine_is_africa() (0) +#endif + +#ifdef CONFIG_MACH_NH233 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NH233 +# endif +# define machine_is_nh233() (machine_arch_type == MACH_TYPE_NH233) +#else +# define machine_is_nh233() (0) +#endif + +#ifdef CONFIG_MACH_RD88F6183AP_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RD88F6183AP_GE +# endif +# define machine_is_rd88f6183ap_ge() (machine_arch_type == MACH_TYPE_RD88F6183AP_GE) +#else +# define machine_is_rd88f6183ap_ge() (0) +#endif + +#ifdef CONFIG_MACH_BCM4760 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM4760 +# endif +# define machine_is_bcm4760() (machine_arch_type == MACH_TYPE_BCM4760) +#else +# define machine_is_bcm4760() (0) +#endif + +#ifdef CONFIG_MACH_EDDY_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDDY_V2 +# endif +# define machine_is_eddy_v2() (machine_arch_type == MACH_TYPE_EDDY_V2) +#else +# define machine_is_eddy_v2() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBA8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBA8 +# endif +# define machine_is_realview_pba8() (machine_arch_type == MACH_TYPE_REALVIEW_PBA8) +#else +# define machine_is_realview_pba8() (0) +#endif + +#ifdef CONFIG_MACH_HID_A7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HID_A7 +# endif +# define machine_is_hid_a7() (machine_arch_type == MACH_TYPE_HID_A7) +#else +# define machine_is_hid_a7() (0) +#endif + +#ifdef CONFIG_MACH_HERO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HERO +# endif +# define machine_is_hero() (machine_arch_type == MACH_TYPE_HERO) +#else +# define machine_is_hero() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_POSEIDON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_POSEIDON +# endif +# define machine_is_omap_poseidon() (machine_arch_type == MACH_TYPE_OMAP_POSEIDON) +#else +# define machine_is_omap_poseidon() (0) +#endif + +#ifdef CONFIG_MACH_REALVIEW_PBX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_REALVIEW_PBX +# endif +# define machine_is_realview_pbx() (machine_arch_type == MACH_TYPE_REALVIEW_PBX) +#else +# define machine_is_realview_pbx() (0) +#endif + +#ifdef CONFIG_MACH_MICRO9S +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MICRO9S +# endif +# define machine_is_micro9s() (machine_arch_type == MACH_TYPE_MICRO9S) +#else +# define machine_is_micro9s() (0) +#endif + +#ifdef CONFIG_MACH_MAKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAKO +# endif +# define machine_is_mako() (machine_arch_type == MACH_TYPE_MAKO) +#else +# define machine_is_mako() (0) +#endif + +#ifdef CONFIG_MACH_XDAFLAME +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XDAFLAME +# endif +# define machine_is_xdaflame() (machine_arch_type == MACH_TYPE_XDAFLAME) +#else +# define machine_is_xdaflame() (0) +#endif + +#ifdef CONFIG_MACH_PHIDGET_SBC2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PHIDGET_SBC2 +# endif +# define machine_is_phidget_sbc2() (machine_arch_type == MACH_TYPE_PHIDGET_SBC2) +#else +# define machine_is_phidget_sbc2() (0) +#endif + +#ifdef CONFIG_MACH_LIMESTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LIMESTONE +# endif +# define machine_is_limestone() (machine_arch_type == MACH_TYPE_LIMESTONE) +#else +# define machine_is_limestone() (0) +#endif + +#ifdef CONFIG_MACH_IPROBE_C32 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IPROBE_C32 +# endif +# define machine_is_iprobe_c32() (machine_arch_type == MACH_TYPE_IPROBE_C32) +#else +# define machine_is_iprobe_c32() (0) +#endif + +#ifdef CONFIG_MACH_RUT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RUT100 +# endif +# define machine_is_rut100() (machine_arch_type == MACH_TYPE_RUT100) +#else +# define machine_is_rut100() (0) +#endif + +#ifdef CONFIG_MACH_ASUSP535 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASUSP535 +# endif +# define machine_is_asusp535() (machine_arch_type == MACH_TYPE_ASUSP535) +#else +# define machine_is_asusp535() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL +# endif +# define machine_is_htcraphael() (machine_arch_type == MACH_TYPE_HTCRAPHAEL) +#else +# define machine_is_htcraphael() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG1 +# endif +# define machine_is_sygdg1() (machine_arch_type == MACH_TYPE_SYGDG1) +#else +# define machine_is_sygdg1() (0) +#endif + +#ifdef CONFIG_MACH_SYGDG2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SYGDG2 +# endif +# define machine_is_sygdg2() (machine_arch_type == MACH_TYPE_SYGDG2) +#else +# define machine_is_sygdg2() (0) +#endif + +#ifdef CONFIG_MACH_SEOUL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SEOUL +# endif +# define machine_is_seoul() (machine_arch_type == MACH_TYPE_SEOUL) +#else +# define machine_is_seoul() (0) +#endif + +#ifdef CONFIG_MACH_SALERNO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALERNO +# endif +# define machine_is_salerno() (machine_arch_type == MACH_TYPE_SALERNO) +#else +# define machine_is_salerno() (0) +#endif + +#ifdef CONFIG_MACH_UCN_S3C64XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UCN_S3C64XX +# endif +# define machine_is_ucn_s3c64xx() (machine_arch_type == MACH_TYPE_UCN_S3C64XX) +#else +# define machine_is_ucn_s3c64xx() (0) +#endif + +#ifdef CONFIG_MACH_MSM7201A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MSM7201A +# endif +# define machine_is_msm7201a() (machine_arch_type == MACH_TYPE_MSM7201A) +#else +# define machine_is_msm7201a() (0) +#endif + +#ifdef CONFIG_MACH_LPR1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPR1 +# endif +# define machine_is_lpr1() (machine_arch_type == MACH_TYPE_LPR1) +#else +# define machine_is_lpr1() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO500FX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO500FX +# endif +# define machine_is_armadillo500fx() (machine_arch_type == MACH_TYPE_ARMADILLO500FX) +#else +# define machine_is_armadillo500fx() (0) +#endif + +#ifdef CONFIG_MACH_G3EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_G3EVM +# endif +# define machine_is_g3evm() (machine_arch_type == MACH_TYPE_G3EVM) +#else +# define machine_is_g3evm() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM355 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM355 +# endif +# define machine_is_z3_dm355() (machine_arch_type == MACH_TYPE_Z3_DM355) +#else +# define machine_is_z3_dm355() (0) +#endif + +#ifdef CONFIG_MACH_W90P910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P910EVB +# endif +# define machine_is_w90p910evb() (machine_arch_type == MACH_TYPE_W90P910EVB) +#else +# define machine_is_w90p910evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P920EVB +# endif +# define machine_is_w90p920evb() (machine_arch_type == MACH_TYPE_W90P920EVB) +#else +# define machine_is_w90p920evb() (0) +#endif + +#ifdef CONFIG_MACH_W90P950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90P950EVB +# endif +# define machine_is_w90p950evb() (machine_arch_type == MACH_TYPE_W90P950EVB) +#else +# define machine_is_w90p950evb() (0) +#endif + +#ifdef CONFIG_MACH_W90N960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_W90N960EVB +# endif +# define machine_is_w90n960evb() (machine_arch_type == MACH_TYPE_W90N960EVB) +#else +# define machine_is_w90n960evb() (0) +#endif + +#ifdef CONFIG_MACH_CAMHD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CAMHD +# endif +# define machine_is_camhd() (machine_arch_type == MACH_TYPE_CAMHD) +#else +# define machine_is_camhd() (0) +#endif + +#ifdef CONFIG_MACH_MVC100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MVC100 +# endif +# define machine_is_mvc100() (machine_arch_type == MACH_TYPE_MVC100) +#else +# define machine_is_mvc100() (0) +#endif + +#ifdef CONFIG_MACH_ELECTRUM_200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ELECTRUM_200 +# endif +# define machine_is_electrum_200() (machine_arch_type == MACH_TYPE_ELECTRUM_200) +#else +# define machine_is_electrum_200() (0) +#endif + +#ifdef CONFIG_MACH_HTCJADE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCJADE +# endif +# define machine_is_htcjade() (machine_arch_type == MACH_TYPE_HTCJADE) +#else +# define machine_is_htcjade() (0) +#endif + +#ifdef CONFIG_MACH_MEMPHIS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEMPHIS +# endif +# define machine_is_memphis() (machine_arch_type == MACH_TYPE_MEMPHIS) +#else +# define machine_is_memphis() (0) +#endif + +#ifdef CONFIG_MACH_IMX27SBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27SBC +# endif +# define machine_is_imx27sbc() (machine_arch_type == MACH_TYPE_IMX27SBC) +#else +# define machine_is_imx27sbc() (0) +#endif + +#ifdef CONFIG_MACH_LEXTAR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEXTAR +# endif +# define machine_is_lextar() (machine_arch_type == MACH_TYPE_LEXTAR) +#else +# define machine_is_lextar() (0) +#endif + +#ifdef CONFIG_MACH_MV88F6281GTW_GE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV88F6281GTW_GE +# endif +# define machine_is_mv88f6281gtw_ge() (machine_arch_type == MACH_TYPE_MV88F6281GTW_GE) +#else +# define machine_is_mv88f6281gtw_ge() (0) +#endif + +#ifdef CONFIG_MACH_NCP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NCP +# endif +# define machine_is_ncp() (machine_arch_type == MACH_TYPE_NCP) +#else +# define machine_is_ncp() (0) +#endif + +#ifdef CONFIG_MACH_Z32AN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z32AN +# endif +# define machine_is_z32an_series() (machine_arch_type == MACH_TYPE_Z32AN) +#else +# define machine_is_z32an_series() (0) +#endif + +#ifdef CONFIG_MACH_TMQ_CAPD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TMQ_CAPD +# endif +# define machine_is_tmq_capd() (machine_arch_type == MACH_TYPE_TMQ_CAPD) +#else +# define machine_is_tmq_capd() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL +# endif +# define machine_is_omap3_wl() (machine_arch_type == MACH_TYPE_OMAP3_WL) +#else +# define machine_is_omap3_wl() (0) +#endif + +#ifdef CONFIG_MACH_CHUMBY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHUMBY +# endif +# define machine_is_chumby() (machine_arch_type == MACH_TYPE_CHUMBY) +#else +# define machine_is_chumby() (0) +#endif + +#ifdef CONFIG_MACH_ATSARM9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATSARM9 +# endif +# define machine_is_atsarm9() (machine_arch_type == MACH_TYPE_ATSARM9) +#else +# define machine_is_atsarm9() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DM365_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DM365_EVM +# endif +# define machine_is_davinci_dm365_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DM365_EVM) +#else +# define machine_is_davinci_dm365_evm() (0) +#endif + +#ifdef CONFIG_MACH_BAHAMAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BAHAMAS +# endif +# define machine_is_bahamas() (machine_arch_type == MACH_TYPE_BAHAMAS) +#else +# define machine_is_bahamas() (0) +#endif + +#ifdef CONFIG_MACH_DAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAS +# endif +# define machine_is_das() (machine_arch_type == MACH_TYPE_DAS) +#else +# define machine_is_das() (0) +#endif + +#ifdef CONFIG_MACH_MINIDAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINIDAS +# endif +# define machine_is_minidas() (machine_arch_type == MACH_TYPE_MINIDAS) +#else +# define machine_is_minidas() (0) +#endif + +#ifdef CONFIG_MACH_VK1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VK1000 +# endif +# define machine_is_vk1000() (machine_arch_type == MACH_TYPE_VK1000) +#else +# define machine_is_vk1000() (0) +#endif + +#ifdef CONFIG_MACH_CENTRO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CENTRO +# endif +# define machine_is_centro() (machine_arch_type == MACH_TYPE_CENTRO) +#else +# define machine_is_centro() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY +# endif +# define machine_is_ctera_2bay() (machine_arch_type == MACH_TYPE_CTERA_2BAY) +#else +# define machine_is_ctera_2bay() (0) +#endif + +#ifdef CONFIG_MACH_EDGECONNECT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EDGECONNECT +# endif +# define machine_is_edgeconnect() (machine_arch_type == MACH_TYPE_EDGECONNECT) +#else +# define machine_is_edgeconnect() (0) +#endif + +#ifdef CONFIG_MACH_ND27000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ND27000 +# endif +# define machine_is_nd27000() (machine_arch_type == MACH_TYPE_ND27000) +#else +# define machine_is_nd27000() (0) +#endif + +#ifdef CONFIG_MACH_GEMALTO_COBRA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMALTO_COBRA +# endif +# define machine_is_cobra() (machine_arch_type == MACH_TYPE_GEMALTO_COBRA) +#else +# define machine_is_cobra() (0) +#endif + +#ifdef CONFIG_MACH_INGELABS_COMET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INGELABS_COMET +# endif +# define machine_is_ingelabs_comet() (machine_arch_type == MACH_TYPE_INGELABS_COMET) +#else +# define machine_is_ingelabs_comet() (0) +#endif + +#ifdef CONFIG_MACH_POLLUX_WIZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_POLLUX_WIZ +# endif +# define machine_is_pollux_wiz() (machine_arch_type == MACH_TYPE_POLLUX_WIZ) +#else +# define machine_is_pollux_wiz() (0) +#endif + +#ifdef CONFIG_MACH_BLACKSTONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLACKSTONE +# endif +# define machine_is_blackstone() (machine_arch_type == MACH_TYPE_BLACKSTONE) +#else +# define machine_is_blackstone() (0) +#endif + +#ifdef CONFIG_MACH_TOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOPAZ +# endif +# define machine_is_topaz() (machine_arch_type == MACH_TYPE_TOPAZ) +#else +# define machine_is_topaz() (0) +#endif + +#ifdef CONFIG_MACH_AIXLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AIXLE +# endif +# define machine_is_aixle() (machine_arch_type == MACH_TYPE_AIXLE) +#else +# define machine_is_aixle() (0) +#endif + +#ifdef CONFIG_MACH_MW998 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW998 +# endif +# define machine_is_mw998() (machine_arch_type == MACH_TYPE_MW998) +#else +# define machine_is_mw998() (0) +#endif + +#ifdef CONFIG_MACH_NOKIA_RX51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOKIA_RX51 +# endif +# define machine_is_nokia_rx51() (machine_arch_type == MACH_TYPE_NOKIA_RX51) +#else +# define machine_is_nokia_rx51() (0) +#endif + +#ifdef CONFIG_MACH_VSC5605EV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VSC5605EV +# endif +# define machine_is_vsc5605ev() (machine_arch_type == MACH_TYPE_VSC5605EV) +#else +# define machine_is_vsc5605ev() (0) +#endif + +#ifdef CONFIG_MACH_NT98700DK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NT98700DK +# endif +# define machine_is_nt98700dk() (machine_arch_type == MACH_TYPE_NT98700DK) +#else +# define machine_is_nt98700dk() (0) +#endif + +#ifdef CONFIG_MACH_ICONTACT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ICONTACT +# endif +# define machine_is_icontact() (machine_arch_type == MACH_TYPE_ICONTACT) +#else +# define machine_is_icontact() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_FRCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_FRCPU +# endif +# define machine_is_swarco_frcpu() (machine_arch_type == MACH_TYPE_SWARCO_FRCPU) +#else +# define machine_is_swarco_frcpu() (0) +#endif + +#ifdef CONFIG_MACH_SWARCO_SCPU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SWARCO_SCPU +# endif +# define machine_is_swarco_scpu() (machine_arch_type == MACH_TYPE_SWARCO_SCPU) +#else +# define machine_is_swarco_scpu() (0) +#endif + +#ifdef CONFIG_MACH_BBOX_P16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BBOX_P16 +# endif +# define machine_is_bbox_p16() (machine_arch_type == MACH_TYPE_BBOX_P16) +#else +# define machine_is_bbox_p16() (0) +#endif + +#ifdef CONFIG_MACH_BSTD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSTD +# endif +# define machine_is_bstd() (machine_arch_type == MACH_TYPE_BSTD) +#else +# define machine_is_bstd() (0) +#endif + +#ifdef CONFIG_MACH_SBC2440II +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBC2440II +# endif +# define machine_is_sbc2440ii() (machine_arch_type == MACH_TYPE_SBC2440II) +#else +# define machine_is_sbc2440ii() (0) +#endif + +#ifdef CONFIG_MACH_PCM034 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCM034 +# endif +# define machine_is_pcm034() (machine_arch_type == MACH_TYPE_PCM034) +#else +# define machine_is_pcm034() (0) +#endif + +#ifdef CONFIG_MACH_NESO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NESO +# endif +# define machine_is_neso() (machine_arch_type == MACH_TYPE_NESO) +#else +# define machine_is_neso() (0) +#endif + +#ifdef CONFIG_MACH_WLNX_9G20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WLNX_9G20 +# endif +# define machine_is_wlnx_9g20() (machine_arch_type == MACH_TYPE_WLNX_9G20) +#else +# define machine_is_wlnx_9g20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_ZOOM2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_ZOOM2 +# endif +# define machine_is_omap_zoom2() (machine_arch_type == MACH_TYPE_OMAP_ZOOM2) +#else +# define machine_is_omap_zoom2() (0) +#endif + +#ifdef CONFIG_MACH_TOTEMNOVA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOTEMNOVA +# endif +# define machine_is_totemnova() (machine_arch_type == MACH_TYPE_TOTEMNOVA) +#else +# define machine_is_totemnova() (0) +#endif + +#ifdef CONFIG_MACH_C5000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C5000 +# endif +# define machine_is_c5000() (machine_arch_type == MACH_TYPE_C5000) +#else +# define machine_is_c5000() (0) +#endif + +#ifdef CONFIG_MACH_UNIPO_AT91SAM9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_UNIPO_AT91SAM9263 +# endif +# define machine_is_unipo_at91sam9263() (machine_arch_type == MACH_TYPE_UNIPO_AT91SAM9263) +#else +# define machine_is_unipo_at91sam9263() (0) +#endif + +#ifdef CONFIG_MACH_ETHERNUT5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERNUT5 +# endif +# define machine_is_ethernut5() (machine_arch_type == MACH_TYPE_ETHERNUT5) +#else +# define machine_is_ethernut5() (0) +#endif + +#ifdef CONFIG_MACH_ARM11 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM11 +# endif +# define machine_is_arm11() (machine_arch_type == MACH_TYPE_ARM11) +#else +# define machine_is_arm11() (0) +#endif + +#ifdef CONFIG_MACH_CPUAT9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUAT9260 +# endif +# define machine_is_cpuat9260() (machine_arch_type == MACH_TYPE_CPUAT9260) +#else +# define machine_is_cpuat9260() (0) +#endif + +#ifdef CONFIG_MACH_CPUPXA255 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUPXA255 +# endif +# define machine_is_cpupxa255() (machine_arch_type == MACH_TYPE_CPUPXA255) +#else +# define machine_is_cpupxa255() (0) +#endif + +#ifdef CONFIG_MACH_CPUIMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CPUIMX27 +# endif +# define machine_is_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +#else +# define machine_is_cpuimx27() (0) +#endif + +#ifdef CONFIG_MACH_CHEFLUX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CHEFLUX +# endif +# define machine_is_cheflux() (machine_arch_type == MACH_TYPE_CHEFLUX) +#else +# define machine_is_cheflux() (0) +#endif + +#ifdef CONFIG_MACH_EB_CPUX9K2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EB_CPUX9K2 +# endif +# define machine_is_eb_cpux9k2() (machine_arch_type == MACH_TYPE_EB_CPUX9K2) +#else +# define machine_is_eb_cpux9k2() (0) +#endif + +#ifdef CONFIG_MACH_OPCOTEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPCOTEC +# endif +# define machine_is_opcotec() (machine_arch_type == MACH_TYPE_OPCOTEC) +#else +# define machine_is_opcotec() (0) +#endif + +#ifdef CONFIG_MACH_YT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_YT +# endif +# define machine_is_yt() (machine_arch_type == MACH_TYPE_YT) +#else +# define machine_is_yt() (0) +#endif + +#ifdef CONFIG_MACH_MOTOQ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOQ +# endif +# define machine_is_motoq() (machine_arch_type == MACH_TYPE_MOTOQ) +#else +# define machine_is_motoq() (0) +#endif + +#ifdef CONFIG_MACH_BSB1 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BSB1 +# endif +# define machine_is_bsb1() (machine_arch_type == MACH_TYPE_BSB1) +#else +# define machine_is_bsb1() (0) +#endif + +#ifdef CONFIG_MACH_ACS5K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACS5K +# endif +# define machine_is_acs5k() (machine_arch_type == MACH_TYPE_ACS5K) +#else +# define machine_is_acs5k() (0) +#endif + +#ifdef CONFIG_MACH_MILAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MILAN +# endif +# define machine_is_milan() (machine_arch_type == MACH_TYPE_MILAN) +#else +# define machine_is_milan() (0) +#endif + +#ifdef CONFIG_MACH_QUARTZV2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUARTZV2 +# endif +# define machine_is_quartzv2() (machine_arch_type == MACH_TYPE_QUARTZV2) +#else +# define machine_is_quartzv2() (0) +#endif + +#ifdef CONFIG_MACH_RSVP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSVP +# endif +# define machine_is_rsvp() (machine_arch_type == MACH_TYPE_RSVP) +#else +# define machine_is_rsvp() (0) +#endif + +#ifdef CONFIG_MACH_RMP200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RMP200 +# endif +# define machine_is_rmp200() (machine_arch_type == MACH_TYPE_RMP200) +#else +# define machine_is_rmp200() (0) +#endif + +#ifdef CONFIG_MACH_SNAPPER_9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SNAPPER_9260 +# endif +# define machine_is_snapper_9260() (machine_arch_type == MACH_TYPE_SNAPPER_9260) +#else +# define machine_is_snapper_9260() (0) +#endif + +#ifdef CONFIG_MACH_DSM320 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DSM320 +# endif +# define machine_is_dsm320() (machine_arch_type == MACH_TYPE_DSM320) +#else +# define machine_is_dsm320() (0) +#endif + +#ifdef CONFIG_MACH_ADSGCM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ADSGCM +# endif +# define machine_is_adsgcm() (machine_arch_type == MACH_TYPE_ADSGCM) +#else +# define machine_is_adsgcm() (0) +#endif + +#ifdef CONFIG_MACH_ASE2_400 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ASE2_400 +# endif +# define machine_is_ase2_400() (machine_arch_type == MACH_TYPE_ASE2_400) +#else +# define machine_is_ase2_400() (0) +#endif + +#ifdef CONFIG_MACH_PIZZA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PIZZA +# endif +# define machine_is_pizza() (machine_arch_type == MACH_TYPE_PIZZA) +#else +# define machine_is_pizza() (0) +#endif + +#ifdef CONFIG_MACH_SPOT_NGPL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPOT_NGPL +# endif +# define machine_is_spot_ngpl() (machine_arch_type == MACH_TYPE_SPOT_NGPL) +#else +# define machine_is_spot_ngpl() (0) +#endif + +#ifdef CONFIG_MACH_ARMATA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMATA +# endif +# define machine_is_armata() (machine_arch_type == MACH_TYPE_ARMATA) +#else +# define machine_is_armata() (0) +#endif + +#ifdef CONFIG_MACH_EXEDA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EXEDA +# endif +# define machine_is_exeda() (machine_arch_type == MACH_TYPE_EXEDA) +#else +# define machine_is_exeda() (0) +#endif + +#ifdef CONFIG_MACH_MX31SF005 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31SF005 +# endif +# define machine_is_mx31sf005() (machine_arch_type == MACH_TYPE_MX31SF005) +#else +# define machine_is_mx31sf005() (0) +#endif + +#ifdef CONFIG_MACH_F5D8231_4_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_F5D8231_4_V2 +# endif +# define machine_is_f5d8231_4_v2() (machine_arch_type == MACH_TYPE_F5D8231_4_V2) +#else +# define machine_is_f5d8231_4_v2() (0) +#endif + +#ifdef CONFIG_MACH_Q2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Q2440 +# endif +# define machine_is_q2440() (machine_arch_type == MACH_TYPE_Q2440) +#else +# define machine_is_q2440() (0) +#endif + +#ifdef CONFIG_MACH_QQ2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QQ2440 +# endif +# define machine_is_qq2440() (machine_arch_type == MACH_TYPE_QQ2440) +#else +# define machine_is_qq2440() (0) +#endif + +#ifdef CONFIG_MACH_MINI2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MINI2440 +# endif +# define machine_is_mini2440() (machine_arch_type == MACH_TYPE_MINI2440) +#else +# define machine_is_mini2440() (0) +#endif + +#ifdef CONFIG_MACH_COLIBRI300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COLIBRI300 +# endif +# define machine_is_colibri300() (machine_arch_type == MACH_TYPE_COLIBRI300) +#else +# define machine_is_colibri300() (0) +#endif + +#ifdef CONFIG_MACH_JADES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JADES +# endif +# define machine_is_jades() (machine_arch_type == MACH_TYPE_JADES) +#else +# define machine_is_jades() (0) +#endif + +#ifdef CONFIG_MACH_SPARK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPARK +# endif +# define machine_is_spark() (machine_arch_type == MACH_TYPE_SPARK) +#else +# define machine_is_spark() (0) +#endif + +#ifdef CONFIG_MACH_BENZINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BENZINA +# endif +# define machine_is_benzina() (machine_arch_type == MACH_TYPE_BENZINA) +#else +# define machine_is_benzina() (0) +#endif + +#ifdef CONFIG_MACH_BLAZE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BLAZE +# endif +# define machine_is_blaze() (machine_arch_type == MACH_TYPE_BLAZE) +#else +# define machine_is_blaze() (0) +#endif + +#ifdef CONFIG_MACH_LINKSTATION_LS_HGL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LINKSTATION_LS_HGL +# endif +# define machine_is_linkstation_ls_hgl() (machine_arch_type == MACH_TYPE_LINKSTATION_LS_HGL) +#else +# define machine_is_linkstation_ls_hgl() (0) +#endif + +#ifdef CONFIG_MACH_HTCVENUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCVENUS +# endif +# define machine_is_htcvenus() (machine_arch_type == MACH_TYPE_HTCVENUS) +#else +# define machine_is_htcvenus() (0) +#endif + /* * These have not yet been registered */ diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h deleted file mode 100644 index 9caba9168..000000000 --- a/include/asm-avr32/arch-at32ap700x/mmc.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (C) 2004-2006 Atmel Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_AVR32_MMC_H -#define __ASM_AVR32_MMC_H - -struct mmc_cid { - unsigned long psn; - unsigned short oid; - unsigned char mid; - unsigned char prv; - unsigned char mdt; - char pnm[7]; -}; - -struct mmc_csd -{ - u8 csd_structure:2, - spec_vers:4, - rsvd1:2; - u8 taac; - u8 nsac; - u8 tran_speed; - u16 ccc:12, - read_bl_len:4; - u64 read_bl_partial:1, - write_blk_misalign:1, - read_blk_misalign:1, - dsr_imp:1, - rsvd2:2, - c_size:12, - vdd_r_curr_min:3, - vdd_r_curr_max:3, - vdd_w_curr_min:3, - vdd_w_curr_max:3, - c_size_mult:3, - sector_size:5, - erase_grp_size:5, - wp_grp_size:5, - wp_grp_enable:1, - default_ecc:2, - r2w_factor:3, - write_bl_len:4, - write_bl_partial:1, - rsvd3:5; - u8 file_format_grp:1, - copy:1, - perm_write_protect:1, - tmp_write_protect:1, - file_format:2, - ecc:2; - u8 crc:7; - u8 one:1; -}; - -#define R1_ILLEGAL_COMMAND (1 << 22) -#define R1_APP_CMD (1 << 5) - -#endif /* __ASM_AVR32_MMC_H */ diff --git a/include/asm-avr32/config.h b/include/asm-avr32/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-avr32/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-blackfin/blackfin-config-post.h b/include/asm-blackfin/blackfin-config-post.h index 0ab68ace7..fea473712 100644 --- a/include/asm-blackfin/blackfin-config-post.h +++ b/include/asm-blackfin/blackfin-config-post.h @@ -1,7 +1,7 @@ /* * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h * - * Copyright (c) 2007 Analog Devices Inc. + * Copyright (c) 2007-2008 Analog Devices Inc. * * Licensed under the GPL-2 or later. */ @@ -9,11 +9,6 @@ #ifndef __ASM_BLACKFIN_CONFIG_POST_H__ #define __ASM_BLACKFIN_CONFIG_POST_H__ -/* Check to make sure everything fits in external RAM */ -#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) -# error Memory Map does not fit into configuration -#endif - /* Sanity check CONFIG_BFIN_CPU */ #ifndef CONFIG_BFIN_CPU # error CONFIG_BFIN_CPU: your board config needs to define this @@ -65,8 +60,86 @@ #endif /* Using L1 scratch pad makes sense for everyone by default. */ -#ifndef CMD_LINE_ADDR -# define CMD_LINE_ADDR L1_SRAM_SCRATCH +#ifndef CONFIG_LINUX_CMDLINE_ADDR +# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH +#endif +#ifndef CONFIG_LINUX_CMDLINE_SIZE +# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE +#endif + +/* Set default SPI flash CS to the one we boot from */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS) +# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL +#endif + +/* Default/common Blackfin memory layout */ +#ifndef CONFIG_SYS_SDRAM_BASE +# define CONFIG_SYS_SDRAM_BASE 0 +#endif +#ifndef CONFIG_SYS_MAX_RAM_SIZE +# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024) +#endif +#ifndef CONFIG_SYS_MONITOR_BASE +# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN) +#endif +#ifndef CONFIG_SYS_MALLOC_BASE +# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) +#endif +#ifndef CONFIG_SYS_GBL_DATA_SIZE +# define CONFIG_SYS_GBL_DATA_SIZE (128) +#endif +#ifndef CONFIG_SYS_GBL_DATA_ADDR +# define CONFIG_SYS_GBL_DATA_ADDR (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) +#endif +#ifndef CONFIG_STACKBASE +# define CONFIG_STACKBASE (CONFIG_SYS_GBL_DATA_ADDR - 4) +#endif +#ifndef CONFIG_SYS_MEMTEST_START +# define CONFIG_SYS_MEMTEST_START 0 +#endif +#ifndef CONFIG_SYS_MEMTEST_END +# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4) +#endif + +/* Check to make sure everything fits in external RAM */ +#if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) +# error Memory Map does not fit into configuration +#endif + +/* Default/common Blackfin environment settings */ +#ifndef CONFIG_LOADADDR +# define CONFIG_LOADADDR 0x1000000 +#endif +#ifndef CONFIG_SYS_LOAD_ADDR +# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#endif +#ifndef CONFIG_SYS_BOOTM_LEN +# define CONFIG_SYS_BOOTM_LEN 0x4000000 +#endif +#ifndef CONFIG_SYS_PROMPT +# define CONFIG_SYS_PROMPT "bfin> " +#endif +#ifndef CONFIG_SYS_CBSIZE +# ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 +# else +# define CONFIG_SYS_CBSIZE 256 +# endif +#endif +#ifndef CONFIG_SYS_BARGSIZE +# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#endif +#ifndef CONFIG_SYS_PBSIZE +# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#endif +#ifndef CONFIG_SYS_MAXARGS +# define CONFIG_SYS_MAXARGS 16 +#endif +#ifndef CONFIG_SYS_HZ +# define CONFIG_SYS_HZ 1000 +#endif +#ifndef CONFIG_SYS_BAUDRATE_TABLE +# define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #endif #endif diff --git a/include/asm-blackfin/blackfin-config-pre.h b/include/asm-blackfin/blackfin-config-pre.h index 714352b1c..9df01ad25 100644 --- a/include/asm-blackfin/blackfin-config-pre.h +++ b/include/asm-blackfin/blackfin-config-pre.h @@ -38,4 +38,35 @@ #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */ #define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */ +#ifndef __ASSEMBLY__ +static inline const char *get_bfin_boot_mode(int bfin_boot) +{ + switch (bfin_boot) { + case BFIN_BOOT_BYPASS: return "bypass"; + case BFIN_BOOT_PARA: return "parallel flash"; + case BFIN_BOOT_SPI_MASTER: return "spi flash"; + case BFIN_BOOT_SPI_SLAVE: return "spi slave"; + case BFIN_BOOT_TWI_MASTER: return "i2c flash"; + case BFIN_BOOT_TWI_SLAVE: return "i2c slave"; + case BFIN_BOOT_UART: return "uart"; + case BFIN_BOOT_IDLE: return "idle"; + case BFIN_BOOT_FIFO: return "fifo"; + case BFIN_BOOT_MEM: return "memory"; + case BFIN_BOOT_16HOST_DMA: return "16bit dma"; + case BFIN_BOOT_8HOST_DMA: return "8bit dma"; + case BFIN_BOOT_NAND: return "nand flash"; + default: return "INVALID"; + } +} +#endif + +/* Define the default SPI CS used when booting out of SPI */ +#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \ + defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \ + defined(__ADSPBF51x__) +# define BFIN_BOOT_SPI_SSEL 2 +#else +# define BFIN_BOOT_SPI_SSEL 1 +#endif + #endif diff --git a/include/asm-blackfin/blackfin_local.h b/include/asm-blackfin/blackfin_local.h index 6f0e662a9..e17d8a200 100644 --- a/include/asm-blackfin/blackfin_local.h +++ b/include/asm-blackfin/blackfin_local.h @@ -43,6 +43,9 @@ #define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC)) #define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC) +#define L1_CACHE_SHIFT 5 +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + #include <asm/linkage.h> #ifndef __ASSEMBLY__ @@ -52,25 +55,22 @@ # include <linux/types.h> +extern u_long get_vco(void); +extern u_long get_cclk(void); extern u_long get_sclk(void); # define bfin_revid() (*pCHIPID >> 28) extern void blackfin_icache_flush_range(const void *, const void *); extern void blackfin_dcache_flush_range(const void *, const void *); -extern void blackfin_dcache_invalidate_range(const void *, const void *); - -/* Use DMA to move data from on chip to external memory. While this is - * required for only L1 instruction (it is not directly readable by the - * core via data loads), it isn't a huge performance issue for other - * regions (it's probably even faster than core load/stores). However, - * the DMA engine does not have access to the L1 scratchpad, and we - * cannot use DMA inside of the MMR space. +extern void blackfin_icache_dcache_flush_range(const void *, const void *); +extern void blackfin_dcache_flush_invalidate_range(const void *, const void *); + +/* Use DMA to move data from on chip to external memory. The L1 instruction + * regions can only be accessed via DMA, so if the address in question is in + * that region, make sure we attempt to DMA indirectly. */ -# define addr_bfin_on_chip_mem(addr) \ - (((unsigned long)(addr) >= 0xef000000 && (unsigned long)addr < SYSMMR_BASE) && \ - !((unsigned long)(addr) >= L1_SRAM_SCRATCH && \ - (unsigned long)(addr) < L1_SRAM_SCRATCH_END)) +# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) # include <asm/system.h> diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-blackfin/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 7c5127eca..035e8d835 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h @@ -7,82 +7,154 @@ */ /* This file shoule be up to date with: - * - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List + * - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List + * - Revision E, 08/18/2008; ADSP-BF527 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ #define _MACH_ANOMALY_H_ +#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) +# define ANOMALY_BF526 1 +#else +# define ANOMALY_BF526 0 +#endif +#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__) +# define ANOMALY_BF527 1 +#else +# define ANOMALY_BF527 0 +#endif + /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ #define ANOMALY_05000074 (1) /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ -#define ANOMALY_05000119 (1) +#define ANOMALY_05000119 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ #define ANOMALY_05000122 (1) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ #define ANOMALY_05000245 (1) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ #define ANOMALY_05000265 (1) -/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ +#define ANOMALY_05000310 (1) +/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ +#define ANOMALY_05000313 (__SILICON_REVISION__ < 2) /* Incorrect Access of OTP_STATUS During otp_write() Function */ -#define ANOMALY_05000328 (1) +#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ -#define ANOMALY_05000337 (1) +#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ -#define ANOMALY_05000341 (1) +#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */ -#define ANOMALY_05000342 (1) +#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* USB Calibration Value Is Not Initialized */ -#define ANOMALY_05000346 (1) +#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0xE510 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ -#define ANOMALY_05000347 (1) +#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Security Features Are Not Functional */ -#define ANOMALY_05000348 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1) +/* bfrom_SysControl() Firmware Function Performs Improper System Reset */ +#define ANOMALY_05000353 (ANOMALY_BF526) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ -#define ANOMALY_05000355 (1) +#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) +#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Incorrect Revision Number in DSPID Register */ -#define ANOMALY_05000364 (__SILICON_REVISION__ > 0) +#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) -/* New Feature: Higher Default CCLK Rate */ -#define ANOMALY_05000368 (1) +/* Incorrect Default CSEL Value in PLL_DIV */ +#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Authentication Fails To Initiate */ -#define ANOMALY_05000376 (__SILICON_REVISION__ > 0) +#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* Data Read From L3 Memory by USB DMA May be Corrupted */ -#define ANOMALY_05000380 (1) -/* USB Full-speed Mode not Fully Tested */ -#define ANOMALY_05000381 (1) -/* New Feature: Boot from OTP Memory */ -#define ANOMALY_05000385 (1) -/* New Feature: bfrom_SysControl() Routine */ -#define ANOMALY_05000386 (1) -/* New Feature: Programmable Preboot Settings */ -#define ANOMALY_05000387 (1) +#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* 8-Bit NAND Flash Boot Mode Not Functional */ +#define ANOMALY_05000382 (__SILICON_REVISION__ < 2) +/* Host Must Not Read Back During Host DMA Boot */ +#define ANOMALY_05000384 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Boot from OTP Memory Not Functional */ +#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* bfrom_SysControl() Firmware Routine Not Functional */ +#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Programmable Preboot Settings Not Functional */ +#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* CRC32 Checksum Support Not Functional */ +#define ANOMALY_05000388 (__SILICON_REVISION__ < 2) /* Reset Vector Must Not Be in SDRAM Memory Space */ -#define ANOMALY_05000389 (1) -/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */ -#define ANOMALY_05000392 (1) -/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */ -#define ANOMALY_05000393 (1) -/* New Feature: Log Buffer Functionality */ -#define ANOMALY_05000394 (1) -/* New Feature: Hook Routine Functionality */ -#define ANOMALY_05000395 (1) -/* New Feature: Header Indirect Bit */ -#define ANOMALY_05000396 (1) -/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */ -#define ANOMALY_05000397 (1) -/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */ -#define ANOMALY_05000398 (1) -/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */ -#define ANOMALY_05000399 (1) +#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */ +#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Log Buffer Not Functional */ +#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Hook Routine Not Functional */ +#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Header Indirect Bit Not Functional */ +#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ +#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */ +#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */ +#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */ -#define ANOMALY_05000401 (1) +#define ANOMALY_05000401 (__SILICON_REVISION__ < 2) +/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ +#define ANOMALY_05000403 (__SILICON_REVISION__ < 2) +/* Lockbox SESR Disallows Certain User Interrupts */ +#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) +/* Lockbox SESR Firmware Does Not Save/Restore Full Context */ +#define ANOMALY_05000405 (1) +/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ +#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) +/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ +#define ANOMALY_05000408 (1) +/* Lockbox firmware leaves MDMA0 channel enabled */ +#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) +/* Incorrect Default Internal Voltage Regulator Setting */ +#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ +#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) +/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ +#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +/* DEB2_URGENT Bit Not Functional */ +#define ANOMALY_05000415 (__SILICON_REVISION__ < 2) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */ +#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */ +#define ANOMALY_05000418 (__SILICON_REVISION__ < 2) +/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */ +#define ANOMALY_05000420 (__SILICON_REVISION__ < 2) +/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */ +#define ANOMALY_05000421 (1) +/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */ +#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */ +#define ANOMALY_05000423 (__SILICON_REVISION__ < 2) +/* Internal Voltage Regulator Not Trimmed */ +#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (__SILICON_REVISION__ < 2) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +#define ANOMALY_05000426 (1) +/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */ +#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +/* Software System Reset Corrupts PLL_LOCKCNT Register */ +#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1) +/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */ +#define ANOMALY_05000432 (ANOMALY_BF526) +/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */ +#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -95,10 +167,12 @@ #define ANOMALY_05000263 (0) #define ANOMALY_05000266 (0) #define ANOMALY_05000273 (0) +#define ANOMALY_05000285 (0) #define ANOMALY_05000307 (0) #define ANOMALY_05000311 (0) +#define ANOMALY_05000312 (0) #define ANOMALY_05000323 (0) -#define ANOMALY_05000353 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) #endif diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 7c34c3813..0d3a03429 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List + * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -97,11 +97,11 @@ /* UART STB Bit Incorrectly Affects Receiver Setting */ #define ANOMALY_05000231 (__SILICON_REVISION__ < 5) /* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */ -#define ANOMALY_05000233 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000233 (__SILICON_REVISION__ < 6) /* Incorrect Revision Number in DSPID Register */ #define ANOMALY_05000234 (__SILICON_REVISION__ == 4) /* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */ -#define ANOMALY_05000242 (__SILICON_REVISION__ < 4) +#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ #define ANOMALY_05000244 (__SILICON_REVISION__ < 5) /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ @@ -131,7 +131,7 @@ /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */ #define ANOMALY_05000264 (__SILICON_REVISION__ < 5) /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ -#define ANOMALY_05000265 (__SILICON_REVISION__ < 5) +#define ANOMALY_05000265 (1) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */ #define ANOMALY_05000269 (__SILICON_REVISION__ < 5) /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ @@ -141,23 +141,23 @@ /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ #define ANOMALY_05000272 (1) /* Writes to Synchronous SDRAM Memory May Be Lost */ -#define ANOMALY_05000273 (1) +#define ANOMALY_05000273 (__SILICON_REVISION__ < 6) /* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */ #define ANOMALY_05000276 (1) /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */ -#define ANOMALY_05000277 (1) +#define ANOMALY_05000277 (__SILICON_REVISION__ < 6) /* Disabling Peripherals with DMA Running May Cause DMA System Instability */ -#define ANOMALY_05000278 (1) +#define ANOMALY_05000278 (__SILICON_REVISION__ < 6) /* False Hardware Error Exception When ISR Context Is Not Restored */ -#define ANOMALY_05000281 (1) +#define ANOMALY_05000281 (__SILICON_REVISION__ < 6) /* Memory DMA Corruption with 32-Bit Data and Traffic Control */ -#define ANOMALY_05000282 (1) +#define ANOMALY_05000282 (__SILICON_REVISION__ < 6) /* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */ -#define ANOMALY_05000283 (1) +#define ANOMALY_05000283 (__SILICON_REVISION__ < 6) /* SPORTs May Receive Bad Data If FIFOs Fill Up */ -#define ANOMALY_05000288 (1) +#define ANOMALY_05000288 (__SILICON_REVISION__ < 6) /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */ -#define ANOMALY_05000301 (1) +#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ @@ -169,30 +169,37 @@ /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ #define ANOMALY_05000310 (1) /* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ -#define ANOMALY_05000311 (1) +#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ -#define ANOMALY_05000312 (1) +#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) /* PPI Is Level-Sensitive on First Transfer */ -#define ANOMALY_05000313 (1) +#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) /* Killed System MMR Write Completes Erroneously On Next System MMR Access */ -#define ANOMALY_05000315 (1) +#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ -#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) +#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6) /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ -#define ANOMALY_05000357 (1) +#define ANOMALY_05000357 (__SILICON_REVISION__ < 6) /* UART Break Signal Issues */ #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ #define ANOMALY_05000366 (1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (__SILICON_REVISION__ < 6) /* PPI Does Not Start Properly In Specific Mode */ -#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000400 (__SILICON_REVISION__ == 5) /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ -#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) +#define ANOMALY_05000402 (__SILICON_REVISION__ == 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) - +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* These anomalies have been "phased" out of analog.com anomaly sheets and are * here to show running on older silicon just isn't feasible. @@ -271,5 +278,9 @@ #define ANOMALY_05000266 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index 8d7f30579..9cb39121d 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List + * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -148,6 +148,14 @@ #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -160,5 +168,9 @@ #define ANOMALY_05000323 (0) #define ANOMALY_05000353 (1) #define ANOMALY_05000363 (0) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 1dc75ef1a..3b5430999 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision F, 06/11/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List + * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -36,7 +36,7 @@ /* TWI Slave Boot Mode Is Not Functional */ #define ANOMALY_05000324 (__SILICON_REVISION__ < 1) /* External FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000325 (__SILICON_REVISION__ < 1) +#define ANOMALY_05000325 (__SILICON_REVISION__ < 2) /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */ #define ANOMALY_05000327 (__SILICON_REVISION__ < 1) /* Incorrect Access of OTP_STATUS During otp_write() Function */ @@ -61,6 +61,8 @@ #define ANOMALY_05000344 (__SILICON_REVISION__ < 1) /* USB Calibration Value Is Not Intialized */ #define ANOMALY_05000346 (__SILICON_REVISION__ < 1) +/* USB Calibration Value to use */ +#define ANOMALY_05000346_value 0x5411 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */ #define ANOMALY_05000347 (__SILICON_REVISION__ < 1) /* Data Lost when Core Reads SDH Data FIFO */ @@ -68,7 +70,7 @@ /* PLL Status Register Is Inaccurate */ #define ANOMALY_05000351 (__SILICON_REVISION__ < 1) /* bfrom_SysControl() Firmware Function Performs Improper System Reset */ -#define ANOMALY_05000353 (1) +#define ANOMALY_05000353 (__SILICON_REVISION__ < 2) /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ #define ANOMALY_05000355 (__SILICON_REVISION__ < 1) /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */ @@ -86,13 +88,13 @@ /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */ #define ANOMALY_05000370 (__SILICON_REVISION__ < 1) /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ -#define ANOMALY_05000371 (1) +#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) /* Mobile DDR Operation Not Functional */ #define ANOMALY_05000377 (1) /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ -#define ANOMALY_05000378 (1) +#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ #define ANOMALY_05000379 (1) /* 8-Bit NAND Flash Boot Mode Not Functional */ @@ -126,25 +128,37 @@ /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */ #define ANOMALY_05000397 (__SILICON_REVISION__ < 1) /* Lockbox SESR Disallows Certain User Interrupts */ -#define ANOMALY_05000404 (1) +#define ANOMALY_05000404 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Does Not Save/Restore Full Context */ #define ANOMALY_05000405 (1) /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */ -#define ANOMALY_05000406 (1) +#define ANOMALY_05000406 (__SILICON_REVISION__ < 2) /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */ -#define ANOMALY_05000407 (1) +#define ANOMALY_05000407 (__SILICON_REVISION__ < 2) /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */ #define ANOMALY_05000408 (1) /* Lockbox firmware leaves MDMA0 channel enabled */ -#define ANOMALY_05000409 (1) +#define ANOMALY_05000409 (__SILICON_REVISION__ < 2) /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */ -#define ANOMALY_05000411 (1) -/* FIFO Boot Mode Is Not Functional */ -#define ANOMALY_05000412 (1) +#define ANOMALY_05000411 (__SILICON_REVISION__ < 2) /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */ -#define ANOMALY_05000413 (1) +#define ANOMALY_05000413 (__SILICON_REVISION__ < 2) /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */ -#define ANOMALY_05000414 (1) +#define ANOMALY_05000414 (__SILICON_REVISION__ < 2) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause Spurious Hardware Errors */ +#define ANOMALY_05000426 (1) +/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */ +#define ANOMALY_05000427 (__SILICON_REVISION__ < 2) +/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Behaves as a Buffer Status Bit Instead of an IRQ Status Bit */ +#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) +/* Software System Reset Corrupts PLL_LOCKCNT Register */ +#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000125 (0) @@ -161,5 +175,8 @@ #define ANOMALY_05000311 (0) #define ANOMALY_05000323 (0) #define ANOMALY_05000363 (0) +#define ANOMALY_05000412 (0) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-bf548/ports.h b/include/asm-blackfin/mach-bf548/ports.h index c8285163f..5f0e45ef5 100644 --- a/include/asm-blackfin/mach-bf548/ports.h +++ b/include/asm-blackfin/mach-bf548/ports.h @@ -236,7 +236,25 @@ #define PH14 0x4000 #define PH15 0x8000 -/* Port J Masks */ +/* Port I Masks */ +#define PI0 0x0001 +#define PI1 0x0002 +#define PI2 0x0004 +#define PI3 0x0008 +#define PI4 0x0010 +#define PI5 0x0020 +#define PI6 0x0040 +#define PI7 0x0080 +#define PI8 0x0100 +#define PI9 0x0200 +#define PI10 0x0400 +#define PI11 0x0800 +#define PI12 0x1000 +#define PI13 0x2000 +#define PI14 0x4000 +#define PI15 0x8000 + +/* Port I Masks */ #define PJ0 0x0001 #define PJ1 0x0002 #define PJ2 0x0004 diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index e9c4ca878..1a9e17562 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h @@ -7,7 +7,7 @@ */ /* This file shoule be up to date with: - * - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List + * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List */ #ifndef _MACH_ANOMALY_H_ @@ -264,6 +264,18 @@ #define ANOMALY_05000371 (1) /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ #define ANOMALY_05000403 (1) +/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ +#define ANOMALY_05000412 (1) +/* Speculative Fetches Can Cause Undesired External FIFO Operations */ +#define ANOMALY_05000416 (1) +/* Multichannel SPORT Channel Misalignment Under Specific Configuration */ +#define ANOMALY_05000425 (1) +/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */ +#define ANOMALY_05000426 (1) +/* Lost/Corrupted L2/L3 Memory Write after Speculative L2 Memory Read by Core B */ +#define ANOMALY_05000428 (__SILICON_REVISION__ > 3) +/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ +#define ANOMALY_05000443 (1) /* Anomalies that don't exist on this proc */ #define ANOMALY_05000158 (0) @@ -271,5 +283,8 @@ #define ANOMALY_05000273 (0) #define ANOMALY_05000311 (0) #define ANOMALY_05000353 (1) +#define ANOMALY_05000386 (1) +#define ANOMALY_05000432 (0) +#define ANOMALY_05000435 (0) #endif diff --git a/include/asm-blackfin/mach-common/bits/bootrom.h b/include/asm-blackfin/mach-common/bits/bootrom.h index 6cdaa4f89..fb97ff81b 100644 --- a/include/asm-blackfin/mach-common/bits/bootrom.h +++ b/include/asm-blackfin/mach-common/bits/bootrom.h @@ -88,27 +88,42 @@ #define _BOOTROM_REV 0xEF000040 #define _BOOTROM_SESR 0xEF001000 +#define BOOTROM_FOLLOWS_C_ABI 1 + #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 1 -/* Not available on initial BF54x or BF52x */ -#if (defined(__ADSPBF54x__) && __SILICON_REVISION__ < 1) || \ - (defined(__ADSPBF52x__) && __SILICON_REVISION__ < 2) -#define BOOTROM_CAPS_SYSCONTROL 0 -#else -#define BOOTROM_CAPS_SYSCONTROL 1 #endif +#ifndef BOOTROM_FOLLOWS_C_ABI +#define BOOTROM_FOLLOWS_C_ABI 0 #endif - #ifndef BOOTROM_CAPS_ADI_BOOT_STRUCTS #define BOOTROM_CAPS_ADI_BOOT_STRUCTS 0 #endif -#ifndef BOOTROM_CAPS_SYSCONTROL -#define BOOTROM_CAPS_SYSCONTROL 0 -#endif + +/* Possible syscontrol action flags */ +#define SYSCTRL_READ 0x00000000 /* read registers */ +#define SYSCTRL_WRITE 0x00000001 /* write registers */ +#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ +#define SYSCTRL_CORERESET 0x00000004 /* perform core reset */ +#define SYSCTRL_SOFTRESET 0x00000006 /* perform core and system reset */ +#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ +#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ +#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ +#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ +#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ +#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ +#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ +#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ #ifndef __ASSEMBLY__ +#if BOOTROM_FOLLOWS_C_ABI +# define BOOTROM_CALLED_FUNC_ATTR +#else +# define BOOTROM_CALLED_FUNC_ATTR __attribute__((saveall)) +#endif + /* Structures for the syscontrol() function */ typedef struct ADI_SYSCTRL_VALUES { uint16_t uwVrCtl; @@ -121,25 +136,26 @@ typedef struct ADI_SYSCTRL_VALUES { #ifndef _BOOTROM_SYSCONTROL #define _BOOTROM_SYSCONTROL 0 #endif -static uint32_t (* const syscontrol)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL; - -#endif /* __ASSEMBLY__ */ - -/* Possible syscontrol action flags */ -#define SYSCTRL_READ 0x00000000 /* read registers */ -#define SYSCTRL_WRITE 0x00000001 /* write registers */ -#define SYSCTRL_SYSRESET 0x00000002 /* perform system reset */ -#define SYSCTRL_SOFTRESET 0x00000004 /* perform core and system reset */ -#define SYSCTRL_VRCTL 0x00000010 /* read/write VR_CTL register */ -#define SYSCTRL_EXTVOLTAGE 0x00000020 /* VDDINT supplied externally */ -#define SYSCTRL_INTVOLTAGE 0x00000000 /* VDDINT generated by on-chip regulator */ -#define SYSCTRL_OTPVOLTAGE 0x00000040 /* For Factory Purposes Only */ -#define SYSCTRL_PLLCTL 0x00000100 /* read/write PLL_CTL register */ -#define SYSCTRL_PLLDIV 0x00000200 /* read/write PLL_DIV register */ -#define SYSCTRL_LOCKCNT 0x00000400 /* read/write PLL_LOCKCNT register */ -#define SYSCTRL_PLLSTAT 0x00000800 /* read/write PLL_STAT register */ +static uint32_t (* const bfrom_SysControl)(uint32_t action_flags, ADI_SYSCTRL_VALUES *power_settings, void *reserved) = (void *)_BOOTROM_SYSCONTROL; -#ifndef __ASSEMBLY__ +/* We need a dedicated function since we need to screw with the stack pointer + * when resetting. The on-chip ROM will save/restore registers on the stack + * when doing a system reset, so the stack cannot be outside of the chip. + */ +__attribute__((__noreturn__)) +static inline void bfrom_SoftReset(void *new_stack) +{ + while (1) + __asm__ __volatile__( + "sp = %[stack];" + "jump (%[bfrom_syscontrol]);" + : : [bfrom_syscontrol] "p"(bfrom_SysControl), + "q0"(SYSCTRL_SOFTRESET), + "q1"(0), + "q2"(NULL), + [stack] "p"(new_stack) + ); +} /* Structures for working with LDRs and boot rom callbacks */ typedef struct ADI_BOOT_HEADER { diff --git a/include/asm-blackfin/mach-common/bits/ebiu.h b/include/asm-blackfin/mach-common/bits/ebiu.h index ab530ad86..7c0c569ac 100644 --- a/include/asm-blackfin/mach-common/bits/ebiu.h +++ b/include/asm-blackfin/mach-common/bits/ebiu.h @@ -357,8 +357,8 @@ #define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ #define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ #define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ -#define EBSZ_256 0x0007 /* SDRAM External Bank Size = 256MB */ -#define EBSZ_512 0x0008 /* SDRAM External Bank Size = 512MB */ +#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */ +#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */ #define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ #define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ #define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ @@ -410,12 +410,31 @@ /* EBIU_SDSTAT Masks */ #define SDCI 0x0001 /* SDRAM controller is idle */ -#define SDSRA 0x0002 /* SDRAM SDRAM self refresh is active */ +#define SDSRA 0x0002 /* SDRAM self refresh is active */ #define SDPUA 0x0004 /* SDRAM power up active */ #define SDRS 0x0008 /* SDRAM is in reset state */ #define SDEASE 0x0010 /* SDRAM EAB sticky error status - W1C */ #define BGSTAT 0x0020 /* Bus granted */ +/* Only available on DDR based-parts */ +#else + +/* EBIU_ERRMST Masks */ +#define DEB0_ERROR 0x0001 /* DEB0 access on reserved memory */ +#define DEB1_ERROR 0x0002 /* DEB1 access on reserved memory */ +#define DEB2_ERROR 0x0004 /* DEB2 (USB) access on reserved memory */ +#define CORE_ERROR 0x0008 /* Core access on reserved memory */ +#define DEB0_MERROR 0x0010 /* DEB0 access on reserved memory and DEB0_ERROR is set */ +#define DEB1_MERROR 0x0020 /* DEB1 access on reserved memory and DEB1_ERROR is set */ +#define DEB2_MERROR 0x0040 /* DEB2 access on reserved memory and DEB2_ERROR is set */ +#define CORE_MERROR 0x0080 /* Core access on reserved memory and CORE_ERROR is set */ + +/* EBIU_RSTCTL Masks */ +#define DDR_SRESET 0x0001 /* Reset Control to DDR Controller */ +#define SRREQ 0x0008 /* Self Refresh Request */ +#define SRACK 0x0010 /* Self Refresh Request Acknowledgement */ +#define MDDRENABLE 0x0020 /* Mobile DDR Enable */ + #endif /* EBIU_SDGCTL */ #endif diff --git a/include/asm-blackfin/mach-common/bits/otp.h b/include/asm-blackfin/mach-common/bits/otp.h index d529a0a98..4e3f1afcf 100644 --- a/include/asm-blackfin/mach-common/bits/otp.h +++ b/include/asm-blackfin/mach-common/bits/otp.h @@ -9,23 +9,22 @@ #include "bootrom.h" -static uint32_t (* const otp_command)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND; -static uint32_t (* const otp_read)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ; -static uint32_t (* const otp_write)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE; +static uint32_t (* const bfrom_OtpCommand)(uint32_t command, uint32_t value) = (void *)_BOOTROM_OTP_COMMAND; +static uint32_t (* const bfrom_OtpRead)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_READ; +static uint32_t (* const bfrom_OtpWrite)(uint32_t page, uint32_t flags, uint64_t *page_content) = (void *)_BOOTROM_OTP_WRITE; #endif /* otp_command(): defines for "command" */ -#define OTP_INIT 0x00000001 -#define OTP_CLOSE 0x00000002 +#define OTP_INIT 0x00000001 +#define OTP_CLOSE 0x00000002 /* otp_{read,write}(): defines for "flags" */ -#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ -#define OTP_UPPER_HALF 0x00000001 -#define OTP_NO_ECC 0x00000010 /* do not use ECC */ -#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ -#define OTP_ACCESS_READ 0x00001000 -#define OTP_ACCESS_READWRITE 0x00002000 +#define OTP_LOWER_HALF 0x00000000 /* select upper/lower 64-bit half (bit 0) */ +#define OTP_UPPER_HALF 0x00000001 +#define OTP_NO_ECC 0x00000010 /* do not use ECC */ +#define OTP_LOCK 0x00000020 /* sets page protection bit for page */ +#define OTP_CHECK_FOR_PREV_WRITE 0x00000080 /* Return values for all functions */ #define OTP_SUCCESS 0x00000000 diff --git a/include/asm-blackfin/mach-common/bits/pata.h b/include/asm-blackfin/mach-common/bits/pata.h new file mode 100644 index 000000000..9b61824f1 --- /dev/null +++ b/include/asm-blackfin/mach-common/bits/pata.h @@ -0,0 +1,220 @@ +/* + * ATAPI Masks + */ + +#ifndef __BFIN_PERIPHERAL_PATA__ +#define __BFIN_PERIPHERAL_PATA__ + +/* Bit masks for ATAPI_CONTROL */ +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +/* Bit masks for ATAPI_CONTROL */ +#define PIO_START 0x1 /* Start PIO/Reg Op */ +#define MULTI_START 0x2 /* Start Multi-DMA Op */ +#define ULTRA_START 0x4 /* Start Ultra-DMA Op */ +#define XFER_DIR 0x8 /* Transfer Direction */ +#define IORDY_EN 0x10 /* IORDY Enable */ +#define FIFO_FLUSH 0x20 /* Flush FIFOs */ +#define SOFT_RST 0x40 /* Soft Reset */ +#define DEV_RST 0x80 /* Device Reset */ +#define TFRCNT_RST 0x100 /* Trans Count Reset */ +#define END_ON_TERM 0x200 /* End/Terminate Select */ +#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */ +#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */ + +/* Bit masks for ATAPI_STATUS */ +#define PIO_XFER_ON 0x1 /* PIO transfer in progress */ +#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */ +#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */ +#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */ + +/* Bit masks for ATAPI_DEV_ADDR */ +#define DEV_ADDR 0x1f /* Device Address */ + +/* Bit masks for ATAPI_INT_MASK */ +#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */ +#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */ +#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */ +#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */ +#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */ +#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */ +#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */ +#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */ +#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */ + +/* Bit masks for ATAPI_INT_STATUS */ +#define ATAPI_DEV_INT 0x1 /* Device interrupt status */ +#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */ +#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */ +#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */ +#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */ +#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */ +#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */ +#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */ +#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */ + +/* Bit masks for ATAPI_LINE_STATUS */ +#define ATAPI_INTR 0x1 /* Device interrupt to host line status */ +#define ATAPI_DASP 0x2 /* Device dasp to host line status */ +#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */ +#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */ +#define ATAPI_ADDR 0x70 /* ATAPI address line status */ +#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */ +#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */ +#define ATAPI_DIOWN 0x200 /* ATAPI write line status */ +#define ATAPI_DIORN 0x400 /* ATAPI read line status */ +#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_SM_STATE */ +#define PIO_CSTATE 0xf /* PIO mode state machine current state */ +#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */ +#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */ +#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */ + +/* Bit masks for ATAPI_TERMINATE */ +#define ATAPI_HOST_TERM 0x1 /* Host terminationation */ + +/* Bit masks for ATAPI_REG_TIM_0 */ +#define T2_REG 0xff /* End of cycle time for register access transfers */ +#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */ + +/* Bit masks for ATAPI_PIO_TIM_0 */ +#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */ +#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */ +#define T4_REG 0xf000 /* DIOW data hold */ + +/* Bit masks for ATAPI_PIO_TIM_1 */ +#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */ + +/* Bit masks for ATAPI_MULTI_TIM_0 */ +#define TD 0xff /* DIOR/DIOW asserted pulsewidth */ +#define TM 0xff00 /* Time from address valid to DIOR/DIOW */ + +/* Bit masks for ATAPI_MULTI_TIM_1 */ +#define TKW 0xff /* Selects DIOW negated pulsewidth */ +#define TKR 0xff00 /* Selects DIOR negated pulsewidth */ + +/* Bit masks for ATAPI_MULTI_TIM_2 */ +#define TH 0xff /* Selects DIOW data hold */ +#define TEOC 0xff00 /* Selects end of cycle for DMA */ + +/* Bit masks for ATAPI_ULTRA_TIM_0 */ +#define TACK 0xff /* Selects setup and hold times for TACK */ +#define TENV 0xff00 /* Selects envelope time */ + +/* Bit masks for ATAPI_ULTRA_TIM_1 */ +#define TDVS 0xff /* Selects data valid setup time */ +#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */ + +/* Bit masks for ATAPI_ULTRA_TIM_2 */ +#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */ +#define TMLI 0xff00 /* Selects interlock time */ + +/* Bit masks for ATAPI_ULTRA_TIM_3 */ +#define TZAH 0xff /* Selects minimum delay required for output */ +#define READY_PAUSE 0xff00 /* Selects ready to pause */ + +#endif /* __BFIN_PERIPHERAL_PATA__ */ diff --git a/include/asm-blackfin/mach-common/bits/sdh.h b/include/asm-blackfin/mach-common/bits/sdh.h new file mode 100644 index 000000000..8c5dd33f5 --- /dev/null +++ b/include/asm-blackfin/mach-common/bits/sdh.h @@ -0,0 +1,122 @@ +/* + * SDH Masks + */ + +#ifndef __BFIN_PERIPHERAL_SDH__ +#define __BFIN_PERIPHERAL_SDH__ + +/* Bit masks for SDH_COMMAND */ +#define CMD_IDX 0x3f /* Command Index */ +#define CMD_RSP 0x40 /* Response */ +#define CMD_L_RSP 0x80 /* Long Response */ +#define CMD_INT_E 0x100 /* Command Interrupt */ +#define CMD_PEND_E 0x200 /* Command Pending */ +#define CMD_E 0x400 /* Command Enable */ + +/* Bit masks for SDH_PWR_CTL */ +#define PWR_ON 0x3 /* Power On */ +#define SD_CMD_OD 0x40 /* Open Drain Output */ +#define ROD_CTL 0x80 /* Rod Control */ + +/* Bit masks for SDH_CLK_CTL */ +#define CLKDIV 0xff /* MC_CLK Divisor */ +#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */ +#define PWR_SV_E 0x200 /* Power Save Enable */ +#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */ +#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */ + +/* Bit masks for SDH_RESP_CMD */ +#define RESP_CMD 0x3f /* Response Command */ + +/* Bit masks for SDH_DATA_CTL */ +#define DTX_E 0x1 /* Data Transfer Enable */ +#define DTX_DIR 0x2 /* Data Transfer Direction */ +#define DTX_MODE 0x4 /* Data Transfer Mode */ +#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */ +#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */ + +/* Bit masks for SDH_STATUS */ +#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */ +#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */ +#define CMD_TIME_OUT 0x4 /* CMD Time Out */ +#define DAT_TIME_OUT 0x8 /* Data Time Out */ +#define TX_UNDERRUN 0x10 /* Transmit Underrun */ +#define RX_OVERRUN 0x20 /* Receive Overrun */ +#define CMD_RESP_END 0x40 /* CMD Response End */ +#define CMD_SENT 0x80 /* CMD Sent */ +#define DAT_END 0x100 /* Data End */ +#define START_BIT_ERR 0x200 /* Start Bit Error */ +#define DAT_BLK_END 0x400 /* Data Block End */ +#define CMD_ACT 0x800 /* CMD Active */ +#define TX_ACT 0x1000 /* Transmit Active */ +#define RX_ACT 0x2000 /* Receive Active */ +#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */ +#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */ +#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */ +#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */ +#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */ +#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */ +#define TX_DAT_RDY 0x100000 /* Transmit Data Available */ +#define RX_FIFO_RDY 0x200000 /* Receive Data Available */ + +/* Bit masks for SDH_STATUS_CLR */ +#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */ +#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */ +#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */ +#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */ +#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */ +#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */ +#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */ +#define CMD_SENT_STAT 0x80 /* CMD Sent Status */ +#define DAT_END_STAT 0x100 /* Data End Status */ +#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */ +#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */ + +/* Bit masks for SDH_MASK0 */ +#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */ +#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */ +#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */ +#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */ +#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */ +#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */ +#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */ +#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */ +#define DAT_END_MASK 0x100 /* Data End Mask */ +#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */ +#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */ +#define CMD_ACT_MASK 0x800 /* CMD Active Mask */ +#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */ +#define RX_ACT_MASK 0x2000 /* Receive Active Mask */ +#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */ +#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */ +#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */ +#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */ +#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */ +#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */ +#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */ +#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */ + +/* Bit masks for SDH_FIFO_CNT */ +#define FIFO_COUNT 0x7fff /* FIFO Count */ + +/* Bit masks for SDH_E_STATUS */ +#define SDIO_INT_DET 0x2 /* SDIO Int Detected */ +#define SD_CARD_DET 0x10 /* SD Card Detect */ + +/* Bit masks for SDH_E_MASK */ +#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */ +#define SCD_MSK 0x40 /* Mask Card Detect */ + +/* Bit masks for SDH_CFG */ +#define CLKS_EN 0x1 /* Clocks Enable */ +#define SD4E 0x4 /* SDIO 4-Bit Enable */ +#define MWE 0x8 /* Moving Window Enable */ +#define SD_RST 0x10 /* SDMMC Reset */ +#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */ +#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */ +#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */ + +/* Bit masks for SDH_RD_WAIT_EN */ +#define RWR 0x1 /* Read Wait Request */ + +#endif diff --git a/include/asm-blackfin/mmc.h b/include/asm-blackfin/mmc.h new file mode 100644 index 000000000..aa2ac95a9 --- /dev/null +++ b/include/asm-blackfin/mmc.h @@ -0,0 +1 @@ +#include <asm-avr32/arch-at32ap700x/mmc.h> diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h index 39651d206..000ffe52c 100644 --- a/include/asm-blackfin/posix_types.h +++ b/include/asm-blackfin/posix_types.h @@ -40,15 +40,17 @@ typedef unsigned short __kernel_mode_t; typedef unsigned short __kernel_nlink_t; typedef long __kernel_off_t; typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; +typedef unsigned int __kernel_ipc_pid_t; +typedef unsigned int __kernel_uid_t; +typedef unsigned int __kernel_gid_t; +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; typedef int __kernel_daddr_t; typedef char *__kernel_caddr_t; typedef unsigned short __kernel_uid16_t; @@ -67,14 +69,10 @@ typedef long long __kernel_loff_t; #endif typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ } __kernel_fsid_t; -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) +#if defined(__KERNEL__) #undef __FD_SET #define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d)) @@ -88,6 +86,6 @@ typedef struct { #undef __FD_ZERO #define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp))) -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ +#endif /* defined(__KERNEL__) */ #endif diff --git a/include/asm-i386/config.h b/include/asm-i386/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-i386/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-i386/interrupt.h b/include/asm-i386/interrupt.h new file mode 100644 index 000000000..315b4001c --- /dev/null +++ b/include/asm-i386/interrupt.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_INTERRUPT_H_ +#define __ASM_INTERRUPT_H_ 1 + +void set_vector(int intnum, void *routine); + +#endif diff --git a/include/asm-m68k/config.h b/include/asm-m68k/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-m68k/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index 787761689..d25261bcd 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -37,8 +37,27 @@ #define MCF_FMPLL_SYNCR 0x120000 #define MCF_FMPLL_SYNSR 0x120004 + #define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24) +#define MCF_SYNCR_MFD_4X 0x00000000 +#define MCF_SYNCR_MFD_6X 0x01000000 +#define MCF_SYNCR_MFD_8X 0x02000000 +#define MCF_SYNCR_MFD_10X 0x03000000 +#define MCF_SYNCR_MFD_12X 0x04000000 +#define MCF_SYNCR_MFD_14X 0x05000000 +#define MCF_SYNCR_MFD_16X 0x06000000 +#define MCF_SYNCR_MFD_18X 0x07000000 + #define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19) +#define MCF_SYNCR_RFD_DIV1 0x00000000 +#define MCF_SYNCR_RFD_DIV2 0x00080000 +#define MCF_SYNCR_RFD_DIV4 0x00100000 +#define MCF_SYNCR_RFD_DIV8 0x00180000 +#define MCF_SYNCR_RFD_DIV16 0x00200000 +#define MCF_SYNCR_RFD_DIV32 0x00280000 +#define MCF_SYNCR_RFD_DIV64 0x00300000 +#define MCF_SYNCR_RFD_DIV128 0x00380000 + #define MCF_FMPLL_SYNSR_LOCK 0x8 #define MCF_WTM_WCR 0x140000 @@ -50,17 +69,79 @@ #define MCF_RCM_RCR_FRCRSTOUT 0x40 #define MCF_RCM_RCR_SOFTRST 0x80 +#define MCF_GPIO_PODR_ADDR 0x100000 +#define MCF_GPIO_PODR_DATAH 0x100001 +#define MCF_GPIO_PODR_DATAL 0x100002 +#define MCF_GPIO_PODR_BUSCTL 0x100003 +#define MCF_GPIO_PODR_BS 0x100004 +#define MCF_GPIO_PODR_CS 0x100005 +#define MCF_GPIO_PODR_SDRAM 0x100006 +#define MCF_GPIO_PODR_FECI2C 0x100007 +#define MCF_GPIO_PODR_UARTH 0x100008 +#define MCF_GPIO_PODR_UARTL 0x100009 +#define MCF_GPIO_PODR_QSPI 0x10000A +#define MCF_GPIO_PODR_TIMER 0x10000B + +#define MCF_GPIO_PDDR_ADDR 0x100010 +#define MCF_GPIO_PDDR_DATAH 0x100011 +#define MCF_GPIO_PDDR_DATAL 0x100012 +#define MCF_GPIO_PDDR_BUSCTL 0x100013 +#define MCF_GPIO_PDDR_BS 0x100014 +#define MCF_GPIO_PDDR_CS 0x100015 +#define MCF_GPIO_PDDR_SDRAM 0x100016 +#define MCF_GPIO_PDDR_FECI2C 0x100017 +#define MCF_GPIO_PDDR_UARTH 0x100018 +#define MCF_GPIO_PDDR_UARTL 0x100019 +#define MCF_GPIO_PDDR_QSPI 0x10001A +#define MCF_GPIO_PDDR_TIMER 0x10001B + +#define MCF_GPIO_PPDSDR_ADDR 0x100020 +#define MCF_GPIO_PPDSDR_DATAH 0x100021 +#define MCF_GPIO_PPDSDR_DATAL 0x100022 +#define MCF_GPIO_PPDSDR_BUSCTL 0x100023 +#define MCF_GPIO_PPDSDR_BS 0x100024 +#define MCF_GPIO_PPDSDR_CS 0x100025 +#define MCF_GPIO_PPDSDR_SDRAM 0x100026 +#define MCF_GPIO_PPDSDR_FECI2C 0x100027 +#define MCF_GPIO_PPDSDR_UARTH 0x100028 +#define MCF_GPIO_PPDSDR_UARTL 0x100029 +#define MCF_GPIO_PPDSDR_QSPI 0x10002A +#define MCF_GPIO_PPDSDR_TIMER 0x10002B + +#define MCF_GPIO_PCLRR_ADDR 0x100030 +#define MCF_GPIO_PCLRR_DATAH 0x100031 +#define MCF_GPIO_PCLRR_DATAL 0x100032 +#define MCF_GPIO_PCLRR_BUSCTL 0x100033 +#define MCF_GPIO_PCLRR_BS 0x100034 +#define MCF_GPIO_PCLRR_CS 0x100035 +#define MCF_GPIO_PCLRR_SDRAM 0x100036 +#define MCF_GPIO_PCLRR_FECI2C 0x100037 +#define MCF_GPIO_PCLRR_UARTH 0x100038 +#define MCF_GPIO_PCLRR_UARTL 0x100039 +#define MCF_GPIO_PCLRR_QSPI 0x10003A +#define MCF_GPIO_PCLRR_TIMER 0x10003B + #define MCF_GPIO_PAR_AD 0x100040 +#define MCF_GPIO_PAR_BUSCTL 0x100042 +#define MCF_GPIO_PAR_BS 0x100044 #define MCF_GPIO_PAR_CS 0x100045 #define MCF_GPIO_PAR_SDRAM 0x100046 #define MCF_GPIO_PAR_FECI2C 0x100047 #define MCF_GPIO_PAR_UART 0x100048 +#define MCF_GPIO_PAR_QSPI 0x10004A +#define MCF_GPIO_PAR_TIMER 0x10004C + +#define MCF_DSCR_EIM 0x100050 +#define MCF_DCSR_FEC12C 0x100052 +#define MCF_DCSR_UART 0x100053 +#define MCF_DCSR_QSPI 0x100054 +#define MCF_DCSR_TIMER 0x100055 #define MCF_CCM_CIR 0x11000A #define MCF_CCM_CIR_PRN_MASK 0x3F #define MCF_CCM_CIR_PIN_LEN 6 -#define MCF_CCM_CIR_PIN_MCF5270 0x2e -#define MCF_CCM_CIR_PIN_MCF5271 0x80 +#define MCF_CCM_CIR_PIN_MCF5270 0x002e +#define MCF_CCM_CIR_PIN_MCF5271 0x0032 #define MCF_GPIO_AD_ADDR23 0x80 #define MCF_GPIO_AD_ADDR22 0x40 diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-microblaze/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-mips/config.h b/include/asm-mips/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-mips/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index 031186d03..025012ae6 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -118,7 +118,7 @@ static inline void set_io_port_base(unsigned long base) * Change virtual addresses to physical addresses and vv. * These are trivial on the 1:1 Linux/MIPS mapping */ -extern inline phys_addr_t virt_to_phys(void * address) +extern inline phys_addr_t virt_to_phys(volatile void * address) { return CPHYSADDR(address); } diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-nios/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-nios2/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h new file mode 100644 index 000000000..275a7c828 --- /dev/null +++ b/include/asm-ppc/config.h @@ -0,0 +1,32 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#ifndef CONFIG_MAX_MEM_MAPPED +#if defined(CONFIG_4xx) || defined(CONFIG_E500) +#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) +#else +#define CONFIG_MAX_MEM_MAPPED (256 << 20) +#endif +#endif + +#endif diff --git a/include/asm-ppc/cpm_8260.h b/include/asm-ppc/cpm_8260.h index 7e06940c9..8302404ab 100644 --- a/include/asm-ppc/cpm_8260.h +++ b/include/asm-ppc/cpm_8260.h @@ -546,6 +546,34 @@ typedef struct scc_trans { #define BD_SCC_TX_LAST ((ushort)0x0800) +/* SCC as HDLC controller - taken from commproc.h + */ +typedef struct scc_hdlc { + sccp_t sh_genscc; + /* + * HDLC specific parameter RAM + */ + uchar res[4]; /* reserved */ + ulong sh_cmask; /* CRC constant */ + ulong sh_cpres; /* CRC preset */ + ushort sh_disfc; /* discarded frame counter */ + ushort sh_crcec; /* CRC error counter */ + ushort sh_abtsc; /* abort sequence counter */ + ushort sh_nmarc; /* nonmatching address rx cnt */ + ushort sh_retrc; /* frame retransmission cnt */ + ushort sh_mflr; /* maximum frame length reg */ + ushort sh_maxcnt; /* maximum length counter */ + ushort sh_rfthr; /* received frames threshold */ + ushort sh_rfcnt; /* received frames count */ + ushort sh_hmask; /* user defined frm addr mask */ + ushort sh_haddr1; /* user defined frm address 1 */ + ushort sh_haddr2; /* user defined frm address 2 */ + ushort sh_haddr3; /* user defined frm address 3 */ + ushort sh_haddr4; /* user defined frm address 4 */ + ushort tmp; /* temp */ + ushort tmp_mb; /* temp */ +} scc_hdlc_t; + /* How about some FCCs..... */ #define FCC_GFMR_DIAG_NORM ((uint)0x00000000) diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index 05db0de8f..bfef4dfd6 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -88,39 +88,4 @@ #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */ #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */ - -/* BAT (block address translation */ -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - #endif /* __E300_H__ */ diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c1ea7cd6b..6e3b2559c 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -34,7 +34,10 @@ typedef ddr2_spd_eeprom_t generic_spd_eeprom_t; #elif defined(CONFIG_FSL_DDR3) #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (3) /* FIXME */ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; +#ifndef CONFIG_FSL_SDRAM_TYPE +#define CONFIG_FSL_SDRAM_TYPE SDRAM_TYPE_DDR3 #endif +#endif /* #if defined(CONFIG_FSL_DDR1) */ /* define bank(chip select) interleaving mode */ #define FSL_DDR_CS0_CS1 0x40 @@ -48,6 +51,23 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t; #define FSL_DDR_BANK_INTERLEAVING 0x2 #define FSL_DDR_SUPERBANK_INTERLEAVING 0x3 +/* DDR_SDRAM_CFG - DDR SDRAM Control Configuration + */ +#define SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG_SREN 0x40000000 +#define SDRAM_CFG_ECC_EN 0x20000000 +#define SDRAM_CFG_RD_EN 0x10000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR1 0x02000000 +#define SDRAM_CFG_SDRAM_TYPE_DDR2 0x03000000 +#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 +#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 +#define SDRAM_CFG_DYN_PWR 0x00200000 +#define SDRAM_CFG_32_BE 0x00080000 +#define SDRAM_CFG_8_BE 0x00040000 +#define SDRAM_CFG_NCAP 0x00020000 +#define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_BI 0x00000001 + /* Record of register values computed */ typedef struct fsl_ddr_cfg_regs_s { struct { @@ -143,6 +163,10 @@ typedef struct memctl_options_s { unsigned int bstopre; unsigned int tCKE_clock_pulse_width_ps; /* tCKE */ unsigned int tFAW_window_four_activates_ps; /* tFAW -- FOUR_ACT */ + + /* Automatic self refresh */ + unsigned int auto_self_refresh_en; + unsigned int sr_it; } memctl_options_t; extern phys_size_t fsl_ddr_sdram(void); diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index 5bba08d44..e06a1a6e0 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -42,7 +42,7 @@ enum law_trgt_if { #ifndef CONFIG_MPC8641 LAW_TRGT_IF_PCIE_1 = 0x02, #endif -#ifndef CONFIG_MPC8572 +#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020) LAW_TRGT_IF_PCIE_3 = 0x03, #endif LAW_TRGT_IF_LBC = 0x04, @@ -61,7 +61,7 @@ enum law_trgt_if { #define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI #endif -#ifdef CONFIG_MPC8572 +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 51fc5c13b..9fa0b6594 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -28,6 +28,8 @@ #define BR_BA 0xFFFF8000 #define BR_BA_SHIFT 15 +#define BR_XBA 0x00006000 +#define BR_XBA_SHIFT 13 #define BR_PS 0x00001800 #define BR_PS_SHIFT 11 #define BR_PS_8 0x00000800 /* Port Size 8 bit */ @@ -70,7 +72,7 @@ #endif /* Convert an address into the right format for the BR registers */ -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC) #define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \ ((x & 0x300000000ULL) >> 19))) #else @@ -90,6 +92,8 @@ #define OR_GPCM_AM 0xFFFF8000 #define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_XAM 0x00006000 +#define OR_GPCM_XAM_SHIFT 13 #define OR_GPCM_BCTLD 0x00001000 #define OR_GPCM_BCTLD_SHIFT 12 #define OR_GPCM_CSNT 0x00000800 @@ -132,6 +136,8 @@ #define OR_FCM_AM 0xFFFF8000 #define OR_FCM_AM_SHIFT 15 +#define OR_FCM_XAM 0x00006000 +#define OR_FCM_XAM_SHIFT 13 #define OR_FCM_BCTLD 0x00001000 #define OR_FCM_BCTLD_SHIFT 12 #define OR_FCM_PGS 0x00000400 @@ -300,7 +306,10 @@ #define LCRR_EADC_2 0x00020000 #define LCRR_EADC_3 0x00030000 #define LCRR_EADC_4 0x00000000 -#define LCRR_CLKDIV 0x0000000F +/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit + * should always be zero on older parts that have a four bit CLKDIV. + */ +#define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index aade097fa..e5a3b2c17 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -75,7 +75,7 @@ typedef struct global_data { u32 lbiu_clk; u32 lclk_clk; u32 pci_clk; -#if defined(CONFIG_MPC837X) +#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X) u32 pciexp1_clk; u32 pciexp2_clk; #endif @@ -89,6 +89,9 @@ typedef struct global_data { #if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536) u32 sdhc_clk; #endif +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) + u32 lbc_clk; +#endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */ #if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) u32 i2c1_clk; u32 i2c2_clk; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index cd9094519..808786985 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -415,7 +415,25 @@ typedef struct ioctrl512x { * IIM */ typedef struct iim512x { - u8 fixme[0x1000]; + u32 stat; /* IIM status register */ + u32 statm; /* IIM status IRQ mask */ + u32 err; /* IIM errors register */ + u32 emask; /* IIM error IRQ mask */ + u32 fctl; /* IIM fuse control register */ + u32 ua; /* IIM upper address register */ + u32 la; /* IIM lower address register */ + u32 sdat; /* IIM explicit sense data */ + u8 res0[0x08]; + u32 prg_p; /* IIM program protection register */ + u8 res1[0x10]; + u32 divide; /* IIM divide factor register */ + u8 res2[0x7c0]; + u32 fbac0; /* IIM fuse bank 0 prot (for Freescale use) */ + u32 fb0w0[0x1f]; /* IIM fuse bank 0 data (for Freescale use) */ + u8 res3[0x380]; + u32 fbac1; /* IIM fuse bank 1 protection */ + u32 fb1w1[0x01f]; /* IIM fuse bank 1 data */ + u8 res4[0x380]; } iim512x_t; /* @@ -451,7 +469,34 @@ typedef struct lpc512x { * PATA */ typedef struct pata512x { - u8 fixme[0x100]; + /* LOCAL Registers */ + u32 pata_time1; /* Time register 1: PIO and tx timing parameter */ + u32 pata_time2; /* Time register 2: PIO timing parameter */ + u32 pata_time3; /* Time register 3: PIO and MDMA timing parameter */ + u32 pata_time4; /* Time register 4: MDMA and UDMA timing parameter */ + u32 pata_time5; /* Time register 5: UDMA timing parameter */ + u32 pata_time6; /* Time register 6: UDMA timing parameter */ + u32 pata_fifo_data32; /* 32bit wide dataport to/from FIFO */ + u32 pata_fifo_data16; /* 16bit wide dataport to/from FIFO */ + u32 pata_fifo_fill; /* FIFO filling in halfwords (READONLY)*/ + u32 pata_ata_control; /* ATA Interface control register */ + u32 pata_irq_pending; /* Interrupt pending register (READONLY) */ + u32 pata_irq_enable; /* Interrupt enable register */ + u32 pata_irq_clear; /* Interrupt clear register (WRITEONLY)*/ + u32 pata_fifo_alarm; /* fifo alarm threshold */ + u32 res1[0x1A]; + /* DRIVE Registers */ + u32 pata_drive_data; /* drive data register*/ + u32 pata_drive_features;/* drive features register */ + u32 pata_drive_sectcnt; /* drive sector count register */ + u32 pata_drive_sectnum; /* drive sector number register */ + u32 pata_drive_cyllow; /* drive cylinder low register */ + u32 pata_drive_cylhigh; /* drive cylinder high register */ + u32 pata_drive_dev_head;/* drive device head register */ + u32 pata_drive_command; /* write = drive command, read = drive status reg */ + u32 res2[0x06]; + u32 pata_drive_alt_stat;/* write = drive control, read = drive alt status reg */ + u32 res3[0x09]; } pata512x_t; /* diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index df24a6e87..7b847f802 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -52,23 +52,28 @@ typedef struct sysconf83xx { law83xx_t lblaw[4]; /* LBIU local access window */ u8 res2[0x20]; law83xx_t pcilaw[2]; /* PCI local access window */ - u8 res3[0x30]; + u8 res3[0x10]; + law83xx_t pcielaw[2]; /* PCI Express local access window */ + u8 res4[0x10]; law83xx_t ddrlaw[2]; /* DDR local access window */ - u8 res4[0x50]; + u8 res5[0x50]; u32 sgprl; /* System General Purpose Register Low */ u32 sgprh; /* System General Purpose Register High */ u32 spridr; /* System Part and Revision ID Register */ - u8 res5[0x04]; + u8 res6[0x04]; u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x04]; + u8 res7[0x04]; u32 sidcr0; /* System I/O Delay Configuration Register 0 */ u32 sidcr1; /* System I/O Delay Configuration Register 1 */ u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ u32 obir; /* Output Buffer Impedance Register */ - u8 res7[0xCC]; + u8 res8[0xC]; + u32 pecr1; /* PCI Express control register 1 */ + u32 pecr2; /* PCI Express control register 2 */ + u8 res9[0xB8]; } sysconf83xx_t; /* @@ -503,8 +508,110 @@ typedef struct security83xx { /* * PCI Express */ +struct pex_inbound_window { + u32 ar; + u32 tar; + u32 barl; + u32 barh; +}; + +struct pex_outbound_window { + u32 ar; + u32 bar; + u32 tarl; + u32 tarh; +}; + +struct pex_csb_bridge { + u32 pex_csb_ver; + u32 pex_csb_cab; + u32 pex_csb_ctrl; + u8 res0[8]; + u32 pex_dms_dstmr; + u8 res1[4]; + u32 pex_cbs_stat; + u8 res2[0x20]; + u32 pex_csb_obctrl; + u32 pex_csb_obstat; + u8 res3[0x98]; + u32 pex_csb_ibctrl; + u32 pex_csb_ibstat; + u8 res4[0xb8]; + u32 pex_wdma_ctrl; + u32 pex_wdma_addr; + u32 pex_wdma_stat; + u8 res5[0x94]; + u32 pex_rdma_ctrl; + u32 pex_rdma_addr; + u32 pex_rdma_stat; + u8 res6[0xd4]; + u32 pex_ombcr; + u32 pex_ombdr; + u8 res7[0x38]; + u32 pex_imbcr; + u32 pex_imbdr; + u8 res8[0x38]; + u32 pex_int_enb; + u32 pex_int_stat; + u32 pex_int_apio_vec1; + u32 pex_int_apio_vec2; + u8 res9[0x10]; + u32 pex_int_ppio_vec1; + u32 pex_int_ppio_vec2; + u32 pex_int_wdma_vec1; + u32 pex_int_wdma_vec2; + u32 pex_int_rdma_vec1; + u32 pex_int_rdma_vec2; + u32 pex_int_misc_vec; + u8 res10[4]; + u32 pex_int_axi_pio_enb; + u32 pex_int_axi_wdma_enb; + u32 pex_int_axi_rdma_enb; + u32 pex_int_axi_misc_enb; + u32 pex_int_axi_pio_stat; + u32 pex_int_axi_wdma_stat; + u32 pex_int_axi_rdma_stat; + u32 pex_int_axi_misc_stat; + u8 res11[0xa0]; + struct pex_outbound_window pex_outbound_win[4]; + u8 res12[0x100]; + u32 pex_epiwtar0; + u32 pex_epiwtar1; + u32 pex_epiwtar2; + u32 pex_epiwtar3; + u8 res13[0x70]; + struct pex_inbound_window pex_inbound_win[4]; +}; + typedef struct pex83xx { - u8 fixme[0x1000]; + u8 pex_cfg_header[0x404]; + u32 pex_ltssm_stat; + u8 res0[0x30]; + u32 pex_ack_replay_timeout; + u8 res1[4]; + u32 pex_gclk_ratio; + u8 res2[0xc]; + u32 pex_pm_timer; + u32 pex_pme_timeout; + u8 res3[4]; + u32 pex_aspm_req_timer; + u8 res4[0x18]; + u32 pex_ssvid_update; + u8 res5[0x34]; + u32 pex_cfg_ready; + u8 res6[0x24]; + u32 pex_bar_sizel; + u8 res7[4]; + u32 pex_bar_sel; + u8 res8[0x20]; + u32 pex_bar_pf; + u8 res9[0x88]; + u32 pex_pme_to_ack_tor; + u8 res10[0xc]; + u32 pex_ss_intr_mask; + u8 res11[0x25c]; + struct pex_csb_bridge bridge; + u8 res12[0x160]; } pex83xx_t; /* @@ -788,4 +895,6 @@ typedef struct immap { } immap_t; #endif +#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) +#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) #endif /* __IMMAP_83xx__ */ diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e5046bef3..7b97fe0bd 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -58,7 +58,23 @@ typedef struct ccsr_local_ecm { uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ char res19[4]; uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */ + char res19_8a[20]; + uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ + char res19_8b[4]; + uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ + char res19_9a[20]; + uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ + char res19_9b[4]; + uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ + char res19_10a[20]; + uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ + char res19_10b[4]; + uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ + char res19_11a[20]; + uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ + char res19_11b[4]; + uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ + char res20[652]; uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ char res21[12]; uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ @@ -119,7 +135,12 @@ typedef struct ccsr_ddr { uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2672]; + char res8_1b[2456]; + uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ + uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ + uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ + uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ + char res8_1c[200]; uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ char res8_2[512]; @@ -1593,6 +1614,9 @@ typedef struct ccsr_gur { uint gpindr; /* 0xe0050 - General-purpose input data register */ char res5[12]; uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ +#define MPC85xx_PMUXCR_SD_DATA 0x80000000 +#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 +#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 char res6[12]; uint devdisr; /* 0xe0070 - Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index df28c0f2c..470385ffd 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1289,22 +1289,35 @@ typedef struct ccsr_gur { uint powmgtcsr; /* 0xe0080 - Power management status and control register */ char res8[12]; uint mcpsumr; /* 0xe0090 - Machine check summary register */ - char res9[12]; + uint rstrscr; /* 0xe0094 - Reset request status and control register */ + char res9[8]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10a[1880]; + char res10a[8]; + uint rstcr; /* 0xe00b0 - Reset control register */ +#define MPC86xx_RSTCR_HRST_REQ 0x00000002 + char res10b[1868]; uint clkdvdr; /* 0xe0800 - Clock Divide register */ - char res10b[1532]; + char res10c[796]; + uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */ + char res10d[4]; + uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */ + char res10e[724]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ char res12[12]; uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - int res13[57]; - uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ - int res14[6]; - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[216]; + char res13a[224]; + uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */ + char res13b[4]; + uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */ + char res14[24]; + uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ + char res15a[24]; + uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */ + uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */ + char res16[184]; } ccsr_gur_t; /* diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 64cb746b1..4ddad26e8 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -10,6 +10,10 @@ #include <linux/config.h> #include <asm/byteorder.h> +#ifdef CONFIG_ADDR_MAP +#include <addr_map.h> +#endif + #define SIO_CONFIG_RA 0x398 #define SIO_CONFIG_RD 0x399 @@ -287,7 +291,11 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) static inline void * map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { +#ifdef CONFIG_ADDR_MAP + return (void *)(addrmap_phys_to_virt(paddr)); +#else return (void *)((unsigned long)paddr); +#endif } /* @@ -300,7 +308,11 @@ static inline void unmap_physmem(void *vaddr, unsigned long flags) static inline phys_addr_t virt_to_phys(void * vaddr) { +#ifdef CONFIG_ADDR_MAP + return addrmap_virt_to_phys(vaddr); +#else return (phys_addr_t)((unsigned long)vaddr); +#endif } #endif diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8975e6c90..fa92b90c3 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -138,6 +138,10 @@ typedef struct _MMU_context { extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ extern void _tlbia(void); /* invalidate all TLB entries */ +#ifdef CONFIG_ADDR_MAP +extern void init_addr_map(void); +#endif + typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, DBAT0, DBAT1, DBAT2, DBAT3, @@ -153,25 +157,64 @@ extern void print_bats(void); #endif /* __ASSEMBLY__ */ -/* Block size masks */ -#define BL_128K 0x000 -#define BL_256K 0x001 -#define BL_512K 0x003 -#define BL_1M 0x007 -#define BL_2M 0x00F -#define BL_4M 0x01F -#define BL_8M 0x03F -#define BL_16M 0x07F -#define BL_32M 0x0FF -#define BL_64M 0x1FF -#define BL_128M 0x3FF -#define BL_256M 0x7FF +#define BATU_VS 0x00000002 +#define BATU_VP 0x00000001 +#define BATU_INVALID 0x00000000 + +#define BATL_WRITETHROUGH 0x00000040 +#define BATL_CACHEINHIBIT 0x00000020 +#define BATL_MEMCOHERENCE 0x00000010 +#define BATL_GUARDEDSTORAGE 0x00000008 +#define BATL_NO_ACCESS 0x00000000 + +#define BATL_PP_MSK 0x00000003 +#define BATL_PP_00 0x00000000 /* No access */ +#define BATL_PP_01 0x00000001 /* Read-only */ +#define BATL_PP_10 0x00000002 /* Read-write */ +#define BATL_PP_11 0x00000003 + +#define BATL_PP_NO_ACCESS BATL_PP_00 +#define BATL_PP_RO BATL_PP_01 +#define BATL_PP_RW BATL_PP_10 + +/* BAT Block size values */ +#define BATU_BL_128K 0x00000000 +#define BATU_BL_256K 0x00000004 +#define BATU_BL_512K 0x0000000c +#define BATU_BL_1M 0x0000001c +#define BATU_BL_2M 0x0000003c +#define BATU_BL_4M 0x0000007c +#define BATU_BL_8M 0x000000fc +#define BATU_BL_16M 0x000001fc +#define BATU_BL_32M 0x000003fc +#define BATU_BL_64M 0x000007fc +#define BATU_BL_128M 0x00000ffc +#define BATU_BL_256M 0x00001ffc + +/* Block lengths for processors that support extended block length */ +#ifdef HID0_XBSEN +#define BATU_BL_512M 0x00003ffc +#define BATU_BL_1G 0x00007ffc +#define BATU_BL_2G 0x0000fffc +#define BATU_BL_4G 0x0001fffc +#define BATU_BL_MAX BATU_BL_4G +#else +#define BATU_BL_MAX BATU_BL_256M +#endif /* BAT Access Protection */ #define BPP_XX 0x00 /* No access */ #define BPP_RX 0x01 /* Read only */ #define BPP_RW 0x02 /* Read/write */ +/* Macros to get values from BATs, once data is in the BAT register format */ +#define BATU_VALID(x) (x & 0x3) +#define BATU_VADDR(x) (x & 0xfffe0000) +#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \ + | ((x & 0x0e00ULL) << 24) \ + | ((x & 0x04ULL) << 30))) +#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17)) + /* Used to set up SDR1 register */ #define HASH_TABLE_SIZE_64K 0x00010000 #define HASH_TABLE_SIZE_128K 0x00020000 @@ -431,6 +474,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); + extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 98faced36..992a3d221 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -566,6 +566,8 @@ #define SDRAM_RDCC_RSAE_MASK 0x00000001 #define SDRAM_RDCC_RSAE_DISABLE 0x00000001 #define SDRAM_RDCC_RSAE_ENABLE 0x00000000 +#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30) +#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03) /* * SDRAM Read Feedback Delay Control Register diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index e07e5d3be..5b29de0fd 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -451,6 +451,8 @@ #define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ #define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ #define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ @@ -777,6 +779,13 @@ #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +/* e600 core PVR fields */ + +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ + /* Processor Version Numbers */ #define PVR_403GA 0x00200000 @@ -857,7 +866,6 @@ #define PVR_85xx_REV2 (PVR_85xx | 0x0020) #define PVR_86xx 0x80040000 -#define PVR_86xx_REV1 (PVR_86xx | 0x0010) #define PVR_VIRTEX5 0x7ff21912 @@ -949,6 +957,8 @@ #define SVR_8568_E 0x807D00 #define SVR_8572 0x80E000 #define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-sh/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/asm-sh/macro.h b/include/asm-sh/macro.h new file mode 100644 index 000000000..61f792a04 --- /dev/null +++ b/include/asm-sh/macro.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACRO_H__ +#define __MACRO_H__ +#ifdef __ASSEMBLY__ + +.macro write32, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.l r0, @r1 +.endm + +.macro write16, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.w r0, @r1 +.endm + +.macro write8, addr, data + mov.l \addr ,r1 + mov.l \data ,r0 + mov.b r0, @r1 +.endm + +.macro wait_timer, time + mov.l \time ,r3 +1: + nop + tst r3, r3 + bf/s 1b + dt r3 +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __MACRO_H__ */ diff --git a/include/asm-sparc/config.h b/include/asm-sparc/config.h new file mode 100644 index 000000000..049c44eaf --- /dev/null +++ b/include/asm-sparc/config.h @@ -0,0 +1,24 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#endif diff --git a/include/command.h b/include/command.h index a8a153cb0..d7321af92 100644 --- a/include/command.h +++ b/include/command.h @@ -33,6 +33,11 @@ #define NULL 0 #endif +/* Default to a width of 8 characters for help message command width */ +#ifndef CONFIG_SYS_HELP_CMD_WIDTH +#define CONFIG_SYS_HELP_CMD_WIDTH 8 +#endif + #ifndef __ASSEMBLY__ /* * Monitor Command Table @@ -64,6 +69,8 @@ extern cmd_tbl_t __u_boot_cmd_end; cmd_tbl_t *find_cmd(const char *cmd); cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len); +extern void cmd_usage(cmd_tbl_t *cmdtp); + #ifdef CONFIG_AUTO_COMPLETE extern void install_auto_complete(void); extern int cmd_auto_complete(const char *const prompt, char *buf, int *np, int *colp); diff --git a/include/common.h b/include/common.h index 5968036a0..afee1889a 100644 --- a/include/common.h +++ b/include/common.h @@ -597,6 +597,8 @@ ulong video_setmem (ulong); /* lib_$(ARCH)/cache.c */ void flush_cache (unsigned long, unsigned long); +void flush_dcache_range(unsigned long start, unsigned long stop); +void invalidate_dcache_range(unsigned long start, unsigned long stop); /* lib_$(ARCH)/ticks.S */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index d771696fe..205dd1f65 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -33,7 +33,7 @@ #define CONFIG_CMD_ECHO /* echo arguments */ #define CONFIG_CMD_EEPROM /* EEPROM read/write support */ #define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ -#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_FDC /* Floppy Disk Support */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index b556706c7..366760289 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -21,11 +21,13 @@ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ -#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ +#ifndef CONFIG_SYS_NO_FLASH #define CONFIG_CMD_IMLS /* List all found images */ +#endif #define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index a694083d5..2ee4f809d 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -150,7 +149,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 28be8dd62..bced118e3 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -396,10 +396,11 @@ /* * Ethernet configuration * - * Define CONFIG_FEC10MBIT to force FEC at 10MBIT + * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT */ #define CONFIG_MPC5xxx_FEC 1 -#undef CONFIG_FEC_10MBIT +#define CONFIG_MPC5xxx_FEC_MII100 +#undef CONFIG_MPC5xxx_MII10 #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index a44f3e16c..fa9fc2382 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -184,7 +184,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ @@ -219,7 +218,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index d0e246409..40fef88f9 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -157,7 +156,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 328773430..5c88c47b5 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 89ba139af..f032a8d7a 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index e231fa705..2677cfb27 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ @@ -216,6 +215,8 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 2319c5872..aae0d7372 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -92,6 +92,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_BSP #define CONFIG_CMD_EEPROM @@ -132,7 +133,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ @@ -212,6 +212,8 @@ #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index be8c238a0..233320878 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -135,7 +135,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index f1608e145..527c84650 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -86,7 +86,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 884f3fe88..187547d2a 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -117,7 +117,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 729153c2e..85c0e612b 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -411,7 +411,6 @@ int du440_phy_addr(int devnum); * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \ CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS} diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 63a0d3d6a..53bd0d87c 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -170,7 +170,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 36e1f8173..9e9a8a4ab 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -170,7 +170,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 1b766a7dc..201e62aa0 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -114,7 +114,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_IRQ -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h index 1ef806796..d8312384d 100644 --- a/include/configs/FLAGADM.h +++ b/include/configs/FLAGADM.h @@ -83,7 +83,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_LOADB #define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_REGINFO #define CONFIG_CMD_IMMAP #define CONFIG_CMD_NET diff --git a/include/configs/G2000.h b/include/configs/G2000.h index d299044cb..bf9fd8275 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -152,7 +152,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -205,7 +204,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 80e59bb26..ed9a235f6 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -177,7 +177,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -209,7 +208,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index b3c7046fc..0e7d2c010 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -149,7 +148,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index a610ac9c2..fbcbddb40 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -275,7 +275,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_DISABLE_CE(nand) do \ { \ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index f8c94ec2c..5ef0b7798 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -293,14 +293,12 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 -#if defined(CONFIG_LITE5200B) -#define CONFIG_FEC_MII100 1 -#endif /* * GPIO configuration diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 7ddeb550b..50b3ab280 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -82,7 +82,10 @@ #define CONFIG_CMD_MISC #undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADB +#define CONFIG_CMDLINE_EDITING 1 /* enables command line history */ +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC @@ -116,7 +119,7 @@ #define CONFIG_SYS_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */ #define CONFIG_BOOTFILE "u-boot.bin" #ifdef CONFIG_MCFFEC # define CONFIG_NET_RETRY_COUNT 5 @@ -128,16 +131,16 @@ # define CONFIG_OVERWRITE_ETHADDR_ONCE #endif /* FEC_ENET */ -#define CONFIG_HOSTNAME M5235EVB +#define CONFIG_HOSTNAME M5271EVB #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ + "uboot=u-boot.bin\0" \ + "load=tftp $loadaddr $uboot\0" \ "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe2ffff;" \ - "era ffe00000 ffe2ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ + "prog=prot off ffe00000 ffe3ffff;" \ + "era ffe00000 ffe3ffff;" \ + "cp.b $loadaddr ffe00000 $filesize;" \ "save\0" \ "" @@ -159,7 +162,17 @@ #define CONFIG_SYS_MEMTEST_END 0x380000 #define CONFIG_SYS_HZ 1000000 + +/* Clock configuration + * The external oscillator is a 25.000 MHz + * CONFIG_SYS_CLK for ColdFire V2 sets cpu_clk (not bus_clk) + * bus_clk = (cpu_clk/2) (fixed ratio) + * + * If CONFIG_SYS_CLK is changed. the CONFIG_SYS_MCF_SYNCR must be updated to + * match the new clock speed. Max cpu_clk is 150 MHz. + */ #define CONFIG_SYS_CLK 100000000 +#define CONFIG_SYS_MCF_SYNCR (MCF_SYNCR_MFD_4X | MCF_SYNCR_RFD_DIV1) /* * Low Level Configuration Settings @@ -216,7 +229,14 @@ /* Cache Configuration */ #define CONFIG_SYS_CACHELINE_SIZE 16 -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 +/* Chip Select 0 : Boot Flash */ +#define CONFIG_SYS_CS0_BASE 0xFFE00000 +#define CONFIG_SYS_CS0_MASK 0x001F0001 +#define CONFIG_SYS_CS0_CTRL 0x00001980 + +/* Chip Select 1 : External SRAM */ +#define CONFIG_SYS_CS1_BASE 0x30000000 +#define CONFIG_SYS_CS1_MASK 0x00070001 +#define CONFIG_SYS_CS1_CTRL 0x00001900 #endif /* _M5271EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index c207947ff..1f1586a21 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index a1bc32a6d..19916876d 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -215,7 +215,6 @@ # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_MAX_CHIPS 1 # define NAND_ALLOW_ERASE_ALL 1 # define CONFIG_JFFS2_NAND 1 # define CONFIG_JFFS2_DEV "nand0" diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index fc3fa13c7..0ef4ebaec 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -232,7 +232,6 @@ #endif #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 @@ -431,7 +430,7 @@ #define CONFIG_CMD_PCI #if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index add65f03d..9fa91f4f6 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -166,7 +166,7 @@ #undef CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* @@ -223,15 +223,16 @@ */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -308,8 +309,29 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_83XX_GENERIC_PCIE 1 #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -412,7 +434,7 @@ #define CONFIG_CMD_PCI #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c6ac91a53..4eab28571 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -427,7 +427,7 @@ #define CONFIG_CMD_PCI #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index bc56e682a..ea1928eae 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -8,7 +8,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -441,7 +441,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 8e82aac7b..b3c0e2dd5 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -509,7 +509,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fbd2457aa..bdd6b87ad 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -470,7 +470,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f2862c4..f7ebdaad7 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -211,7 +211,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_UPM 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE @@ -377,7 +376,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index d49155fce..a62d805a9 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -271,7 +271,6 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ @@ -320,6 +319,9 @@ #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 +#define CONFIG_SYS_64BIT_VSPRINTF 1 + /* I2C */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ @@ -354,11 +356,32 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #ifdef CONFIG_PCI #ifndef __ASSEMBLY__ extern int board_pci_host_broken(void); #endif #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_83XX_GENERIC_PCIE 1 #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ #define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ @@ -474,7 +497,7 @@ extern int board_pci_host_broken(void); #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif @@ -482,6 +505,18 @@ extern int board_pci_host_broken(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f281c59d3..2e31dd00a 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -481,7 +481,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 532c3df77..bbb448d55 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -34,6 +34,7 @@ #define CONFIG_MPC8536 1 #define CONFIG_MPC8536DS 1 +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -71,6 +72,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ @@ -166,12 +169,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BR0_PRELIM 0xe8001001 -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM 0xe0001001 -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_FLASH_QUIET_TEST @@ -194,8 +198,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#define PIXIS_BASE_PHYS PIXIS_BASE -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ @@ -248,14 +253,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); CONFIG_SYS_NAND_BASE + 0x80000, \ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -272,20 +276,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -356,34 +360,42 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x98000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ @@ -393,10 +405,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_PCI_PNP /* do pci plug-and-play */ /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -409,7 +421,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_PHYS +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT #endif #undef CONFIG_EEPRO100 @@ -423,8 +435,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif @@ -518,6 +530,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index f22b7529d..4aaad55b5 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -308,18 +308,21 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ @@ -420,7 +423,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 5ac1916cb..95ea27583 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -300,7 +300,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 399189c59..fa82fbc6f 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -341,17 +341,21 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 9b1b34cc8..59cfde628 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -263,50 +263,61 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ #define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ +#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 1, tgtid 1, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2,tgtid 2, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 3, direct to uli, tgtid 3, Base address b000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_MEM_BASE2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 CONFIG_SYS_PCIE3_MEM_BASE2 +#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 +#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 +#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 #define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ #if defined(CONFIG_PCI) /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_PHYS*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -336,8 +347,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index e1bd45ef1..95bce9514 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -365,29 +365,36 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif @@ -396,7 +403,8 @@ extern unsigned long get_clock_freq(void); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c92f82d48..6bf09613b 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -339,17 +339,21 @@ extern unsigned long get_clock_freq(void); * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index bf4bd2c1a..a41f50a17 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -300,18 +300,21 @@ #define CONFIG_SYS_I2C_OFFSET 0x3000 /* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ +#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ @@ -454,7 +457,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index da1f45422..58ff52b33 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -322,21 +322,27 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_BASE 0xc0000000 +#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 +#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 #ifdef CONFIG_QE /* diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 37c3f4200..b60b3641f 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -36,6 +36,7 @@ #define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ +#define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ @@ -74,6 +75,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x7fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -84,7 +90,11 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#else #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) @@ -92,6 +102,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) /* DDR Setup */ +#define CONFIG_SYS_DDR_TLB_START 9 +#define CONFIG_VERY_BIG_RAM #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ @@ -168,14 +180,19 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif -#define CONFIG_SYS_BR0_PRELIM 0xe8001001 -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM 0xe0001001 -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -196,8 +213,13 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT +#define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif -#define CONFIG_SYS_BR3_PRELIM (PIXIS_BASE | 0x0801) /* port size 8bit */ +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ @@ -260,20 +282,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000,\ CONFIG_SYS_NAND_BASE + 0xC0000} #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -290,20 +315,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ +#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ +#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V) /* valid */ #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ -#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ +#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ @@ -378,33 +403,66 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ /* controller 3, direct to uli, tgtid 3, Base address 8000 */ -#define CONFIG_SYS_PCIE3_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BASE +#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT /* video */ #define CONFIG_VIDEO @@ -434,8 +492,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BASE + #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS + #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ #endif diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 27517e5b1..1091043c0 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -34,8 +34,6 @@ #define CONFIG_SYS_DIAG_ADDR 0xff800000 #endif -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - /* * virtual address to be used for temporary mappings. There * should be 128k free at this VA. @@ -273,11 +271,13 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x0000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ /* For RTL8139 */ @@ -285,18 +285,18 @@ #define _IO_BASE 0x00000000 /* controller 1, Base address 0xa000 */ -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ /* controller 2, Base Address 0x9000 */ -#define CONFIG_SYS_PCIE2_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 /* reuse mem LAW */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ @@ -364,7 +364,7 @@ #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U @@ -375,7 +375,7 @@ #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U @@ -489,7 +489,7 @@ #define CONFIG_CMD_MII #if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #endif #if defined(CONFIG_PCI) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 5a832961c..9d661010d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -39,13 +39,12 @@ #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ +#define CONFIG_ADDR_MAP 1 /* Use addr map */ #ifdef RUN_DIAG #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - /* * virtual address to be used for temporary mappings. There * should be 128k free at this VA. @@ -70,6 +69,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ +#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ #define CONFIG_ALTIVEC 1 @@ -186,7 +186,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | 0x00001001) /* port size 16bit */ @@ -331,14 +331,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 + +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT #endif #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) @@ -348,12 +351,23 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) #define _IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \ +#ifdef CONFIG_PHYS_64BIT +/* + * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * This will increase the amount of PCI address space available for + * for mapping RAM. + */ +#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#else +#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ + + CONFIG_SYS_PCI1_MEM_SIZE) +#endif +#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ + CONFIG_SYS_PCI1_MEM_SIZE) #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ + CONFIG_SYS_PCI1_IO_SIZE) #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ @@ -501,7 +515,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) @@ -635,7 +649,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_REGINFO #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #endif #if defined(CONFIG_PCI) diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 31b9f038b..79c20696f 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -85,7 +85,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index b03612797..10210f040 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -92,7 +92,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_BOOTD #define CONFIG_CMD_RUN diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index e171f76b5..c9589bd87 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 423ca71c8..0b97f0ce6 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -250,7 +250,6 @@ * NAND flash support */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 34de94797..2d04d8925 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -514,7 +514,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 004b3c8a4..34fdba59c 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -633,7 +633,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD3, CLE = PD4, CE = PD5, F_RY_BY = PC13 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 70995faed..4a2702791 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -515,7 +515,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PD17, CLE = PE18, CE = PE20, F_RY_BY = PE31 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index 87c920f42..f97bdcb72 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -411,7 +411,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_DISABLE_CE(nand) \ do { \ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 32814d49f..2591f1ded 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 58e9328e4..13d6e0496 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -105,7 +105,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PATI.h b/include/configs/PATI.h index 9d80ce413..88e952895 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -57,7 +57,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_FLASH #define CONFIG_CMD_LOADS -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_REGINFO #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index d0a37d7bc..4e397990c 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 481e3354b..831a60d9a 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -137,7 +137,7 @@ */ #define CONFIG_CMD_BDI #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 5b1fcff9c..522349f78 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -177,7 +177,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IRQ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 11ce0080f..7f2337bac 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -138,7 +138,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -173,7 +172,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index e250e0338..ff73ef9a2 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -279,10 +279,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 41e290d0b..3f943aa43 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -331,7 +331,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 6b4e2dd42..43c2873e3 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -330,7 +330,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 8d07d7705..c598d00cf 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -21,16 +21,11 @@ * MA 02111-1307 USA */ -/* - * board/config.h - configuration options, board specific - */ - #ifndef __CONFIG_H #define __CONFIG_H /* * High Level Configuration Options - * (easy to change) */ #define CONFIG_405GP 1 /* This is a PPC405 CPU */ @@ -45,13 +40,22 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ -#undef CONFIG_BOOTARGS -#undef CONFIG_BOOTCOMMAND +/* Only interrupt boot if space is pressed. */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + +#undef CONFIG_BOOTARGS +#undef CONFIG_BOOTCOMMAND -#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 @@ -59,11 +63,8 @@ #define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ - -#define CONFIG_NETCONSOLE /* include NetConsole support */ - +#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ /* * BOOTP options @@ -73,7 +74,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - /* * Command line configuration. */ @@ -91,250 +91,241 @@ #define CONFIG_CMD_UNIVERSE #define CONFIG_CMD_EEPROM - #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ -#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ +#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */ +#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER +#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#ifdef CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #endif #if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */ -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ -#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ +#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ -#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ +#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ -#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ -#define CONFIG_SYS_BASE_BAUD 691200 +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ +#define CONFIG_SYS_BASE_BAUD 806400 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CONFIG_SYS_RX_ETH_BUFFER 16 -/*----------------------------------------------------------------------- +/* * PCI stuff - *----------------------------------------------------------------------- */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ +#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ +#define PCI_HOST_FORCE 1 /* configure as pci host */ +#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + /* resource configuration */ -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ +#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ - -#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#if 1 -#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ -#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ -#else /* old mapping */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ -#endif -/*----------------------------------------------------------------------- +#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */ + +#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ +#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ +#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ + +/* * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ + +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ -/*----------------------------------------------------------------------- +/* * FLASH organization */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT } -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT} +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ /* - * JFFS2 partitions - second bank contains u-boot - * - */ -/* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x01b00000 -#define CONFIG_JFFS2_PART_OFFSET 0x00400000 - -/* mtdparts command line support */ -/* Note: fake mtd_id used, no linux mtd map file */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=pmc405-0" -#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)" -*/ - -/*----------------------------------------------------------------------- * Environment Variable setup */ #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ -#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ - /* total size of a CAT24WC16 is 2048 bytes */ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ +/* environment starts at the beginning of the EEPROM */ +#define CONFIG_ENV_OFFSET 0x000 +#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ -/*----------------------------------------------------------------------- +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ + +/* * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* mask of address bits that overflow into the "EEPROM chip address" */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +/* mask of address bits that overflow into the "EEPROM chip address" */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ /* 16 byte page write mode using*/ - /* last 4 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + /* last 4 bits of the address */ -/*----------------------------------------------------------------------- +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +/* * External Bus Controller (EBC) Setup */ -#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ -#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ -#define RTC_BA 0xF0000500 /* RTC Base Address */ -#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ +#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ +#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ +#define CAN_BA 0xF0000000 /* CAN Base Addres */ +#define RTC_BA 0xF0000500 /* RTC Base Address */ +#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ -/* Memory Bank 0 (Flash Bank 0) initialization */ +/* Memory Bank 0 (Flash Bank 0) initialization */ #define CONFIG_SYS_EBC_PB0AP 0x92015480 -#define CONFIG_SYS_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/ +/* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ +#define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000) -/* Memory Bank 1 (Flash Bank 1) initialization */ +/* Memory Bank 1 (Flash Bank 1) initialization */ #define CONFIG_SYS_EBC_PB1AP 0x92015480 -#define CONFIG_SYS_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ +/* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ +#define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000) -/* Memory Bank 2 (CAN0, 1, RTC) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +/* Memory Bank 2 (CAN0, 1, RTC) initialization */ +/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CONFIG_SYS_EBC_PB2AP 0x03000440 +/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000) /* Memory Bank 3 -> unused */ -/* Memory Bank 4 (NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ -#define CONFIG_SYS_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +/* Memory Bank 4 (NVRAM) initialization */ +/* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ +#define CONFIG_SYS_EBC_PB4AP 0x03000440 +/* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ +#define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000) -/*----------------------------------------------------------------------- +/* * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ +#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */ /* FPGA program pin configuration */ -#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ -#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */ -#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */ -#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ -#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */ +#define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ +#define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ +#define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */ +#define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ +#define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ +/* pass Ethernet MAC to VxWorks */ +#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 -/*----------------------------------------------------------------------- +/* * GPIOs */ -#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO24 */ -#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ -#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ -#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ -#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ +#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ +#define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ +#define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ +#define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ +#define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ +#define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ -/*----------------------------------------------------------------------- +/* * Definitions for initial stack pointer and data area (in data cache) */ -/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +/* use on chip memory (OCM) for temperary stack until sdram is tested */ #define CONFIG_SYS_TEMP_STACK_OCM 1 /* On Chip Memory location */ #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +/* inside of SDRAM */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR + +/* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE + +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \ + CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /* @@ -342,7 +333,10 @@ * * Boot Flags */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index f9f10021b..fc48bc1db 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -505,7 +505,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ #define CONFIG_SYS_NAND_QUIET_TEST 1 diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 2c0774fea..06c11e69b 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -61,7 +61,7 @@ #undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 09a96417f..d2eae1d7f 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -192,7 +192,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ @@ -224,8 +223,6 @@ #define NAND_BIG_DELAY_US 25 #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 - #define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */ #define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */ #define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */ diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 4ac31b1c0..c1416cb91 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -211,7 +211,7 @@ #define CONFIG_CMD_BOOTD #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMMAP diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 65f41e6a7..de74fee76 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -211,7 +211,7 @@ #define CONFIG_CMD_BOOTD #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_DATE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMMAP diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 34196319c..7239f8409 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -382,7 +382,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h new file mode 100644 index 000000000..b939cfa79 --- /dev/null +++ b/include/configs/SIMPC8313.h @@ -0,0 +1,547 @@ +/* + * Copyright (C) Sheldon Instruments, Inc. 2008 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * simpc8313 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_NAND_U_BOOT + +#define CONFIG_E300 1 +#define CONFIG_MPC83XX 1 +#define CONFIG_MPC831X 1 +#define CONFIG_MPC8313 1 + +#define CONFIG_PCI +#define CONFIG_83XX_GENERIC_PCI + +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + * + * TSEC1 is Marvell PHY 88E1118 + */ + +#define CONFIG_SYS_33MHZ + +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ + +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +#define CONFIG_SYS_IMMR 0xE0000000 + +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00001000 +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ + +/* + * Device configurations + */ +#define CONFIG_TSEC1 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE + +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (512 << 20) + +#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) + /* 0x73000002 TODO ODR & DRN ? */ + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#if !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ + +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Local Bus LCRR and LBCR regs + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ + | (0xFF << LBCR_BMT_SHIFT) \ + | 0xF ) /* 0x0004ff0f */ + +#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ + +/* drivers/mtd/nand/nand.c */ +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0xE2800000 +#endif + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 + +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 + +#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ + +#ifdef CONFIG_NAND_SP +#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define NAND_CACHE_PAGES 32 +#elif defined(CONFIG_NAND_LP) +#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ +#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ +#define NAND_CACHE_PAGES 64 +#else +#error Page size of NAND not defined. +#endif /* CONFIG_NAND_SP */ + +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE + +#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM +#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM +#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM + +/* + * JFFS2 configuration + */ +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0" + +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=nand0" +#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)" + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#ifdef CONFIG_NAND_SPL +#define CONFIG_NS16550_MIN_FUNCTIONS +#endif + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 +#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE +#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ + +/* + * TSEC + */ +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ + +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ + +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x0 +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 +#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + + +/* Options are: TSEC[0-1] */ +#define CONFIG_ETHPRIME "TSEC1" + +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Environment + */ +#if defined(CONFIG_NAND_U_BOOT) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET (768 * 1024) + #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) + #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) +#elif !defined(CONFIG_SYS_RAMBOOT) + #define CONFIG_ENV_IS_IN_FLASH 1 + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) + #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ + #define CONFIG_ENV_SIZE 0x2000 + +/* Address and size of Redundant Environment Sector */ +#else + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_FLASH + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 + +#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT) + #undef CONFIG_CMD_SAVEENV + #undef CONFIG_CMD_LOADS +#endif + +#define CONFIG_CMDLINE_EDITING 1 + + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +#define CONFIG_SYS_PBSIZE ( CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) \ + + 16 ) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ + +#define CONFIG_SYS_HRCW_LOW ( HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \ + | 0x20000000 /* reserved */ \ + | HRCWL_DDR_TO_SCB_CLK_2X1 \ + | HRCWL_CSB_TO_CLKIN_4X1 \ + | HRCWL_CORE_TO_CSB_2_5X1 ) + +#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4) + +#define CONFIG_SYS_HRCW_HIGH_BASE ( HRCWH_PCI_HOST \ + | HRCWH_PCI1_ARBITER_ENABLE \ + | HRCWH_CORE_ENABLE \ + | HRCWH_BOOTSEQ_DISABLE \ + | HRCWH_SW_WATCHDOG_DISABLE \ + | HRCWH_TSEC1M_IN_RGMII \ + | HRCWH_TSEC2M_IN_RGMII \ + | HRCWH_BIG_ENDIAN \ + | HRCWH_LALE_NORMAL ) + +#ifdef CONFIG_NAND_LP +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_LP_8BIT \ + | HRCWH_RL_EXT_NAND) +#else +#define CONFIG_SYS_HRCW_HIGH ( CONFIG_SYS_HRCW_HIGH_BASE \ + | HRCWH_FROM_0XFFF00100 \ + | HRCWH_ROM_LOC_NAND_SP_8BIT \ + | HRCWH_RL_EXT_NAND ) +#endif + +/* System IO Config */ +#define CONFIG_SYS_SICRH ( SICRH_ETSEC2_B \ + | SICRH_ETSEC2_C \ + | SICRH_ETSEC2_D \ + | SICRH_ETSEC2_E \ + | SICRH_ETSEC2_F \ + | SICRH_ETSEC2_G \ + | SICRH_TSOBI1 \ + | SICRH_TSOBI2 ) +#define CONFIG_SYS_SICRL (SICRL_USBDR \ + | SICRL_ETSEC2_A ) + +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ + | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) + +#define CONFIG_SYS_HID2 HID2_HBE + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR @ 0x00000000 */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) +#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI @ 0x80000000 */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) + +/* PCI2 not supported on 8313 */ +#define CONFIG_SYS_IBAT4L (0) +#define CONFIG_SYS_IBAT4U (0) + +/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) + +/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10) +#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) + +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) + +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U +#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U +#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_NETDEV eth1 + +#define CONFIG_HOSTNAME simpc8313 +#define CONFIG_ROOTPATH /tftpboot/ +#define CONFIG_BOOTFILE /tftpboot/uImage +#define CONFIG_UBOOTPATH u-boot-nand.bin /* U-Boot image on TFTP server */ +#define CONFIG_FDTFILE simpc8313.dtb + +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 5 /* 5 second delay */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;bootm $loadaddr - $fdtaddr" + +#define XMK_STR(x) #x +#define MK_STR(x) XMK_STR(x) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ + "ethprime=TSEC1\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "fdtaddr=ae0000\0" \ + "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ + "console=ttyS0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "load_uboot=tftp 100000 u-boot-nand.bin\0" \ + "burn_uboot=nand erase u-boot 80000; " \ + "nand write 100000 u-boot $filesize\0" \ + "update_uboot=run load_uboot;run burn_uboot\0" \ + "mtdids=nand0=nand0\0" \ + "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \ + "console=ttyS0,115200\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setbootargs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#undef MK_STR +#undef XMK_STR + +#endif /* __CONFIG_H */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 920134699..4181a400e 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -67,6 +67,7 @@ #define CONFIG_CMD_IDE +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FLASH diff --git a/include/configs/SX1.h b/include/configs/SX1.h index fd1a3bdd5..78c5152e6 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -116,7 +116,9 @@ #include <configs/omap1510.h> #define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" +#ifdef CONFIG_STDOUT_USBTTY #define CONFIG_PREBOOT "setenv stdout usbtty;setenv stdin usbtty" +#endif /* * Miscellaneous configurable options @@ -167,15 +169,19 @@ /*----------------------------------------------------------------------- * FLASH and environment organization + * V1 + * PHYS_FLASH_SIZE_1 (16 << 10) 16 MB + * PHYS_FLASH_SIZE_2 (8 << 10) 8 MB + * V2 only 1 flash + * PHYS_FLASH_SIZE_1 (32 << 10) 32 MB */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define PHYS_FLASH_SIZE (16 << 10) /* 16 MB */ #define PHYS_FLASH_SECT_SIZE (128*1024) /* Size of a sector (128kB) */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT (256) /* max number of sectors on one chip */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SECT_SIZE) /* addr of environment */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ #define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE /* Reserve 1 sector */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE } +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, PHYS_FLASH_2 } /*----------------------------------------------------------------------- * FLASH driver setup diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index 7fc455b8c..9857bf605 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -206,7 +206,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* DFBUSY is available on Port C, bit 12; 0 if busy */ #define NAND_WAIT_READY(nand) \ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 60102469c..b42d3d944 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -344,10 +344,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 046948e74..50197f4c5 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -312,7 +312,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ +#define CONFIG_MPC5xxx_FEC_MII10 /* Workaround for FEC 100Mbit problem */ #define CONFIG_PHY_ADDR 0x1f #define CONFIG_PHY_TYPE 0x79c874 /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index db7f51d4e..6850eba15 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -507,10 +507,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 223269ff0..8934d51bf 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -123,6 +123,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index aed5d5bab..fd4157343 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -121,6 +121,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index ac9c94e68..582e67025 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -81,8 +81,8 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "bootfile=tqm8260/uImage\0" \ - "kernel_addr=40080000\0" \ - "ramdisk_addr=40200000\0" \ + "kernel_addr=400C0000\0" \ + "ramdisk_addr=40240000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 1915a73a6..9cac696b9 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -424,7 +424,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \ CONFIG_SYS_NAND1_BASE, \ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 796030d06..e126dc38c 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -340,7 +340,7 @@ extern int tqm834x_num_flash_banks; #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 4aa8db824..77eb5a96d 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -112,6 +112,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index ce5dcc190..bb8825b9e 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -110,6 +110,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 012e20396..2ccbaf895 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -116,6 +116,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 84889ea17..8a6518358 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -149,6 +149,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_EEPROM #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6d205a7a1..3b2272c23 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -41,14 +41,21 @@ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) +#define CONFIG_TQM8548 +#endif + #define CONFIG_PCI +#ifndef CONFIG_TQM8548_AG +#define CONFIG_PCI1 /* PCI/PCI-X controller */ +#endif +#ifdef CONFIG_TQM8548 +#define CONFIG_PCIE1 /* PCI Express interface */ +#endif + #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ -#ifdef CONFIG_TQM8548 -#define CONFIG_PCI1 -#define CONFIG_PCIE1 #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ -#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -70,7 +77,9 @@ * Warning: NAND support will likely increase the U-Boot image size * to more than 256 KB. Please adjust TEXT_BASE if necessary. */ -#undef CONFIG_NAND +#ifdef CONFIG_TQM8548_BE +#define CONFIG_NAND +#endif /* * MPC8540 and MPC8548 don't have CPM module @@ -81,7 +90,9 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#undef CONFIG_CAN_DRIVER /* CAN Driver support */ +#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE) +#define CONFIG_CAN_DRIVER /* CAN Driver support */ +#endif /* * sysclk for MPC85xx @@ -135,6 +146,9 @@ */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#ifdef CONFIG_TQM8548_AG +#define CONFIG_VERY_BIG_RAM +#endif #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 @@ -363,7 +377,6 @@ #define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST) #define CONFIG_SYS_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #if (CONFIG_SYS_MAX_NAND_DEVICE == 1) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } @@ -605,7 +618,9 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#ifndef CONFIG_TQM8548_AG #define CONFIG_CMD_DATE +#endif #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DTT #define CONFIG_CMD_MII diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index b67cdcd89..8bd1fe062 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -116,6 +116,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 46852dd11..ad2c71ce0 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -116,6 +116,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index a7fcb1aaf..0a5180e4f 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -119,6 +119,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index bcf37d911..ee6980c81 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -119,6 +119,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 87dc2649f..421a2d868 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -160,6 +160,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 942bbf604..4c80bad13 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -157,6 +157,7 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_MII diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 75d1985ff..9a7584807 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -268,6 +268,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_SEVENWIRE /* dummy, 7-wire FEC does not have phy address */ #define CONFIG_PHY_ADDR 0x00 diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 0bc2f6889..d9bcf6b7a 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -36,7 +36,6 @@ #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ @@ -264,7 +263,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_WAIT_READY(nand) NF_WaitRB() diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 10ef620d8..38a1d0dec 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -134,7 +134,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -159,7 +158,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 90efc6d81..db00c652f 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -121,7 +121,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 982f8d801..5f9a17f3d 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -154,7 +154,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_IMLS diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index 01cdf3a6f..99188bc34 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_UART1_CONSOLE /* define for uart1 as console */ @@ -147,7 +146,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h new file mode 100644 index 000000000..370aae1c4 --- /dev/null +++ b/include/configs/XPEDITE5200.h @@ -0,0 +1,546 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2004-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5200 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 1 +#define CONFIG_XPEDITE5200 1 +#define CONFIG_SYS_BOARD_NAME "XPedite5200" +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI1 1 /* PCI controller 1 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS 0x54 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 2 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable + * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_NAND_ACTL +#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ +#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ +#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ +#define CONFIG_SYS_NAND_ACTL_DELAY 25 + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 +#define CONFIG_SYS_FLASH_BASE2 0xf8000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xfbf40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_8) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + BR_PS_8 | \ + BR_V) + +/* NAND flash on CS2 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ + OR_GPCM_BCTLD | \ + OR_GPCM_CSNT | \ + OR_GPCM_ACS_DIV4 | \ + OR_GPCM_SCY_4 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR) + +/* NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ + BR_PS_8 | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x4000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* I2C EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* PCA957 @ 0x18 */ +#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 +#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 +#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 +#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 +#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 +#define CONFIG_SYS_PCA953X_FLASH_WP 0x20 +#define CONFIG_SYS_PCA953X_MONARCH 0x40 +#define CONFIG_SYS_PCA953X_EREADY 0x80 + +/* PCA957 @ 0x19 */ +#define CONFIG_SYS_PCA953X_P14_IO0 0x01 +#define CONFIG_SYS_PCA953X_P14_IO1 0x02 +#define CONFIG_SYS_PCA953X_P14_IO2 0x04 +#define CONFIG_SYS_PCA953X_P14_IO3 0x08 +#define CONFIG_SYS_PCA953X_P14_IO4 0x10 +#define CONFIG_SYS_PCA953X_P14_IO5 0x20 +#define CONFIG_SYS_PCA953X_P14_IO6 0x40 +#define CONFIG_SYS_PCA953X_P14_IO7 0x80 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define TSEC3_FLAGS TSEC_GIGABIT +#define TSEC3_PHY_ADDR 3 +#define TSEC3_PHYIDX 0 +#define CONFIG_HAS_ETH2 + +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" +#define TSEC4_FLAGS TSEC_GIGABIT +#define TSEC4_PHY_ADDR 4 +#define TSEC4_PHYIDX 0 +#define CONFIG_HAS_ETH3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY + +/* + * Command configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * fc000000 - feefffff Pri OS Use/Filesystem (47MB) + * + * fbf80000 - fbffffff Sec U-Boot (512 KB) + * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) + * fbf00000 - fbf3ffff Sec FDT (256KB) + * faf00000 - fbefffff Sec OS image (16MB) + * f8000000 - faefffff Sec OS Use/Filesystem (47MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5200\0" \ + "fdtfile=/home/user/xpedite5200.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h new file mode 100644 index 000000000..a353a14e7 --- /dev/null +++ b/include/configs/XPEDITE5370.h @@ -0,0 +1,589 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * Copyright 2007-2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * xpedite5370 board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_BOOKE 1 /* BOOKE */ +#define CONFIG_E500 1 /* BOOKE e500 family */ +#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8572 1 +#define CONFIG_XPEDITE5370 1 +#define CONFIG_SYS_BOARD_NAME "XPedite5370" +#define CONFIG_NUM_CPUS 2 /* 2 Cores */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ +#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ + +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ + +/* + * DDR config + */ +#define CONFIG_FSL_DDR2 +#undef CONFIG_FSL_DDR_INTERACTIVE +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#define CONFIG_DDR_SPD +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ +#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ +#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ +#define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_VERY_BIG_RAM + +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +extern unsigned long get_board_ddr_clk(unsigned long dummy); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ENABLE_36BIT_PHYS 1 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) + +/* + * Diagnostics + */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END 0x20000000 + +/* + * Memory map + * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable + * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable + * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable + * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable + * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable + * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable + * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable + * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable + * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable + */ + +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) + +/* + * NAND flash configuration + */ +#define CONFIG_SYS_NAND_BASE 0xef800000 +#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ + +/* + * NOR flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +#define CONFIG_SYS_FLASH_BASE2 0xf0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ + {0xf7f40000, 0xc0000} } +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +/* + * Chip select configuration + */ +/* NOR Flash 0 on CS0 */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ + OR_GPCM_CSNT | \ + OR_GPCM_XACS | \ + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_8 | \ + OR_GPCM_TRLX | \ + OR_GPCM_EHTR | \ + OR_GPCM_EAD) + +/* NOR Flash 1 on CS1 */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ + BR_PS_16 | \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM + +/* NAND flash on CS2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ + (2<<BR_DECC_SHIFT) | \ + BR_PS_8 | \ + BR_MS_FCM | \ + BR_V) + +/* NAND flash on CS2 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ + OR_FCM_PGS | \ + OR_FCM_CSCT | \ + OR_FCM_CST | \ + OR_FCM_CHT | \ + OR_FCM_SCY_1 | \ + OR_FCM_TRLX | \ + OR_FCM_EHTR) + +/* NAND flash on CS3 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ + (2<<BR_DECC_SHIFT) | \ + BR_PS_8 | \ + BR_MS_FCM | \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM + +/* + * Use L1 as initial stack + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Use the HUSH parser + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * I2C + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE + +/* PEX8518 slave I2C interface */ +#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 + +/* I2C DS1631 temperature sensor */ +#define CONFIG_SYS_I2C_DS1621_ADDR 0x48 +#define CONFIG_DTT_DS1621 +#define CONFIG_DTT_SENSORS { 0 } + +/* I2C EEPROM - AT24C128B */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +/* I2C RTC */ +#define CONFIG_RTC_M41T11 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_M41T11_BASE_YEAR 2000 + +/* GPIO/EEPROM/SRAM */ +#define CONFIG_DS4510 +#define CONFIG_SYS_I2C_DS4510_ADDR 0x51 + +/* GPIO */ +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 +#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c +#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e +#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f +#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 + +/* + * PU = pulled high, PD = pulled low + * I = input, O = output, IO = input/output + */ +/* PCA9557 @ 0x18*/ +#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ +#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ +#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ +#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */ +#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */ + +/* PCA9557 @ 0x1c*/ +#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ +#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */ +#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ +#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ +#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ +#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ +#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ +#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ + +/* PCA9557 @ 0x1e*/ +#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ +#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */ +#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */ + +/* PCA9557 @ 0x1f */ +#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */ +#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */ +#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */ + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* PCIE1 - VPX P1 */ +#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ + +/* PCIE2 - PEX8518 */ +#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ + +/* + * Networking options + */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_TSEC_TBI +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_ETHPRIME "eTSEC2" + +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC1_PHY_ADDR 1 +#define TSEC1_PHYIDX 0 +#define CONFIG_HAS_ETH0 + +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_PHY_ADDR 2 +#define TSEC2_PHYIDX 0 +#define CONFIG_HAS_ETH1 + +/* + * Command configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DS4510 +#define CONFIG_CMD_DS4510_INFO +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ +#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */ +#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ + +/* + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ +#define CONFIG_ENV_SIZE 0x8000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) + +/* + * Flash memory map: + * fff80000 - ffffffff Pri U-Boot (512 KB) + * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) + * fff00000 - fff3ffff Pri FDT (256KB) + * fef00000 - ffefffff Pri OS image (16MB) + * f8000000 - feefffff Pri OS Use/Filesystem (111MB) + * + * f7f80000 - f7ffffff Sec U-Boot (512 KB) + * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB) + * f7f00000 - f7f3ffff Sec FDT (256KB) + * f6f00000 - f7efffff Sec OS image (16MB) + * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) + */ +#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000) +#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000) +#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000) +#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000) +#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000) +#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000) + +#define CONFIG_PROG_UBOOT1 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_UBOOT2 \ + "$download_cmd $loadaddr $ubootfile; " \ + "if test $? -eq 0; then " \ + "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ + "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ + "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ + "if test $? -ne 0; then " \ + "echo PROGRAM FAILED; " \ + "else; " \ + "echo PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_BOOT_OS_NET \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "if test -n $fdtaddr; then " \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "bootm $osaddr - $fdtaddr; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi; " \ + "else; " \ + "bootm $osaddr; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS1 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_OS2 \ + "$download_cmd $osaddr $osfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ + "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo OS PROGRAM FAILED; " \ + "else; " \ + "echo OS PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo OS DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT1 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_PROG_FDT2 \ + "$download_cmd $fdtaddr $fdtfile; " \ + "if test $? -eq 0; then " \ + "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ + "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ + "if test $? -ne 0; then " \ + "echo FDT PROGRAM FAILED; " \ + "else; " \ + "echo FDT PROGRAM SUCCEEDED; " \ + "fi; " \ + "else; " \ + "echo FDT DOWNLOAD FAILED; " \ + "fi;" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=yes\0" \ + "download_cmd=tftp\0" \ + "console_args=console=ttyS0,115200\0" \ + "root_args=root=/dev/nfs rw\0" \ + "misc_args=ip=on\0" \ + "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ + "bootfile=/home/user/file\0" \ + "osfile=/home/user/uImage-XPedite5370\0" \ + "fdtfile=/home/user/xpedite5370.dtb\0" \ + "ubootfile=/home/user/u-boot.bin\0" \ + "fdtaddr=c00000\0" \ + "osaddr=0x1000000\0" \ + "loadaddr=0x1000000\0" \ + "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ + "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ + "prog_os1="CONFIG_PROG_OS1"\0" \ + "prog_os2="CONFIG_PROG_OS2"\0" \ + "prog_fdt1="CONFIG_PROG_FDT1"\0" \ + "prog_fdt2="CONFIG_PROG_FDT2"\0" \ + "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ + "bootcmd_flash1=run set_bootargs; " \ + "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ + "bootcmd_flash2=run set_bootargs; " \ + "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ + "bootcmd=run bootcmd_flash1\0" +#endif /* __CONFIG_H */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 52ccdb5b9..9ffd86b1a 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -262,7 +262,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/actux1.h b/include/configs/actux1.h index a3b04b1af..adbc39951 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -39,6 +39,7 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_IXP_SERIAL #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 @@ -172,8 +173,6 @@ /* include IXP4xx NPE support */ #define CONFIG_IXP4XX_NPE 1 -/* use separate flash sector with ucode images */ -#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ #define CONFIG_PHY_ADDR 0 @@ -208,6 +207,7 @@ #define CONFIG_SYS_USE_PPCENV 1 #define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ "rootaddr=50170000\0" \ diff --git a/include/configs/actux2.h b/include/configs/actux2.h index 7e6e8f282..4c579ebe2 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -32,6 +32,7 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_IXP_SERIAL #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 @@ -147,8 +148,6 @@ /* include IXP4xx NPE support */ #define CONFIG_IXP4XX_NPE 1 -/* use separate flash sector with ucode images */ -#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ #define CONFIG_PHY_ADDR 0x00 @@ -185,6 +184,7 @@ #define CONFIG_SYS_USE_PPCENV 1 #define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ "rootaddr=50170000\0" \ diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 3f42ed497..694f52254 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -32,6 +32,7 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_IXP_SERIAL #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART2 #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 @@ -146,8 +147,6 @@ /* include IXP4xx NPE support */ #define CONFIG_IXP4XX_NPE 1 -/* use separate flash sector with ucode images */ -#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ @@ -185,6 +184,7 @@ #define CONFIG_SYS_USE_PPCENV 1 #define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=50040000\0" \ "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ "kerneladdr=50050000\0" \ "rootaddr=50170000\0" \ diff --git a/include/configs/actux4.h b/include/configs/actux4.h index 3cf1b2058..cdc995672 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -32,6 +32,7 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_IXP_SERIAL #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 @@ -149,8 +150,6 @@ /* include IXP4xx NPE support */ #define CONFIG_IXP4XX_NPE 1 -/* use separate flash sector with ucode images */ -#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x51000000 #define CONFIG_NET_MULTI 1 /* NPE0 PHY address */ @@ -181,6 +180,7 @@ #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) #define CONFIG_EXTRA_ENV_SETTINGS \ + "npe_ucode=51000000\0" \ "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ "kerneladdr=51020000\0" \ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index bb3525f17..8fda3f29f 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -47,6 +47,7 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ +#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ /* video */ #undef CONFIG_VIDEO @@ -294,6 +295,11 @@ #endif /* + * IIM - IC Identification Module + */ +#undef CONFIG_IIM + +/* * EEPROM configuration */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16-bit EEPROM address */ @@ -348,11 +354,20 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_EEPROM #define CONFIG_CMD_DATE +#undef CONFIG_CMD_FUSE +#define CONFIG_CMD_IDE +#define CONFIG_CMD_EXT2 #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif +#if defined(CONFIG_CMD_IDE) +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif /* defined(CONFIG_CMD_IDE) */ + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -489,4 +504,48 @@ #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@80000000/serial@11300" +/*----------------------------------------------------------------------- + * IDE/ATA stuff + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for IDE not supported */ + +#define CONFIG_IDE_RESET /* reset for IDE supported */ +#define CONFIG_IDE_PREINIT + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 +#define CONFIG_SYS_ATA_BASE_ADDR MPC512X_PATA + +/* Offset for data I/O RefMan MPC5121EE Table 28-10 */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define ATA_BASE_ADDR MPC512X_PATA + +/* + * Control register bit definitions + */ +#define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 +#define FSL_ATA_CTRL_ATA_RST_B 0x40000000 +#define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 +#define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 +#define FSL_ATA_CTRL_DMA_PENDING 0x08000000 +#define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 +#define FSL_ATA_CTRL_DMA_WRITE 0x02000000 +#define FSL_ATA_CTRL_IORDY_EN 0x01000000 + #endif /* __CONFIG_H */ diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index d63a1a07f..9eed3423c 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -97,7 +97,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 @@ -115,7 +114,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 7ce820518..e6248e9df 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -335,7 +335,6 @@ * NAND-FLASH stuff *-----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE + 0, CONFIG_SYS_NAND_BASE + 2, \ CONFIG_SYS_NAND_BASE + 4, CONFIG_SYS_NAND_BASE + 6 } diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h index 9134ad1dc..c6d77e3ae 100644 --- a/include/configs/ap325rxa.h +++ b/include/configs/ap325rxa.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_NFS #define CONFIG_CMD_SDRAM -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h index b2baf1b34..01da99b82 100644 --- a/include/configs/at91cap9adk.h +++ b/include/configs/at91cap9adk.h @@ -118,7 +118,6 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 @@ -132,7 +131,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 746f0ef10..5a980d353 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ @@ -129,7 +129,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 15389296f..2f1a41f64 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -100,7 +100,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 @@ -117,7 +116,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 0016b4fbf..ebecfa409 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -111,7 +111,6 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 @@ -130,7 +129,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index d9ebc87ae..09b871a5e 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -123,7 +123,6 @@ #endif /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 @@ -137,7 +136,6 @@ /* USB */ #define CONFIG_USB_OHCI_NEW 1 -#define LITTLEENDIAN 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 35fefc421..5bef1fe97 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -104,7 +104,6 @@ #define CONFIG_SYS_NO_FLASH 1 /* NAND flash */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index f3ffe1cca..8c4127da0 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -197,7 +197,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index e87173717..48c0252e4 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -198,7 +198,7 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SLAVE 0 #define CONFIG_SYS_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 5ad99a2fd..ee41c7e78 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -300,7 +300,7 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SLAVE 0 #endif /* CONFIG_SOFT_I2C */ /* diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 1b54d3b88..f6399a9f5 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -278,7 +278,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define BFIN_NAND_READY PF3 #define NAND_WAIT_READY(nand) \ @@ -306,13 +305,11 @@ /* * I2C settings - * By default PF1 is used as SDA and PF0 as SCL on the Stamp board */ -/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */ -#define CONFIG_HARD_I2C 1 /* I2C TWI */ -#if defined CONFIG_HARD_I2C -#define CONFIG_TWICLK_KHZ 50 -#endif +#define CONFIG_HARD_I2C 1 +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 #define CONFIG_EBIU_SDRRC_VAL 0x306 #define CONFIG_EBIU_SDGCTL_VAL 0x91114d @@ -322,39 +319,6 @@ #define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0 #define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 -#if defined CONFIG_SOFT_I2C -/* - * Software (bit-bang) I2C driver configuration - */ -#define PF_SCL PF0 -#define PF_SDA PF1 - -#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;") -#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;") -#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;") -#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;") -#define I2C_SDA(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SDA; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SDA; \ - asm("ssync;"); \ - } -#define I2C_SCL(bit) if(bit) { \ - *pFIO_FLAG_S = PF_SCL; \ - asm("ssync;"); \ - } \ - else { \ - *pFIO_FLAG_C = PF_SCL; \ - asm("ssync;"); \ - } -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ -#endif - -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0xFE - /* 0xFF, 0x7BB07BB0, 0x22547BB0 */ /* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN) #define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index ff7b6e5ca..1f275e5db 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -173,6 +173,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x0 /* * GPIO configuration: diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index faf630496..d814012c4 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -234,7 +234,6 @@ * NAND-FLASH related *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 71e5b58dd..f19374e30 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -117,7 +117,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index cfe6de79f..ce36a2426 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -73,7 +73,7 @@ */ #include <config_cmd_default.h> -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #define CONFIG_BOOTDELAY 0 diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index 5454c2e5b..02cb1efd0 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -73,7 +73,7 @@ */ #include <config_cmd_default.h> -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #define CONFIG_BOOTDELAY 0 diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index 620ffea08..ddcc6aad4 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -65,6 +65,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ /* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index cdd308d8b..d9acb470f 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -44,33 +44,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ -#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 69.120MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3399c1d4 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3399c1d4 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index fa70a09f6..c3c603b42 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -69,7 +69,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_BDI #define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_IMI diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index b9dabac98..52df16af1 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -259,6 +259,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* * Define CONFIG_FEC_10MBIT to force FEC at 10Mb */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index e80504a09..513117504 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -103,7 +103,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ /* valid baudrates */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index a24e34a50..d65c14a67 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -78,7 +78,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO @@ -131,7 +131,7 @@ /* RS: is this where U-Boot is */ /* RS: relocated to in RAM? */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 /* RS: the oscillator is actually 3680130?? */ #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ /* 0101000001 */ diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 874f2c0b3..5d3b09aa3 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -162,7 +162,6 @@ * */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #undef CONFIG_SYS_BASE_BAUD #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 2e30e6964..a33efde9f 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -161,7 +161,6 @@ * */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ -#undef CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 38400 /* Default baud rate */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 682db447d..761c0dca3 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -45,33 +45,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ -#define PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x128A3E19 /* 47.996928 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000302 /* PCK/4 = MCK Master Clock = 46.080000 MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x21914159 /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000080 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x21914159 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ @@ -131,7 +131,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6885b2cbd..667c0d882 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) @@ -172,6 +171,8 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC +#define CONFIG_MUSB_HCD +#define CONFIG_USB_DAVINCI /*===================*/ /* Linux Information */ /*===================*/ @@ -204,6 +205,22 @@ #else #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" #endif +/*==========================*/ +/* USB MSC support (if any) */ +/*==========================*/ +#ifdef CONFIG_USB_DAVINCI +#define CONFIG_CMD_USB +#ifdef CONFIG_MUSB_HCD +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif +#endif /*=======================*/ /* KGDB support (if any) */ /*=======================*/ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 8d7bcf57c..22d3808a3 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -89,7 +89,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /*=====================*/ /* Board related stuff */ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index e9cd5a662..875bab6f7 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -85,7 +85,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ /* I2C switch definitions for PCA9543 chip */ #define CONFIG_SYS_I2C_PCA9543_ADDR 0x70 diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 381eeb7a1..47ab27a87 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -122,7 +122,6 @@ #define CONFIG_SYS_NAND_BASE 0x02000000 #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_MAX_CHIPS 1 #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index a578038b5..b439c80d4 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -97,7 +97,7 @@ #undef CONFIG_CMD_BDI #undef CONFIG_CMD_BEDBUG #undef CONFIG_CMD_ELF -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_MII diff --git a/include/configs/delta.h b/include/configs/delta.h index 08b28ca8a..001b48a7e 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -34,7 +34,6 @@ #ifdef CONFIG_LCD #define CONFIG_SHARP_LM8V31 #endif -/* #define CONFIG_MMC 1 */ #define BOARD_LATE_INIT 1 #undef CONFIG_SKIP_RELOCATE_UBOOT @@ -108,7 +107,7 @@ #else -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #define CONFIG_CMD_I2C @@ -131,8 +130,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "delta" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - #define CONFIG_BOOTDELAY -1 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.0.0 @@ -173,7 +170,7 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ -#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */ +#define CONFIG_SYS_HZ 1000 /* Monahans Core Frequency */ #define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ @@ -183,7 +180,11 @@ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* #define CONFIG_SYS_MMC_BASE 0xF0000000 */ +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes @@ -258,7 +259,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NO_FLASH 1 diff --git a/include/configs/eNET.h b/include/configs/eNET.h new file mode 100644 index 000000000..447c7bc87 --- /dev/null +++ b/include/configs/eNET.h @@ -0,0 +1,248 @@ +/* + * (C) Copyright 2008 + * Graeme Russ, graeme.russ@gmail.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Stuff still to be dealt with - + */ +#define CONFIG_RTC_MC146818 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define DEBUG_PARSER + +#define CONFIG_X86 1 /* Intel X86 CPU */ +#define CONFIG_SC520 1 /* AMD SC520 */ +#define CONFIG_SC520_SSI +#define CONFIG_SHOW_BOOT_PROGRESS 1 +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the + * bottom (processor) board MUST be removed! + */ +#undef CONFIG_WATCHDOG +#undef CONFIG_HW_WATCHDOG + + /*----------------------------------------------------------------------- + * Video Configuration + */ +#undef CONFIG_VIDEO /* No Video Hardware */ +#undef CONFIG_CFB_CONSOLE + +/* + * Size of malloc() pool + */ +#define CONFIG_MALLOC_SIZE (CONFIG_SYS_ENV_SIZE + 128*1024) + +#define CONFIG_BAUDRATE 9600 + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_SAVEENV /* saveenv */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ +#undef CONFIG_CMD_IRQ /* IRQ Information */ + +#define CONFIG_BOOTDELAY 15 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" +/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + \ + 16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1024 /* incrementer freq: 1kHz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * SDRAM Configuration + */ +#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18 +#define CONFIG_NR_DRAM_BANKS 4 + +/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/ +#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY +#undef CONFIG_SYS_SDRAM_REFRESH_RATE +#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T +#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T + +/*----------------------------------------------------------------------- + * CPU Features + */ +#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ +#undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ +#define CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ +#undef CONFIG_SYS_TIMER_GENERIC /* use the i8254 PIT timers */ +#undef CONFIG_SYS_TIMER_TSC /* use the Pentium TSC timers */ +#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those + * in the SC520 on the CDP */ + +/*----------------------------------------------------------------------- + * Memory organization + */ +#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */ +#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */ +#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */ +#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */ +#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + + /*----------------------------------------------------------------------- + * FLASH configuration + */ +#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */ +#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_FLASH_BASE_1, \ + CONFIG_SYS_FLASH_BASE_2} +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + + /*----------------------------------------------------------------------- + * Environment configuration + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ +#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + + + /*----------------------------------------------------------------------- + * PCI configuration + */ +#undef CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* pci plug-and-play */ +#undef CONFIG_PCI_SCAN_SHOW +#undef CONFIG_SYS_FIRST_PCI_IRQ +#undef CONFIG_SYS_SECOND_PCI_IRQ +#undef CONFIG_SYS_THIRD_PCI_IRQ +#undef CONFIG_SYS_FORTH_PCI_IRQ + +/*----------------------------------------------------------------------- + * Hardware watchdog configuration + */ +#define CONFIG_SYS_WATCHDOG_PIO_BIT 0x8000 +#define CONFIG_SYS_WATCHDIG_PIO_DATA SC520_PIODATA15_0 +#define CONFIG_SYS_WATCHDIG_PIO_CLR SC520_PIOCLR15_0 +#define CONFIG_SYS_WATCHDIG_PIO_SET SC520_PIOSET15_0 + +/*----------------------------------------------------------------------- + * FPGA configuration + */ +#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000 +#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000 +#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000 +#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16 +#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16 +#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16 +#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16 +#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */ +#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */ + +#ifndef __ASSEMBLER__ +extern unsigned long ip; + +#define PRINTIP asm ("call next_line\n" \ + "next_line:\n" \ + "pop %%eax\n" \ + "movl %%eax, %0\n" \ + :"=r"(ip) \ + : /* No Input Registers */ \ + :"%eax"); \ + printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__); + +#endif +#endif /* __CONFIG_H */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index fc3174c63..85bf236c6 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -77,7 +77,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_PCI diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h new file mode 100644 index 000000000..d193919dc --- /dev/null +++ b/include/configs/gdppc440etx.h @@ -0,0 +1,194 @@ +/* + * (C) Copyright 2008 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * Based on include/configs/yosemite.h + * (C) Copyright 2005-2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * gdppc440etx.h - configuration for G&D 440EP/GR ETX-Module + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_440GR 1 /* Specific PPC440GR support */ +#define CONFIG_HOSTNAME gdppc440etx +#define CONFIG_440 1 /* ... PPC440 family */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f*/ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory */ +#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 +#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 + +/*Don't change either of these*/ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ +/*Don't change either of these*/ + +#define CONFIG_SYS_USB_DEVICE 0x50000000 +#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 + +/* + * Initial RAM & stack pointer (placed in SDRAM) + */ +#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram*/ +#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes init data*/ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_UART1_CONSOLE + +/* + * Environment + * Define here the location of the environment variables (FLASH or EEPROM). + * Note: DENX encourages to use redundant environment in FLASH. + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* FLASH for env. vars*/ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible*/ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB!*/ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors/chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout/Flash Erase (in ms)*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout/Flash Write (in ms)*/ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x faster)*/ + +#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Env. Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup*/ +#define CONFIG_SYS_KBYTES_SDRAM (128 * 1024) /* 128MB */ +#define CONFIG_SYS_SDRAM_BANKS (2) + +#define CONFIG_SDRAM_BANK0 +#define CONFIG_SDRAM_BANK1 + +#define CONFIG_SYS_SDRAM0_TR0 0x410a4012 +#define CONFIG_SYS_SDRAM0_WDDCTR 0x40000000 +#define CONFIG_SYS_SDRAM0_RTR 0x04080000 +#define CONFIG_SYS_SDRAM0_CFG0 0x80000000 + +#undef CONFIG_SDRAM_ECC + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed+slave address*/ + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "" + +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY1_ADDR 3 + +#ifdef DEBUG +#define CONFIG_PANIC_HANG +#endif + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_PCI +#undef CONFIG_CMD_EEPROM + +/* + * PCI stuff + */ + +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup*/ +#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to \ + CONFIG_SYS_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT +#define CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* tbd */ + +/* + * External Bus Controller (EBC) Setup + */ +#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x03017200 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xda000) + +#endif /* __CONFIG_H */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index aeede0466..b1b4842e0 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -90,7 +90,7 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_DHCP -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_FPGA diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 16b06cd8b..a81527ebe 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -215,6 +215,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 405234cc8..e42fa6dcc 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -221,10 +221,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 1b05b8058..d9b155548 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -73,7 +73,7 @@ #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C #define CONFIG_CMD_IMI @@ -119,7 +119,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* load kernel to this address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 /* RS: the oscillator is actually 3680130?? */ #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 1a70af620..5b4747a57 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -85,7 +85,7 @@ */ #define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_MEMORY diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 35b045127..70f398736 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -73,6 +73,7 @@ #define CONFIG_PCI +#define CONFIG_IXP_PCI #define CONFIG_NET_MULTI #define CONFIG_EEPRO100 @@ -134,6 +135,7 @@ /* * select serial console configuration */ +#define CONFIG_IXP_SERIAL #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ /* diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 528bccdab..193008e0e 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -72,6 +72,7 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_IXP_SERIAL #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 2ebe37057..9c45acf88 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -239,10 +239,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/katmai.h b/include/configs/katmai.h index ea6cf0d23..0d89594f2 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -45,7 +45,6 @@ */ #define CONFIG_PHYS_64BIT #define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) /* * Include common defines/options for all AMCC eval boards diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h new file mode 100644 index 000000000..d70bc4808 --- /dev/null +++ b/include/configs/keymile-common.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_KEYMILE_H +#define __CONFIG_KEYMILE_H + +/* Do boardspecific init for all boards */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_BOOTCOUNT_LIMIT +#endif + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#endif + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* should go away, if kmeter I2C support is enabled */ +#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD) +#define CONFIG_HUSH_INIT_VAR 1 +#endif + +#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */ +#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * How to get access to the slot ID. Put this here to make it easy + * to modify in a centralized location. This is used in the HDLC + * driver to set the MAC. +*/ +#define CONFIG_CHECK_ETHERNET_PRESENT 1 +#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE +#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */ +#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index b943f3153..26cb85439 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -214,7 +214,6 @@ * NAND FLASH *----------------------------------------------------------------------*/ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ @@ -235,16 +234,9 @@ * * DDR Autocalibration Method_B is the default. */ -#if 0 -/* - * Needs FIX!!! - * Disable autocalibration for now, because of the unresolved problem - * with kilauea board using 200MHz PLB/DDR2 frequency - */ #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ #undef CONFIG_PPC4xx_DDR_METHOD_A -#endif #define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE) diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h new file mode 100644 index 000000000..b86c61d5f --- /dev/null +++ b/include/configs/kmeter1.h @@ -0,0 +1,457 @@ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Dave Liu <daveliu@freescale.com> + * + * Copyright (C) 2007 Logic Product Development, Inc. + * Peter Barada <peterb@logicpd.com> + * + * Copyright (C) 2007 MontaVista Software, Inc. + * Anton Vorontsov <avorontsov@ru.mvista.com> + * + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_QE 1 /* Has QE */ +#define CONFIG_MPC83XX 1 /* MPC83XX family */ +#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ +#define CONFIG_KMETER1 1 /* KMETER1 board specific */ + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 66000000 +#define CONFIG_SYS_CLK_FREQ 66000000 +#define CONFIG_83XX_PCICLK 66000000 + +/* + * Hardware Reset Configuration Word + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_CSB_TO_CLKIN_4X1 | \ + HRCWL_CORE_TO_CSB_2X1 | \ + HRCWL_CE_PLL_VCO_DIV_2 | \ + HRCWL_CE_TO_PLL_1X6 ) + +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_CORE_ENABLE | \ + HRCWH_FROM_0X00000100 | \ + HRCWH_BOOTSEQ_NORMAL | \ + HRCWH_SW_WATCHDOG_DISABLE | \ + HRCWH_ROM_LOC_LOCAL_16BIT | \ + HRCWH_BIG_ENDIAN | \ + HRCWH_LDP_CLEAR ) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH 0x00000006 +#define CONFIG_SYS_SICRL 0x00000000 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + +#define CFG_83XX_DDR_USES_CS0 + +#undef CONFIG_DDR_ECC + +/* + * DDRCDR - DDR Control Driver Register + */ + +#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ + +/* + * Manually set up DDR parameters + */ +#define CONFIG_DDR_II +#define CONFIG_SYS_DDR_SIZE 256 /* MB */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ + CSCONFIG_ROW_BIT_13 | \ + CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ + SDRAM_CFG_SREN) +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (0x406 << SDRAM_INTERVAL_REFINT_SHIFT)) + +#define CONFIG_SYS_DDR_MODE 0x04440242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 + +#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ + (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ + (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ + (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ + (0 << TIMING_CFG0_WWT_SHIFT) | \ + (0 << TIMING_CFG0_RRT_SHIFT) | \ + (0 << TIMING_CFG0_WRT_SHIFT) | \ + (0 << TIMING_CFG0_RWT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \ + ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \ + ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \ + ( 2 << TIMING_CFG1_WRREC_SHIFT) | \ + ( 2 << TIMING_CFG1_REFREC_SHIFT) | \ + ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \ + ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ + ( 2 << TIMING_CFG1_PRETOACT_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ + (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ + (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ + (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ + (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ + (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ + (4 << TIMING_CFG2_CPO_SHIFT)) + +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_FLASH_BASE 0xF0000000 +#define CONFIG_SYS_FLASH_BASE_1 0xF2000000 +#define CONFIG_SYS_PIGGY_BASE 0x80000000 +#define CONFIG_SYS_PAXE_BASE 0xA0000000 +#define CONFIG_SYS_PAXE_SIZE 256 + +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) + +/* + * Init Local Bus Memory Controller: + * + * Bank Bus Machine PortSz Size Device + * ---- --- ------- ------ ----- ------ + * 0 Local GPCM 16 bit 256MB FLASH + * 1 Local GPCM 8 bit 256KB GPIO/PIGGY + * 3 Local GPCM 8 bit 256MB PAXE + * + */ +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_V) + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_5 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 } + +#undef CONFIG_SYS_FLASH_CHECKSUM + +/* + * PRIO1/PIGGY on the local bus CS1 + */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */ + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * PAXE on the local bus CS3 + */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */ +#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */ + +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ + (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_V) +#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX | OR_GPCM_EAD) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#undef CONFIG_PCI /* No PCI */ + +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI 1 +#endif +/* + * QE UEC ethernet configuration + */ +#define CONFIG_UEC_ETH +#define CONFIG_ETHPRIME "FSL UEC0" + +#define CONFIG_UEC_ETH1 /* GETH1 */ +#define UEC_VERBOSE_DEBUG 1 + +#ifdef CONFIG_UEC_ETH1 +#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ +#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ +#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 +#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH +#define CONFIG_SYS_UEC1_PHY_ADDR 0 +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII +#endif + +/* + * Environment + */ + +#ifndef CONFIG_SYS_RAMBOOT +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#else /* CFG_RAMBOOT */ +#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif /* CFG_RAMBOOT */ + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#if defined(CFG_RAMBOOT) +#undef CONFIG_CMD_SAVEENV +#undef CONFIG_CMD_LOADS +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR & PCI IO: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L +#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U + +/* PAXE: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U + +#ifdef CONFIG_PCI +/* PCI MEM space: cacheable */ +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT6L CFG_IBAT6L +#define CFG_DBAT6U CFG_IBAT6U +/* PCI MMIO space: cache-inhibit and guarded */ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) +#define CFG_DBAT7L CFG_IBAT7L +#define CFG_DBAT7U CFG_IBAT7U +#else /* CONFIG_PCI */ +#define CONFIG_SYS_IBAT6L (0) +#define CONFIG_SYS_IBAT6U (0) +#define CONFIG_SYS_IBAT7L (0) +#define CONFIG_SYS_IBAT7U (0) +#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L +#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U +#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L +#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U +#endif /* CONFIG_PCI */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_UEC_ETH) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttyS0,${baudrate}\0" \ + "fdt_addr=f0080000\0" \ + "kernel_addr=f00a0000\0" \ + "ramdisk_addr=f03a0000\0" \ + "kernel_addr_r=400000\0" \ + "fdt_addr_r=800000\0" \ + "ramdisk_addr_r=810000\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \ + "tftp ${fdt_addr_r} ${fdt_file}; " \ + "run nfsargs addip addtty;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \ + "boot_file=/tftpboot/kmeter1/uImage\0" \ + "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \ + "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \ + "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "load=tftp $loadaddr ${u-boot}\0" \ + "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \ + "erase " MK_STR(TEXT_BASE) " +$filesize;" \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "protect on " MK_STR(TEXT_BASE) " +$filesize;" \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \ + "setenv filesize;saveenv\0" \ + "upd=run load update\0" \ + "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \ + "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \ + "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \ + "unlock=yes\0" \ + "" + +#endif /* __CONFIG_H */ diff --git a/include/configs/korat.h b/include/configs/korat.h index d56da1448..eb2c1d43b 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Larry Johnson, lrj@acm.org * * (C) Copyright 2006-2007 @@ -138,15 +138,14 @@ /* * DDR SDRAM */ -#define CONFIG_SYS_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */ #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ #define CONFIG_DDR_ECC /* Use ECC when available */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */ - /* 440EPx errata CHIP 11 */ +#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as */ + /* per 440EPx Errata CHIP_11 */ /* * I2C @@ -173,42 +172,59 @@ #define CONFIG_SYS_DTT_MIN_TEMP -30 #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \ "echo" #undef CONFIG_BOOTARGS /* Setup some board specific values for the default environment variables */ #define CONFIG_HOSTNAME korat -#define CONFIG_SYS_BOOTFILE "bootfile=/tftpboot/korat/uImage\0" -#define CONFIG_SYS_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0" /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */ #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_SYS_BOOTFILE \ - CONFIG_SYS_ROOTPATH \ + "u_boot=korat/u-boot.bin\0" \ + "load=tftp 200000 ${u_boot}\0" \ + "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \ + "cp.b ${fileaddr} F7F60000 ${filesize};protect on " \ + "F7F60000 F7FBFFFF\0" \ + "upd=run load update\0" \ + "bootfile=korat/uImage\0" \ + "dtb=korat/korat.dtb\0" \ + "kernel_addr=F4000000\0" \ + "ramdisk_addr=F4400000\0" \ + "dtb_addr=F41E0000\0" \ + "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; " \ + "cp.b ${fileaddr} F4000000 ${filesize}\0" \ + "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; " \ + "cp.b ${fileaddr} F41E0000 ${filesize}\0" \ + "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; " \ + "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} " \ + "${dtb}\0" \ + "rd_size=73728\0" \ + "ramargs=setenv bootargs root=/dev/ram rw " \ + "ramdisk_size=${rd_size}\0" \ + "usbdev=sda1\0" \ + "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ "netdev=eth0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "pciclk=33\0" \ + "addide=setenv bootargs ${bootargs} ide=reverse " \ + "idebus=${pciclk}\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "kernel_addr=F4000000\0" \ - "ramdisk_addr=F4400000\0" \ - "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ - "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load update\0" \ + "flash_cf=run usbargs addide addip addtty; " \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "flash_nfs=run nfsargs addide addip addtty; " \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "flash_self=run ramargs addip addtty; " \ + "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTCOMMAND "run flash_cf" #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -278,15 +294,15 @@ #define CONFIG_CMD_USB /* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_ECC | \ - CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU | \ - CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_SPR | \ +#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_ECC | \ + CONFIG_SYS_POST_ETHER | \ + CONFIG_SYS_POST_FPU | \ + CONFIG_SYS_POST_I2C | \ + CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_SPR | \ CONFIG_SYS_POST_UART) #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) @@ -403,7 +419,7 @@ * GPIO10 Alt1 O x PerCS5 to expansion bus connector * GPIO11 Alt1 I x PerErr * GPIO12 GPIO O 0 ATMega !Reset - * GPIO13 GPIO O 1 SPI Atmega !SS + * GPIO13 GPIO x x Test Point 2 (TP2) * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) * GPIO15 GPIO O 0 CPU Run LED !On * GPIO16 Alt1 O x GMC1TxD0 @@ -478,7 +494,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \ diff --git a/include/configs/logodl.h b/include/configs/logodl.h index bb6f943ae..cd105da31 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -69,7 +69,7 @@ */ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_ECHO -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_RUN @@ -112,7 +112,7 @@ #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* load kernel to this address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 /* RS: the oscillator is actually 3680130?? */ #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 208910eb9..69774d746 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -40,7 +40,7 @@ #ifdef CONFIG_LCD #define CONFIG_SHARP_LM8V31 #endif -#define CONFIG_MMC 1 +#define CONFIG_MMC #define BOARD_LATE_INIT 1 #define CONFIG_DOS_PARTITION @@ -83,7 +83,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT @@ -127,13 +126,17 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes diff --git a/include/configs/m501sk.h b/include/configs/m501sk.h index f09214dce..a43285051 100644 --- a/include/configs/m501sk.h +++ b/include/configs/m501sk.h @@ -41,6 +41,39 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_MENUPROMPT "." +/* + * LowLevel Init + */ +#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +/* flash */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ + +/* clocks */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ +/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 + +/* sdram */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ /* * Size of malloc() pool @@ -121,7 +154,7 @@ #define CONFIG_CMD_IMI #define CONFIG_CMD_NFS #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_SYS_HUSH_PARSER #define CONFIG_AUTO_COMPLETE diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index e64cc3704..e5812ee8a 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -271,11 +271,12 @@ /* * Ethernet configuration */ -/*#define CONFIG_MPC5xxx_FEC 1*/ +/* #define CONFIG_MPC5xxx_FEC 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII100 */ /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 1 /* diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 7ef5bdfd9..4a93b5888 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -243,10 +243,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_UDP_CHECKSUM 1 diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index dc9b311d4..79c70502e 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -32,11 +32,12 @@ #define CONFIG_MPC8247 1 #define CONFIG_MPC8272_FAMILY 1 #define CONFIG_MGCOGE 1 +#define CONFIG_HOSTNAME mgcoge #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" /* * Select serial console configuration @@ -49,6 +50,8 @@ #undef CONFIG_CONS_ON_SCC /* It's not on SCC */ #undef CONFIG_CONS_NONE /* It's not on external UART */ #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 /* * Select ethernet configuration @@ -64,6 +67,7 @@ #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */ #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ +#define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 @@ -74,22 +78,13 @@ #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif -#define CONFIG_BAUDRATE 115200 +#define BOOTFLASH_START FE000000 +#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ -#define CONFIG_BOOTCOUNT_LIMIT - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DTT -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING +#define MTDIDS_DEFAULT "nor0=boot,nor1=app" +#define MTDPARTS_DEFAULT \ + "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \ + "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)" /* * Default environment settings @@ -123,37 +118,9 @@ "tftp ${ramdisk_addr} ${ramdisk_file}; " \ "run ramargs addip; " \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "EEprom_ivm=pca9544a:70:4 \0" \ + "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \ "" -#define CONFIG_BOOTCOMMAND "run net_nfs" -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_HUSH_INIT_VAR 1 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xFE000000 @@ -173,12 +140,12 @@ #define CONFIG_SYS_RAMBOOT #endif -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */ #define CONFIG_ENV_IS_IN_FLASH #ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x4000 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN @@ -186,6 +153,7 @@ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) #endif /* CONFIG_ENV_IS_IN_FLASH */ +#define CONFIG_ENV_BUFFER_PRINT 1 /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ @@ -233,6 +201,8 @@ #define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + #define CONFIG_SYS_IMMR 0xF0000000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR @@ -379,6 +349,18 @@ ORxG_CSNT | ORxG_ACS_DIV2 |\ ORxG_SCY_3_CLK | ORxG_TRLX ) +/* Board FPGA on CS4 initialization values +*/ +#define CONFIG_SYS_FPGA_BASE 0x40000000 +#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/ + +#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\ + BRx_PS_8 | BRx_MS_GPCM_P | BRx_V) + +#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\ + ORxG_CSNT | ORxG_ACS_DIV2 |\ + ORxG_SCY_3_CLK | ORxG_TRLX ) + /* CFG-Flash on CS5 initialization values */ #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\ diff --git a/include/configs/mgsuvd.h b/include/configs/mgsuvd.h index fca2e5513..4623e4c85 100644 --- a/include/configs/mgsuvd.h +++ b/include/configs/mgsuvd.h @@ -35,32 +35,29 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */ +#define CONFIG_HOSTNAME mgsuvd -/* Do boardspecific init */ -#define CONFIG_BOARD_EARLY_INIT_R 1 +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" #define CONFIG_8xx_GCLK_FREQ 66000000 #define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */ #define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_SYS_SMC_RXBUFLEN 128 +#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_BOOTCOUNT_LIMIT #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation, the * default value is not working */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define BOOTFLASH_START F0000000 +#define CONFIG_PRAM 512 /* protected RAM [KBytes] */ #define CONFIG_PREBOOT "echo;" \ "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" -#undef CONFIG_BOOTARGS - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ @@ -88,71 +85,12 @@ "cp.b 200000 f0000000 ${filesize};" \ "protect on f0000000 +${filesize}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */ #define CONFIG_TIMESTAMP /* but print image timestmps */ /* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ -#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_HUSH_INIT_VAR 1 -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. @@ -178,7 +116,7 @@ */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ @@ -203,13 +141,14 @@ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ +#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN +#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ /* Address and size of Redundant Environment Sector */ #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_BUFFER_PRINT 1 /*----------------------------------------------------------------------- * Cache Configuration @@ -392,4 +331,9 @@ #define CONFIG_SYS_DTT_HYSTERESIS 3 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS) +#define MTDIDS_DEFAULT "nor0=app" +#define MTDPARTS_DEFAULT ( \ + "mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \ + "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)") + #endif /* __CONFIG_H */ diff --git a/include/configs/ml401.h b/include/configs/microblaze-generic.h index c802dcb6a..ac18c8776 100644 --- a/include/configs/ml401.h +++ b/include/configs/microblaze-generic.h @@ -25,32 +25,33 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include "../board/xilinx/ml401/xparameters.h" +#include "../board/xilinx/microblaze-generic/xparameters.h" #define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */ #define MICROBLAZE_V5 1 -#define CONFIG_ML401 1 /* ML401 Board */ /* uart */ #ifdef XILINX_UARTLITE_BASEADDR -#define CONFIG_XILINX_UARTLITE -#define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR -#define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE -#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } + #define CONFIG_XILINX_UARTLITE + #define CONFIG_SERIAL_BASE XILINX_UARTLITE_BASEADDR + #define CONFIG_BAUDRATE XILINX_UARTLITE_BAUDRATE + #define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE } + #define CONSOLE_ARG "console=console=ttyUL0,115200\0" #elif XILINX_UART16550_BASEADDR -#define CONFIG_SYS_NS16550 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) -#define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ -#define CONFIG_BAUDRATE 115200 - -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + #define CONFIG_SYS_NS16550 1 + #define CONFIG_SYS_NS16550_SERIAL + #define CONFIG_SYS_NS16550_REG_SIZE -4 + #define CONFIG_CONS_INDEX 1 + #define CONFIG_SYS_NS16550_COM1 (XILINX_UART16550_BASEADDR + 0x1000 + 0x3) + #define CONFIG_SYS_NS16550_CLK XILINX_UART16550_CLOCK_HZ + #define CONFIG_BAUDRATE 115200 + + /* The following table includes the supported baudrates */ + #define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + #define CONSOLE_ARG "console=console=ttyS0,115200\0" #else -#error Undefined uart + #error Undefined uart #endif /* setting reset address */ @@ -58,44 +59,44 @@ /* ethernet */ #ifdef XILINX_EMAC_BASEADDR -#define CONFIG_XILINX_EMAC 1 -#define CONFIG_SYS_ENET -#else -#ifdef XILINX_EMACLITE_BASEADDR -#define CONFIG_XILINX_EMACLITE 1 -#define CONFIG_SYS_ENET -#endif + #define CONFIG_XILINX_EMAC 1 + #define CONFIG_SYS_ENET +#elif XILINX_EMACLITE_BASEADDR + #define CONFIG_XILINX_EMACLITE 1 + #define CONFIG_SYS_ENET +#elif XILINX_LLTEMAC_BASEADDR + #define CONFIG_XILINX_LL_TEMAC 1 + #define CONFIG_SYS_ENET #endif + #undef ET_DEBUG /* gpio */ #ifdef XILINX_GPIO_BASEADDR -#define CONFIG_SYS_GPIO_0 1 -#define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR + #define CONFIG_SYS_GPIO_0 1 + #define CONFIG_SYS_GPIO_0_ADDR XILINX_GPIO_BASEADDR #endif /* interrupt controller */ #ifdef XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0 1 -#define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -#define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS + #define CONFIG_SYS_INTC_0 1 + #define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR + #define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS #endif /* timer */ #ifdef XILINX_TIMER_BASEADDR -#if (XILINX_TIMER_IRQ != -1) -#define CONFIG_SYS_TIMER_0 1 -#define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -#define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#define FREQUENCE XILINX_CLOCK_FREQ -#define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) -#endif -#else -#ifdef XILINX_CLOCK_FREQ -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ + #if (XILINX_TIMER_IRQ != -1) + #define CONFIG_SYS_TIMER_0 1 + #define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR + #define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ + #define FREQUENCE XILINX_CLOCK_FREQ + #define CONFIG_SYS_TIMER_0_PRELOAD ( FREQUENCE/1000 ) + #endif +#elif XILINX_CLOCK_FREQ + #define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ #else -#error BAD CLOCK FREQ -#endif + #error BAD CLOCK FREQ #endif /* FSL */ /* #define CONFIG_SYS_FSL_2 */ @@ -160,7 +161,7 @@ #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* ?empty sector */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ - #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ #define CONFIG_SYS_FLASH_PROTECTION /* hardware flash protection */ #ifdef RAMENV @@ -170,9 +171,9 @@ #else /* !RAMENV */ #define CONFIG_ENV_IS_IN_FLASH 1 - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) - #define CONFIG_ENV_SIZE 0x40000 + #define CONFIG_ENV_SIZE 0x20000 #endif /* !RAMBOOT */ #else /* !FLASH */ /* ENV in RAM */ @@ -193,6 +194,18 @@ #define CONFIG_DOS_PARTITION #endif +#if defined(XILINX_USE_ICACHE) + #define CONFIG_ICACHE +#else + #undef CONFIG_ICACHE +#endif + +#if defined(XILINX_USE_DCACHE) + #define CONFIG_DCACHE +#else + #undef CONFIG_DCACHE +#endif + /* * BOOTP options */ @@ -207,9 +220,15 @@ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE #define CONFIG_CMD_IRQ #define CONFIG_CMD_MFSL +#define CONFIG_CMD_ECHO + +#if defined(CONFIG_DCACHE) || defined(CONFIG_ICACHE) + #define CONFIG_CMD_CACHE +#else + #undef CONFIG_CMD_CACHE +#endif #ifndef CONFIG_SYS_ENET #undef CONFIG_CMD_NET @@ -229,11 +248,13 @@ #define CONFIG_CMD_JFFS2 #if !defined(RAMENV) - #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SAVES #endif #else + #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_JFFS2 #endif #if defined(CONFIG_CMD_JFFS2) @@ -253,11 +274,11 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */ #define CONFIG_SYS_MAXARGS 15 /* max number of command args */ #define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_LOAD_ADDR 0x12000000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR XILINX_RAM_START /* default load address */ -#define CONFIG_BOOTDELAY 30 +#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BOOTARGS "root=romfs" -#define CONFIG_HOSTNAME "ml401" +#define CONFIG_HOSTNAME XILINX_BOARD_NAME #define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" #define CONFIG_IPADDR 192.168.0.3 #define CONFIG_SERVERIP 192.168.0.5 @@ -268,7 +289,7 @@ #define CONFIG_SYS_USR_EXCEP /* user exception */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_PREBOOT "echo U-BOOT for ML401;setenv preboot;echo" +#define CONFIG_PREBOOT "echo U-BOOT for $(hostname);setenv preboot;echo" #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ "nor0=ml401-0\0"\ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index b3f16d5e7..e6e3729a2 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -82,6 +82,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x2 #define CONFIG_PHY_TYPE 0x79c874 #define CONFIG_RESET_PHY_R 1 diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index cbbdb0c77..9ac7e9afb 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -49,33 +49,33 @@ #ifndef CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 /* flash */ -#define MC_PUIA_VAL 0x00000000 -#define MC_PUP_VAL 0x00000000 -#define MC_PUER_VAL 0x00000000 -#define MC_ASR_VAL 0x00000000 -#define MC_AASR_VAL 0x00000000 -#define EBI_CFGR_VAL 0x00000000 -#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ +#define CONFIG_SYS_MC_PUIA_VAL 0x00000000 +#define CONFIG_SYS_MC_PUP_VAL 0x00000000 +#define CONFIG_SYS_MC_PUER_VAL 0x00000000 +#define CONFIG_SYS_MC_ASR_VAL 0x00000000 +#define CONFIG_SYS_MC_AASR_VAL 0x00000000 +#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 +#define CONFIG_SYS_SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */ /* clocks */ -#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ -#define PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ -#define MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ +#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */ +#define CONFIG_SYS_PLLBR_VAL 0x1048bE0E /* 48 MHz (divider by 2 for USB) */ +#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 60MHz from PLLA */ /* sdram */ -#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define PIOC_BSR_VAL 0x00000000 -#define PIOC_PDR_VAL 0xFFFF0000 -#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */ -#define SDRC_CR_VAL 0x3211295A /* set up the SDRAM */ -#define SDRAM 0x20000000 /* address of the SDRAM */ -#define SDRAM1 0x20000020 /* address of the SDRAM */ -#define SDRAM_VAL 0x00000000 /* value written to SDRAM */ -#define SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define SDRC_MR_VAL1 0x00000004 /* refresh */ -#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ +#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ +#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 +#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 +#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_CR_VAL 0x3211295A /* set up the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM1 0x20000020 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ +#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ +#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ +#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ +#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ #else #define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ @@ -216,7 +216,6 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ #define CONFIG_SYS_DEVICE_DEREGISTER /* needs device_deregister */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ #define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK/2) /* AT91C_TC0_CMR is implicitly set to */ diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 483bc5305..a1783b200 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -163,7 +163,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_EEPROM #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_BSP #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING diff --git a/include/configs/mpr2.h b/include/configs/mpr2.h index 6ebb1e17b..86f6a934f 100644 --- a/include/configs/mpr2.h +++ b/include/configs/mpr2.h @@ -27,7 +27,7 @@ #define __MPR2_H /* Supported commands */ -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CACHE #define CONFIG_CMD_MEMORY #define CONFIG_CMD_FLASH diff --git a/include/configs/ms7720se.h b/include/configs/ms7720se.h index 520bac074..9a88ec7fa 100644 --- a/include/configs/ms7720se.h +++ b/include/configs/ms7720se.h @@ -31,7 +31,7 @@ #define CONFIG_MS7720SE 1 #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY #define CONFIG_CMD_CACHE diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 52020047d..53ffbeef2 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -38,7 +38,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/ms7750se.h b/include/configs/ms7750se.h index af9933cad..5eed3ab66 100644 --- a/include/configs/ms7750se.h +++ b/include/configs/ms7750se.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_SCIF_CONSOLE 1 #define CONFIG_BAUDRATE 38400 diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index 2f48a0f25..ae60cd221 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -225,6 +225,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 /* MII PHY management */ diff --git a/include/configs/munices.h b/include/configs/munices.h index 7682faa32..fa5230f52 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -166,6 +166,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x01 #define CONFIG_MII 1 diff --git a/include/configs/netstar.h b/include/configs/netstar.h index dda659784..2c90265e3 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -120,7 +120,6 @@ * NAND flash */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x04000000 + (2 << 23) #define NAND_ALLOW_ERASE_ALL 1 @@ -141,7 +140,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_JFFS2 diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h new file mode 100644 index 000000000..543780d77 --- /dev/null +++ b/include/configs/nmdk8815.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2005 + * STMicroelectronics. + * Configuration settings for the STn8815 nomadik board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <nomadik.h> + +#define CONFIG_ARM926EJS +#define CONFIG_NOMADIK +#define CONFIG_NOMADIK_8815 +#define CONFIG_NOMADIK_NDK15 +#define CONFIG_NOMADIK_NHK15 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ + +/* commands */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +/* There is no NOR flash, so undefine these commands */ +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_NO_FLASH +/* There is NAND storage */ +#define CONFIG_NAND_NOMADIK +#define CONFIG_CMD_JFFS2 + +/* user interface */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Nomadik> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* boot config */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" +#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ + " fsload 0x800000 initrd.gz.uimg;" \ + " bootm 0x100000 0x800000" + +/* memory-related information */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ + +#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ + +/* timing informazion */ +#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ +#define CONFIG_SYS_TIMERBASE 0x101E2000 +#undef CONFIG_SYS_CLKS_IN_HZ + +/* serial port (PL011) configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SERIAL0 0x101FD000 +#define CFG_SERIAL1 0x101FB000 + +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } +#define CONFIG_PL011_CLOCK 48000000 + +/* Ethernet */ +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_IO_VADDR 0xee000000 +#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) +#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) + +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/ +#define CONFIG_SMC91111_BASE 0x34000300 +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT +#define CONFIG_BOOTFILE "uImage" + +/* flash memory and filesystem information */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MTD_ONENAND_VERIFY_WRITE +#define CONFIG_SYS_ONENAND_BASE 0x30000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ + +#ifdef CONFIG_BOOT_ONENAND + +# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ + /* Partition Size Start + * XloaderTOC + X-Loader 256KB 0x00000000 + * Memory init function 256KB 0x00040000 + * U-Boot 2MB 0x00080000 + * Sysimage (kernel + ramdisk) 4MB 0x00280000 + * JFFS2 Root filesystem 22MB 0x00680000 + * JFFS2 User Data 227.5MB 0x01C80000 + */ +# define CONFIG_JFFS2_PART_SIZE 0x400000 +# define CONFIG_JFFS2_PART_OFFSET 0x280000 + +# define CONFIG_ENV_IS_IN_ONENAND +# define CONFIG_ENV_SIZE (256 * 1024) +# define CONFIG_ENV_ADDR 0x30300000 + +#else /* ! CONFIG_BOOT_ONENAND */ + +# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ + +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ +# define CONFIG_JFFS2_PART_SIZE 0x00300000 +# define CONFIG_JFFS2_PART_OFFSET 0x00280000 + +# define CONFIG_ENV_IS_IN_NAND +# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ +# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE) + +#endif /* CONFIG_BOOT_ONENAND */ + +/* this is needed to make hello_world.c and other stuff happy */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index bfae7b429..18e7cc2a9 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -233,10 +233,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index d11868e08..92df0b4fd 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -163,7 +163,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) #define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h new file mode 100644 index 000000000..90576060e --- /dev/null +++ b/include/configs/omap3_beagle.h @@ -0,0 +1,325 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * + * Configuration settings for the TI OMAP3530 Beagle board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "videomode=1024x768@60,vxres=1024,vyres=768\0" \ + "videospec=omapfb:vram:2M,vram:4M\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3 beagleboard.org # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h new file mode 100644 index 000000000..f4498a9bc --- /dev/null +++ b/include/configs/omap3_evm.h @@ -0,0 +1,345 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Author : + * Manikandan Pillai <mani.pillai@ti.com> + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> + * + * Manikandan Pillai <mani.pillai@ti.com> + * + * Configuration settings for the TI OMAP3 EVM board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_EVM 1 /* working with EVM */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_ONENAND /* ONENAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access */ + /* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ + /* NAND devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "onenand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3_EVM # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ + /* in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ + /* on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_ONENAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR boot_flash_env_addr + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_32_BIT +#define CONFIG_DRIVER_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + +/* + * BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h new file mode 100644 index 000000000..dee0417de --- /dev/null +++ b/include/configs/omap3_overo.h @@ -0,0 +1,318 @@ +/* + * Configuration settings for the Gumstix Overo board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_OVERO 1 /* working with overo */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand */ + /* at CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "videomode=1024x768@60,vxres=1024,vyres=768\0" \ + "videospec=omapfb:vram:2M,vram:4M\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "Overo # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ + /* in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h new file mode 100644 index 000000000..00c037464 --- /dev/null +++ b/include/configs/omap3_pandora.h @@ -0,0 +1,320 @@ +/* + * (C) Copyright 2008 + * Grazvydas Ignotas <notasas@gmail.com> + * + * Configuration settings for the OMAP3 Pandora. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand */ + /* at CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS0,115200n8\0" \ + "videospec=omapfb:vram:2M,vram:4M\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "video=${videospec} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "video=${videospec} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "Pandora # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command */ + /* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, */ + /* in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ + /* address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h new file mode 100644 index 000000000..f8ae16394 --- /dev/null +++ b/include/configs/omap3_zoom1.h @@ -0,0 +1,327 @@ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <x0khasim@ti.com> + * Nishanth Menon <nm@ti.com> + * + * Configuration settings for the TI OMAP3430 Zoom MDK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ + /* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* + * Board NAND Info. + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ + /* devices */ +#define SECTORSIZE 512 + +#define NAND_ALLOW_ERASE_ALL +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 + +#define NAND_ChipID_UNKNOWN 0x00 +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 +#define NAND_NO_RB 1 +#define CONFIG_SYS_NAND_WP + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ + /* partition */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS2,115200n8\0" \ + "videomode=1024x768@60,vxres=1024,vyres=768\0" \ + "videospec=omapfb:vram:2M,vram:4M\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "video=${videospec},mode:${videomode} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP3 Zoom1# " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ + /* works on */ +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000) /* 31MB */ + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ + /* load address */ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define V_PVT 7 + +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PVT)) + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP + +#define CONFIG_ENV_IS_IN_NAND 1 +#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ +#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#ifndef __ASSEMBLY__ +extern gpmc_csx_t *nand_cs_base; +extern gpmc_t *gpmc_cfg_base; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + + +#define WRITE_NAND_COMMAND(d, adr)\ + writel(d, &nand_cs_base->nand_cmd) +#define WRITE_NAND_ADDRESS(d, adr)\ + writel(d, &nand_cs_base->nand_adr) +#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat) +#define READ_NAND(adr) readl(&nand_cs_base->nand_dat) + +/* Other NAND Access APIs */ +#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \ + while (0) +#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \ + while (0) +#define NAND_DISABLE_CE(nand) +#define NAND_ENABLE_CE(nand) +#define NAND_WAIT_READY(nand) udelay(10) + +#endif /* __CONFIG_H */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 7c7bebac3..5ad745e64 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -198,7 +198,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_FPGA diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 8b7890e2c..4da401f46 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -68,6 +68,7 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_IXP_SERIAL #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ @@ -264,7 +265,6 @@ * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ #endif diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index b2e2a1c4a..8ca55d78e 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -245,10 +245,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 #define CONFIG_UDP_CHECKSUM 1 diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 14f8917a9..59741a98f 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -126,12 +126,17 @@ #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#endif + /* * Stack sizes * diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 577ab8ef6..0fd863568 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -83,7 +83,7 @@ #include <config_cmd_default.h> #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_RUN #define CONFIG_CMD_ELF #define CONFIG_CMD_NET diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index f81103b79..d1c2c650c 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -119,7 +119,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_DHCP @@ -241,7 +240,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #define RTC 1 /* enable 32KHz osc */ @@ -249,7 +248,11 @@ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index f028d1ac6..844446205 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -150,7 +150,7 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) /* Address and size of Primary Environment Sector */ #define CONFIG_ENV_SIZE 0x8000 diff --git a/include/configs/qong.h b/include/configs/qong.h new file mode 100644 index 000000000..ccc262513 --- /dev/null +++ b/include/configs/qong.h @@ -0,0 +1,221 @@ +/* + * Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com> + * + * Configuration settings for the Dave/DENX QongEVB-LITE board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx31-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_QONG 1 +#define CONFIG_MX31_HCLK_FREQ 26000000 /* 26MHz */ +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CONFIG_SYS_MX31_UART1 1 + +/* FPGA */ +#define CONFIG_QONG_FPGA 1 +#define CONFIG_FPGA_BASE (CS1_BASE) + +#ifdef CONFIG_QONG_FPGA +/* Ethernet */ +#define CONFIG_DNET 1 +#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE) +#define CONFIG_NET_MULTI 1 + +/* + * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the + * initial TFTP transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +#endif /* CONFIG_QONG_FPGA */ + +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_JFFS2 + +/* + * You can compile in a MAC address and your custom net settings by using + * the following syntax. + * + * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx + * #define CONFIG_SERVERIP <server ip> + * #define CONFIG_IPADDR <board ip> + * #define CONFIG_GATEWAYIP <gateway ip> + * #define CONFIG_NETMASK <your netmask> + */ + +#define CONFIG_BOOTDELAY 5 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=ttymxc0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "uboot_addr=a0000000\0" \ + "kernel_addr=a0080000\0" \ + "ramdisk_addr=a0300000\0" \ + "u-boot=qong/u-boot.bin\0" \ + "kernel_addr_r=80800000\0" \ + "hostname=qong\0" \ + "bootfile=qong/uImage\0" \ + "rootpath=/opt/eldk-4.2-arm/armVFP\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm\0" \ + "bootcmd=run flash_self\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* memtest works on first 255MB of RAM */ +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_MISC_INIT_R 1 +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 +/* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +/* Flash memory is CFI compliant */ +#define CONFIG_SYS_FLASH_CFI 1 +/* Use drivers/cfi_flash.c */ +#define CONFIG_FLASH_CFI_DRIVER 1 +/* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Use hardware sector protection */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + +/* + * JFFS2 partitions + */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:256k(U-Boot),128k(env1)," \ + "128k(env2),2560k(kernel),13m(ramdisk),-(user)" + +#endif /* __CONFIG_H */ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 0f7fca38d..3ea854bec 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -224,7 +224,6 @@ #define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */ #define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */ #define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */ -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index f85d5d669..72a3b5c8b 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -43,7 +43,7 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_NET #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NFS #define CONFIG_CMD_IDE #define CONFIG_CMD_EXT2 diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index f88a77340..36e4c017b 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -37,7 +37,7 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_SDRAM #define CONFIG_CMD_MEMORY #define CONFIG_CMD_CACHE diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index d7a6ae46c..bf4a14e00 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -209,7 +209,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define NAND_WAIT_READY(nand) NF_WaitRB() #define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH) diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index c156820ac..7197aaf79 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -147,7 +147,6 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 /* The following table includes the supported baudrates */ diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h index d19a787e9..1cc2920b3 100644 --- a/include/configs/sbc8240.h +++ b/include/configs/sbc8240.h @@ -96,7 +96,7 @@ #define CONFIG_CMD_BSP #define CONFIG_CMD_DIAG #define CONFIG_CMD_ELF -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_PCI #define CONFIG_CMD_PING diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0603e3c8a..f476e3ed5 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -455,7 +455,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 528c81090..8141a46dc 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -399,25 +399,16 @@ #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC2" -#define CONFIG_TSEC4 -#define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 +#define TSEC1_PHY_ADDR 0x19 +#define TSEC2_PHY_ADDR 0x1a #define TSEC1_PHYIDX 0 #define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 + #define TSEC1_FLAGS TSEC_GIGABIT #define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" @@ -464,6 +455,7 @@ /* * Miscellaneous configurable options */ +#define CONFIG_CMDLINE_EDITING /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ @@ -507,10 +499,6 @@ #define CONFIG_ETHADDR 02:E0:0C:00:00:FD #define CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD -#define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 02:E0:0C:00:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 02:E0:0C:00:03:FD #endif #define CONFIG_IPADDR 192.168.0.55 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index d4e9d7479..4fa501da5 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -380,7 +380,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #endif diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 001294575..1008812b7 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -311,18 +311,22 @@ * General PCI * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_BUS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BUS +#define CONFIG_SYS_PCI1_IO_VIRT CONFIG_SYS_PCI1_IO_BUS #define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS +#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BUS #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0xe3000000 -#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BASE +#define CONFIG_SYS_PCI2_IO_BUS 0xe3000000 +#define CONFIG_SYS_PCI2_IO_PHYS CONFIG_SYS_PCI2_IO_BUS +#define CONFIG_SYS_PCI2_IO_VIRT CONFIG_SYS_PCI2_IO_BUS #define CONFIG_SYS_PCI2_IO_SIZE 0x1000000 /* 16M */ #if defined(CONFIG_PCI) @@ -409,10 +413,10 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* @@ -452,10 +456,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW \ +#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U /* diff --git a/include/configs/sc3.h b/include/configs/sc3.h index d152a9670..515b09789 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -424,7 +424,6 @@ extern unsigned long offsetOfEnvironment; * NAND-FLASH stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE 0x77D00000 diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index bf8693e46..9f2357b0b 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -47,7 +47,6 @@ #define CONFIG_SYS_SDRAM_CAS_LATENCY_3T #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ #undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ #undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ #define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index fbdbeddf6..50af7324a 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_SDRAM_CAS_LATENCY_3T #define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */ -#define CONFIG_SYS_RESET_GENERIC 1 /* use tripple-fault to reset cpu */ #undef CONFIG_SYS_RESET_SC520 /* use SC520 MMCR's to reset cpu */ #undef CONFIG_SYS_TIMER_SC520 /* use SC520 swtimers */ #define CONFIG_SYS_TIMER_GENERIC 1 /* use the i8254 PIT timers */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 9321bdc07..a3e2fcef4 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -373,7 +373,6 @@ * NAND FLASH */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index 8a76dad5d..8d7456eb6 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_PING -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NFS #define CONFIG_CMD_JFFS2 @@ -118,6 +118,7 @@ #define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) /* Ether */ +#define CONFIG_NET_MULTI 1 #define CONFIG_SH_ETHER 1 #define CONFIG_SH_ETHER_USE_PORT (1) #define CONFIG_SH_ETHER_PHY_ADDR (0x01) diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 1b5905945..537ec4eca 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -40,7 +40,7 @@ #define CONFIG_CMD_DFL #define CONFIG_CMD_SDRAM #define CONFIG_CMD_RUN -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE @@ -123,7 +123,6 @@ #undef CONFIG_SYS_DIRECT_FLASH_TFTP /* R8A66597 */ -#define LITTLEENDIAN /* for include/usb.h */ #define CONFIG_USB_R8A66597_HCD #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index 1784cc622..06d6a8859 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -104,7 +104,7 @@ #define CONFIG_CMD_REGINFO #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #if defined(CONFIG_BOOT_ONENAND) #define CONFIG_CMD_ONENAND @@ -227,7 +227,6 @@ /* NAND configuration */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x70200010 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_S3C_NAND_HWECC #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ @@ -294,7 +293,6 @@ #define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ #define CONFIG_USB_STORAGE 1 #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index cbf04e3f2..becd13eac 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -186,7 +186,6 @@ #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND /* LIME GDC */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index ae6f45aee..0424e2978 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -322,7 +322,7 @@ #define CONFIG_CMD_I2C #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #else #define CONFIG_CMD_ELF diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index c312f1af9..2783f9e04 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -363,7 +363,7 @@ #endif #if defined(CONFIG_SYS_RAMBOOT) - #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_LOADS #else #define CONFIG_CMD_ELF diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index bc078cf37..5a5f7728f 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -464,7 +464,6 @@ #define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ #define NAND_DISABLE_CE(nand) \ diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index b702de0c5..353e8db42 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -62,7 +62,7 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_BDI -#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_SAVEENV #undef CONFIG_CMD_MEMORY #undef CONFIG_CMD_NET #undef CONFIG_CMD_MISC diff --git a/include/configs/trab.h b/include/configs/trab.h index 562cd6093..0a7a73d30 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -44,7 +44,6 @@ #define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */ #define CONFIG_TRAB 1 /* on a TRAB Board */ #undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ /* automatic software updates (see board/trab/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index b2065ee48..70e5ce97b 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -42,8 +42,6 @@ */ #define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ -#define LITTLEENDIAN 1 /* used by usb_ohci.c */ - #define CONFIG_MMC 1 #define BOARD_LATE_INIT 1 @@ -81,7 +79,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_IMLS #define CONFIG_CMD_PING @@ -170,13 +167,17 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 553eb25fb..87cb4e508 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -233,6 +233,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index 6e9c27c1e..1a47aadcf 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -105,7 +105,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CONFIG_CMD_PCI #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_CONSOLE #define CONFIG_CMD_LOADS #define CONFIG_CMD_LOADB diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 0156ce1c1..fc7128e73 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -247,6 +247,7 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 #define CONFIG_PHY_ADDR 0x00 #define CONFIG_MII 1 diff --git a/include/configs/vct.h b/include/configs/vct.h new file mode 100644 index 000000000..391535ed2 --- /dev/null +++ b/include/configs/vct.h @@ -0,0 +1,340 @@ +/* + * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file contains the configuration parameters for the VCT board + * family: + * + * vct_premium + * vct_premium_small + * vct_premium_onenand + * vct_premium_onenand_small + * vct_platinum + * vct_platinum_small + * vct_platinum_onenand + * vct_platinum_onenand_small + * vct_platinumavc + * vct_platinumavc_small + * vct_platinumavc_onenand + * vct_platinumavc_onenand_small + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MIPS32 /* MIPS 4Kc CPU core */ +#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_STACKSIZE (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 + +#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND) +#define CONFIG_VCT_NOR +#else +#define CONFIG_SYS_NO_FLASH +#endif + +/* + * UART + */ +#define CONFIG_VCT_SERIAL +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * SDRAM + */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_MBYTES_SDRAM 128 +#define CONFIG_SYS_MEMTEST_START 0x80200000 +#define CONFIG_SYS_MEMTEST_END 0x80400000 +#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ + +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +/* + * SMSC91C11x Network Card + */ +#define CONFIG_DRIVER_SMC911X +#define CONFIG_DRIVER_SMC911X_BASE 0x00000000 +#define CONFIG_DRIVER_SMC911X_32_BIT +#define CONFIG_NET_RETRY_COUNT 20 +#endif + +/* + * Commands + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + +/* + * Only Premium/Platinum have ethernet support right now + */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP +#else +#undef CONFIG_CMD_NET +#endif + +/* + * Only Premium/Platinum have USB-EHCI support right now + */ +#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#endif + +#if defined(CONFIG_CMD_USB) +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_SUPPORT_VFAT + +/* + * USB/EHCI + */ +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_VCT /* on VCT platform */ +#define CONFIG_EHCI_DCACHE /* with dcache handling support */ +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ +#endif /* CONFIG_CMD_USB */ + +#if !defined(CONFIG_VCT_NOR) +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#endif + +#if defined(CONFIG_VCT_NAND) +#define CONFIG_CMD_NAND +#endif + +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_CMD_ONENAND +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCT# " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/ + +/* + * FLASH and environment organization + */ +#if defined(CONFIG_VCT_NOR) +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_FLASH_NOT_MEM_MAPPED + +/* + * We need special accessor functions for the CFI FLASH driver. This + * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option. + */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* + * For the non-memory-mapped NOR FLASH, we need to define the + * NOR FLASH area. This can't be detected via the addr2info() + * function, since we check for flash access in the very early + * U-Boot code, before the NOR FLASH is detected. + */ +#define CONFIG_FLASH_BASE 0xb0000000 +#define CONFIG_FLASH_END 0xbfffffff + +/* + * CFI driver settings + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ + +#define CONFIG_SYS_FLASH_BASE 0xb0000000 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ +#endif /* CONFIG_VCT_NOR */ + +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_USE_ONENAND_BOARD_INIT +#define CONFIG_ENV_IS_IN_ONENAND +#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */ +#define CONFIG_SYS_FLASH_BASE 0x00000000 +#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */ +#define CONFIG_ENV_SIZE (128 << 10) /* erase size */ +#endif /* CONFIG_VCT_ONENAND */ + +/* + * Cache Configuration + */ +#define CONFIG_SYS_DCACHE_SIZE 16384 +#define CONFIG_SYS_ICACHE_SIZE 16384 +#define CONFIG_SYS_CACHELINE_SIZE 32 + +/* + * I2C/EEPROM + */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ + +#define CONFIG_SYS_I2C_SPEED 83000 /* 83 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0x7f + +/* + * Software (bit-bang) I2C driver configuration + */ +#define CONFIG_SYS_GPIO_I2C_SCL 11 +#define CONFIG_SYS_GPIO_I2C_SDA 10 + +#ifndef __ASSEMBLY__ +int vct_gpio_dir(int pin, int dir); +void vct_gpio_set(int pin, int val); +int vct_gpio_get(int pin); +#endif + +#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1) +#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1) +#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0) +#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA) +#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) +#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) +#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +/* CAT24WC32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ + /* 32 byte page write mode using*/ + /* last 5 bits of the address */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +#define CONFIG_BOOTCOMMAND "run test3" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +/* + * Needed for 64bit printf format + */ +#define CONFIG_SYS_64BIT_VSPRINTF 1 +#define CONFIG_SYS_64BIT_STRTOUL 1 + +/* + * UBI configuration + */ +#if defined(CONFIG_VCT_ONENAND) +#define CONFIG_SYS_USE_UBI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_JFFS2_CMDLINE + +#define MTDIDS_DEFAULT "onenand0=onenand" +#define MTDPARTS_DEFAULT "mtdparts=onenand:128k(u-boot)," \ + "128k(env)," \ + "20m(kernel)," \ + "-(rootfs)" +#endif + +/* + * We need a small, stripped down image to fit into the first 128k OneNAND + * erase block (gzipped). This image only needs basic commands for FLASH + * (NOR/OneNAND) usage and Linux kernel booting. + */ +#if defined(CONFIG_VCT_SMALL_IMAGE) +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_REGINFO +#undef CONFIG_CMD_STRINGS +#undef CONFIG_CMD_TERMINAL +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_CRC32 +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADY +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_FAT + +#undef CONFIG_DRIVER_SMC911X +#undef CONFIG_SOFT_I2C +#undef CONFIG_AUTOSCRIPT +#undef CONFIG_SYS_LONGHELP +#undef CONFIG_TIMESTAMP +#endif /* CONFIG_VCT_SMALL_IMAGE */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h index d81242165..852becb36 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -108,7 +108,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_MEMORY #define CONFIG_CMD_FLASH -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV /* diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 38b0a4e94..7b61c82af 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -117,6 +117,7 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_IDE #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NFS diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 866b72d4c..f4606102a 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -127,7 +127,7 @@ #define CONFIG_CMD_BDI #define CONFIG_CMD_BOOTD #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ENV +#define CONFIG_CMD_SAVEENV #define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI #define CONFIG_CMD_JFFS2 diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index b70a53139..d0afd29c3 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -81,7 +81,7 @@ #undef CONFIG_SYS_CLKS_IN_HZ /* use HZ for freq. display */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 324f03e24..250247c5c 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -138,7 +138,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 400/200/100 MHz */ /* diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 16af84500..8e9d5ab7b 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -121,7 +121,7 @@ #define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ /* valid baudrates */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index b72741375..676143865 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -35,10 +35,7 @@ #define CONFIG_DOS_PARTITION 1 #define BOARD_LATE_INIT 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ @@ -118,7 +115,6 @@ */ #include <config_cmd_default.h> -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_PING #define CONFIG_CMD_JFFS2 @@ -145,9 +141,14 @@ #define CONFIG_SYS_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */ #undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ -#define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_SYS_LOAD_ADDR 0xA0000000 /* load kernel to this address */ +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif + /* Stack sizes - The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 53397d807..6febeeafa 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -41,7 +41,7 @@ #ifdef CONFIG_LCD #define CONFIG_SHARP_LM8V31 #endif -/* #define CONFIG_MMC 1 */ +#undef CONFIG_MMC #define BOARD_LATE_INIT 1 #undef CONFIG_SKIP_RELOCATE_UBOOT @@ -94,7 +94,7 @@ #ifdef TURN_ON_ETHERNET #define CONFIG_CMD_PING #else - #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NAND #undef CONFIG_CMD_NET @@ -143,7 +143,7 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ -#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */ +#define CONFIG_SYS_HZ 1000 /* Monahans Core Frequency */ #define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ @@ -152,7 +152,11 @@ /* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* #define CONFIG_SYS_MMC_BASE 0xF0000000 */ +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif /* * Stack sizes @@ -227,7 +231,6 @@ #define NAND_ChipID_UNKNOWN 0x00 #define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NO_FLASH 1 diff --git a/include/devices.h b/include/devices.h index 6b78d5888..3a9881bf0 100644 --- a/include/devices.h +++ b/include/devices.h @@ -91,11 +91,16 @@ extern char *stdio_names[MAX_FILES]; */ int device_register (device_t * dev); int devices_init (void); +#ifdef CONFIG_SYS_DEVICE_DEREGISTER int device_deregister(char *devname); +#endif struct list_head* device_get_list(void); device_t* device_get_by_name(char* name); device_t* device_clone(device_t *dev); +#ifdef CONFIG_ARM_DCC_MULTI +int drv_arm_dcc_init(void); +#endif #ifdef CONFIG_LCD int drv_lcd_init (void); #endif @@ -114,5 +119,8 @@ int drv_usbtty_init (void); #ifdef CONFIG_NETCONSOLE int drv_nc_init (void); #endif +#ifdef CONFIG_JTAG_CONSOLE +int drv_jtag_console_init (void); +#endif #endif /* _DEVICES_H_ */ diff --git a/include/div64.h b/include/div64.h index c495aefb0..d83314435 100644 --- a/include/div64.h +++ b/include/div64.h @@ -36,4 +36,14 @@ extern uint32_t __div64_32(uint64_t *dividend, uint32_t divisor); __rem; \ }) +/* Wrapper for do_div(). Doesn't modify dividend and returns + * the result, not reminder. + */ +static inline uint64_t lldiv(uint64_t dividend, uint32_t divisor) +{ + uint64_t __res = dividend; + do_div(__res, divisor); + return(__res); +} + #endif /* _ASM_GENERIC_DIV64_H */ diff --git a/include/ds4510.h b/include/ds4510.h new file mode 100644 index 000000000..40480afc9 --- /dev/null +++ b/include/ds4510.h @@ -0,0 +1,75 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __DS4510_H_ +#define __DS4510_H_ + +/* General defines */ +#define DS4510_NUM_IO 0x04 +#define DS4510_IO_MASK ((1 << DS4510_NUM_IO) - 1) +#define DS4510_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* EEPROM from 0x00 - 0x39 */ +#define DS4510_EEPROM 0x00 +#define DS4510_EEPROM_SIZE 0x40 +#define DS4510_EEPROM_PAGE_SIZE 0x08 +#define DS4510_EEPROM_PAGE_OFFSET(x) ((x) & (DS4510_EEPROM_PAGE_SIZE - 1)) + +/* SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_SEEPROM 0xf0 +#define DS4510_SEEPROM_SIZE 0x08 + +/* Registers overlapping SEEPROM from 0xf0 - 0xf7 */ +#define DS4510_PULLUP 0xF0 +#define DS4510_PULLUP_DIS 0x00 +#define DS4510_PULLUP_EN 0x01 +#define DS4510_RSTDELAY 0xF1 +#define DS4510_RSTDELAY_MASK 0x03 +#define DS4510_RSTDELAY_125 0x00 +#define DS4510_RSTDELAY_250 0x01 +#define DS4510_RSTDELAY_500 0x02 +#define DS4510_RSTDELAY_1000 0x03 +#define DS4510_IO3 0xF4 +#define DS4510_IO2 0xF5 +#define DS4510_IO1 0xF6 +#define DS4510_IO0 0xF7 + +/* Status configuration registers from 0xf8 - 0xf9*/ +#define DS4510_IO_STATUS 0xF8 +#define DS4510_CFG 0xF9 +#define DS4510_CFG_READY 0x80 +#define DS4510_CFG_TRIP_POINT 0x40 +#define DS4510_CFG_RESET 0x20 +#define DS4510_CFG_SEE 0x10 +#define DS4510_CFG_SWRST 0x08 + +/* SRAM from 0xfa - 0xff */ +#define DS4510_SRAM 0xfa +#define DS4510_SRAM_SIZE 0x06 + +int ds4510_mem_write(uint8_t chip, int offset, uint8_t *buf, int count); +int ds4510_mem_read(uint8_t chip, int offset, uint8_t *buf, int count); +int ds4510_see_write(uint8_t chip, uint8_t nv); +int ds4510_rstdelay_write(uint8_t chip, uint8_t delay); +int ds4510_pullup_write(uint8_t chip, uint8_t val); +int ds4510_pullup_read(uint8_t chip); +int ds4510_gpio_write(uint8_t chip, uint8_t val); +int ds4510_gpio_read(uint8_t chip); +int ds4510_gpio_read_val(uint8_t chip); + +#endif /* __DS4510_H_ */ diff --git a/include/e500.h b/include/e500.h index 1971eee29..4c5eeb74e 100644 --- a/include/e500.h +++ b/include/e500.h @@ -8,11 +8,16 @@ #ifndef __ASSEMBLY__ +#ifndef CONFIG_NUM_CPUS +#define CONFIG_NUM_CPUS 1 +#endif + typedef struct { - unsigned long freqProcessor; + unsigned long freqProcessor[CONFIG_NUM_CPUS]; unsigned long freqSystemBus; unsigned long freqDDRBus; + unsigned long freqLocalBus; } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ diff --git a/include/flash.h b/include/flash.h index 6e2981c5a..8b8979e2f 100644 --- a/include/flash.h +++ b/include/flash.h @@ -33,7 +33,7 @@ typedef struct { ulong size; /* total bank size in bytes */ ushort sector_count; /* number of erase units */ ulong flash_id; /* combined device & manufacturer code */ - ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* physical sector start addresses */ + ulong start[CONFIG_SYS_MAX_FLASH_SECT]; /* virtual sector start address */ uchar protect[CONFIG_SYS_MAX_FLASH_SECT]; /* sector protection status */ #ifdef CONFIG_SYS_FLASH_CFI uchar portwidth; /* the width of the port */ @@ -124,6 +124,9 @@ extern int jedec_flash_match(flash_info_t *info, ulong base); #define CFI_CMDSET_AMD_LEGACY 0xFFF0 #endif +#if defined(CONFIG_SYS_FLASH_CFI) +extern flash_info_t *flash_get_info(ulong base); +#endif /*----------------------------------------------------------------------- * return codes from flash_write(): diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h new file mode 100644 index 000000000..0a5c5d626 --- /dev/null +++ b/include/fsl_esdhc.h @@ -0,0 +1,145 @@ +/* + * FSL SD/MMC Defines + *------------------------------------------------------------------- + * + * Copyright 2007-2008, Freescale Semiconductor, Inc + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + *------------------------------------------------------------------- + * + */ + +#ifndef __FSL_ESDHC_H__ +#define __FSL_ESDHC_H__ + +/* FSL eSDHC-specific constants */ +#define SYSCTL 0x0002e02c +#define SYSCTL_INITA 0x08000000 +#define SYSCTL_TIMEOUT_MASK 0x000f0000 +#define SYSCTL_CLOCK_MASK 0x00000fff +#define SYSCTL_PEREN 0x00000004 +#define SYSCTL_HCKEN 0x00000002 +#define SYSCTL_IPGEN 0x00000001 + +#define IRQSTAT 0x0002e030 +#define IRQSTAT_DMAE (0x10000000) +#define IRQSTAT_AC12E (0x01000000) +#define IRQSTAT_DEBE (0x00400000) +#define IRQSTAT_DCE (0x00200000) +#define IRQSTAT_DTOE (0x00100000) +#define IRQSTAT_CIE (0x00080000) +#define IRQSTAT_CEBE (0x00040000) +#define IRQSTAT_CCE (0x00020000) +#define IRQSTAT_CTOE (0x00010000) +#define IRQSTAT_CINT (0x00000100) +#define IRQSTAT_CRM (0x00000080) +#define IRQSTAT_CINS (0x00000040) +#define IRQSTAT_BRR (0x00000020) +#define IRQSTAT_BWR (0x00000010) +#define IRQSTAT_DINT (0x00000008) +#define IRQSTAT_BGE (0x00000004) +#define IRQSTAT_TC (0x00000002) +#define IRQSTAT_CC (0x00000001) + +#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE) +#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE) + +#define IRQSTATEN 0x0002e034 +#define IRQSTATEN_DMAE (0x10000000) +#define IRQSTATEN_AC12E (0x01000000) +#define IRQSTATEN_DEBE (0x00400000) +#define IRQSTATEN_DCE (0x00200000) +#define IRQSTATEN_DTOE (0x00100000) +#define IRQSTATEN_CIE (0x00080000) +#define IRQSTATEN_CEBE (0x00040000) +#define IRQSTATEN_CCE (0x00020000) +#define IRQSTATEN_CTOE (0x00010000) +#define IRQSTATEN_CINT (0x00000100) +#define IRQSTATEN_CRM (0x00000080) +#define IRQSTATEN_CINS (0x00000040) +#define IRQSTATEN_BRR (0x00000020) +#define IRQSTATEN_BWR (0x00000010) +#define IRQSTATEN_DINT (0x00000008) +#define IRQSTATEN_BGE (0x00000004) +#define IRQSTATEN_TC (0x00000002) +#define IRQSTATEN_CC (0x00000001) + +#define PRSSTAT 0x0002e024 +#define PRSSTAT_CLSL (0x00800000) +#define PRSSTAT_WPSPL (0x00080000) +#define PRSSTAT_CDPL (0x00040000) +#define PRSSTAT_CINS (0x00010000) +#define PRSSTAT_BREN (0x00000800) +#define PRSSTAT_DLA (0x00000004) +#define PRSSTAT_CICHB (0x00000002) +#define PRSSTAT_CIDHB (0x00000001) + +#define PROCTL 0x0002e028 +#define PROCTL_INIT 0x00000020 +#define PROCTL_DTW_4 0x00000002 +#define PROCTL_DTW_8 0x00000004 + +#define CMDARG 0x0002e008 + +#define XFERTYP 0x0002e00c +#define XFERTYP_CMD(x) ((x & 0x3f) << 24) +#define XFERTYP_CMDTYP_NORMAL 0x0 +#define XFERTYP_CMDTYP_SUSPEND 0x00400000 +#define XFERTYP_CMDTYP_RESUME 0x00800000 +#define XFERTYP_CMDTYP_ABORT 0x00c00000 +#define XFERTYP_DPSEL 0x00200000 +#define XFERTYP_CICEN 0x00100000 +#define XFERTYP_CCCEN 0x00080000 +#define XFERTYP_RSPTYP_NONE 0 +#define XFERTYP_RSPTYP_136 0x00010000 +#define XFERTYP_RSPTYP_48 0x00020000 +#define XFERTYP_RSPTYP_48_BUSY 0x00030000 +#define XFERTYP_MSBSEL 0x00000020 +#define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_AC12EN 0x00000004 +#define XFERTYP_BCEN 0x00000002 +#define XFERTYP_DMAEN 0x00000001 + +#define CINS_TIMEOUT 1000 + +#define DSADDR 0x2e004 + +#define CMDRSP0 0x2e010 +#define CMDRSP1 0x2e014 +#define CMDRSP2 0x2e018 +#define CMDRSP3 0x2e01c + +#define DATPORT 0x2e020 + +#define WML 0x2e044 +#define WML_WRITE 0x00010000 + +#define BLKATTR 0x2e004 +#define BLKATTR_CNT(x) ((x & 0xffff) << 16) +#define BLKATTR_SIZE(x) (x & 0x1fff) +#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */ + +#define ESDHC_HOSTCAPBLT_VS18 0x04000000 +#define ESDHC_HOSTCAPBLT_VS30 0x02000000 +#define ESDHC_HOSTCAPBLT_VS33 0x01000000 +#define ESDHC_HOSTCAPBLT_SRS 0x00800000 +#define ESDHC_HOSTCAPBLT_DMAS 0x00400000 +#define ESDHC_HOSTCAPBLT_HSS 0x00200000 + +int fsl_esdhc_mmc_init(bd_t *bis); + +#endif /* __FSL_ESDHC_H__ */ diff --git a/include/i2c.h b/include/i2c.h index fad2d5716..f8a59a669 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -159,14 +159,7 @@ static inline u8 i2c_reg_read(u8 addr, u8 reg) printf("%s: addr=0x%02x, reg=0x%02x\n", __func__, addr, reg); #endif -#ifdef CONFIG_BLACKFIN - /* This ifdef will become unneccessary in a future version of the - * blackfin I2C driver. - */ - i2c_read(addr, reg, 0, &buf, 1); -#else i2c_read(addr, reg, 1, &buf, 1); -#endif return buf; } @@ -183,14 +176,7 @@ static inline void i2c_reg_write(u8 addr, u8 reg, u8 val) __func__, addr, reg, val); #endif -#ifdef CONFIG_BLACKFIN - /* This ifdef will become unneccessary in a future version of the - * blackfin I2C driver. - */ - i2c_write(addr, reg, 0, &val, 1); -#else i2c_write(addr, reg, 1, &val, 1); -#endif } /* diff --git a/include/image.h b/include/image.h index 4609200b8..74a124006 100644 --- a/include/image.h +++ b/include/image.h @@ -338,23 +338,23 @@ static inline uint32_t image_get_header_size (void) { \ return uimage_to_cpu (hdr->ih_##f); \ } -image_get_hdr_l (magic); -image_get_hdr_l (hcrc); -image_get_hdr_l (time); -image_get_hdr_l (size); -image_get_hdr_l (load); -image_get_hdr_l (ep); -image_get_hdr_l (dcrc); +image_get_hdr_l (magic); /* image_get_magic */ +image_get_hdr_l (hcrc); /* image_get_hcrc */ +image_get_hdr_l (time); /* image_get_time */ +image_get_hdr_l (size); /* image_get_size */ +image_get_hdr_l (load); /* image_get_load */ +image_get_hdr_l (ep); /* image_get_ep */ +image_get_hdr_l (dcrc); /* image_get_dcrc */ #define image_get_hdr_b(f) \ static inline uint8_t image_get_##f(image_header_t *hdr) \ { \ return hdr->ih_##f; \ } -image_get_hdr_b (os); -image_get_hdr_b (arch); -image_get_hdr_b (type); -image_get_hdr_b (comp); +image_get_hdr_b (os); /* image_get_os */ +image_get_hdr_b (arch); /* image_get_arch */ +image_get_hdr_b (type); /* image_get_type */ +image_get_hdr_b (comp); /* image_get_comp */ static inline char *image_get_name (image_header_t *hdr) { @@ -396,23 +396,23 @@ static inline ulong image_get_image_end (image_header_t *hdr) { \ hdr->ih_##f = cpu_to_uimage (val); \ } -image_set_hdr_l (magic); -image_set_hdr_l (hcrc); -image_set_hdr_l (time); -image_set_hdr_l (size); -image_set_hdr_l (load); -image_set_hdr_l (ep); -image_set_hdr_l (dcrc); +image_set_hdr_l (magic); /* image_set_magic */ +image_set_hdr_l (hcrc); /* image_set_hcrc */ +image_set_hdr_l (time); /* image_set_time */ +image_set_hdr_l (size); /* image_set_size */ +image_set_hdr_l (load); /* image_set_load */ +image_set_hdr_l (ep); /* image_set_ep */ +image_set_hdr_l (dcrc); /* image_set_dcrc */ #define image_set_hdr_b(f) \ static inline void image_set_##f(image_header_t *hdr, uint8_t val) \ { \ hdr->ih_##f = val; \ } -image_set_hdr_b (os); -image_set_hdr_b (arch); -image_set_hdr_b (type); -image_set_hdr_b (comp); +image_set_hdr_b (os); /* image_set_os */ +image_set_hdr_b (arch); /* image_set_arch */ +image_set_hdr_b (type); /* image_set_type */ +image_set_hdr_b (comp); /* image_set_comp */ static inline void image_set_name (image_header_t *hdr, const char *name) { diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index abf8f1a7e..7db25465d 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -18,8 +18,8 @@ #define __LINUX_MTD_BBM_H /* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 #endif /** @@ -48,10 +48,10 @@ */ struct nand_bbt_descr { int options; - int pages[NAND_MAX_CHIPS]; + int pages[CONFIG_SYS_NAND_MAX_CHIPS]; int offs; int veroffs; - uint8_t version[NAND_MAX_CHIPS]; + uint8_t version[CONFIG_SYS_NAND_MAX_CHIPS]; int len; int maxblocks; int reserved_block_code; diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 24ad2bdaa..a4ad5711d 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -46,11 +46,6 @@ extern void nand_release (struct mtd_info *mtd); /* Internal helper for board drivers which need to override command function */ extern void nand_wait_ready(struct mtd_info *mtd); -/* The maximum number of NAND chips in an array */ -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - /* This constant declares the max. oobsize / page, which * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. @@ -477,10 +472,6 @@ struct nand_manufacturers { extern struct nand_flash_dev nand_flash_ids[]; extern struct nand_manufacturers nand_manuf_ids[]; -#ifndef NAND_MAX_CHIPS -#define NAND_MAX_CHIPS 8 -#endif - extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); extern int nand_default_bbt(struct mtd_info *mtd); diff --git a/include/linux/mtd/nand_legacy.h b/include/linux/mtd/nand_legacy.h index 99eafbbcd..433444814 100644 --- a/include/linux/mtd/nand_legacy.h +++ b/include/linux/mtd/nand_legacy.h @@ -40,6 +40,11 @@ #error This module is for the legacy NAND support #endif +/* The maximum number of NAND chips in an array */ +#ifndef CONFIG_SYS_NAND_MAX_CHIPS +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#endif + /* * Standard NAND flash commands */ diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 4467c2bb2..2597e347b 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -30,14 +30,10 @@ extern void onenand_release (struct mtd_info *mtd); /** * struct onenand_bufferram - OneNAND BufferRAM Data - * @param block block address in BufferRAM - * @param page page address in BufferRAM - * @param valid valid flag + * @param blockpage block & page address in BufferRAM */ struct onenand_bufferram { - int block; - int page; - int valid; + int blockpage; }; /** @@ -70,6 +66,8 @@ struct onenand_chip { void __iomem *base; unsigned int chipsize; unsigned int device_id; + unsigned int version_id; + unsigned int density_mask; unsigned int options; unsigned int erase_shift; @@ -81,26 +79,36 @@ struct onenand_chip { unsigned int bufferram_index; struct onenand_bufferram bufferram[MAX_BUFFERRAM]; - int (*command) (struct mtd_info * mtd, int cmd, loff_t address, + int (*command) (struct mtd_info *mtd, int cmd, loff_t address, size_t len); - int (*wait) (struct mtd_info * mtd, int state); - int (*read_bufferram) (struct mtd_info * mtd, int area, + int (*wait) (struct mtd_info *mtd, int state); + int (*bbt_wait) (struct mtd_info *mtd, int state); + int (*read_bufferram) (struct mtd_info *mtd, loff_t addr, int area, unsigned char *buffer, int offset, size_t count); - int (*write_bufferram) (struct mtd_info * mtd, int area, + int (*read_spareram) (struct mtd_info *mtd, loff_t addr, int area, + unsigned char *buffer, int offset, size_t count); + int (*write_bufferram) (struct mtd_info *mtd, loff_t addr, int area, const unsigned char *buffer, int offset, size_t count); - unsigned short (*read_word) (void __iomem * addr); - void (*write_word) (unsigned short value, void __iomem * addr); - void (*mmcontrol) (struct mtd_info * mtd, int sync_read); + unsigned short (*read_word) (void __iomem *addr); + void (*write_word) (unsigned short value, void __iomem *addr); + void (*mmcontrol) (struct mtd_info *mtd, int sync_read); int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); int (*scan_bbt)(struct mtd_info *mtd); + unsigned char *main_buf; + unsigned char *spare_buf; +#ifdef DONT_USE_UBOOT + spinlock_t chip_lock; + wait_queue_head_t wq; +#endif int state; - unsigned char *page_buf; - unsigned char *oob_buf; + unsigned char *page_buf; + unsigned char *oob_buf; struct nand_oobinfo *autooob; - struct nand_ecclayout *ecclayout; + int subpagesize; + struct nand_ecclayout *ecclayout; void *bbm; @@ -125,7 +133,9 @@ struct onenand_chip { /* * Options bits */ -#define ONENAND_CONT_LOCK (0x0001) +#define ONENAND_HAS_CONT_LOCK (0x0001) +#define ONENAND_HAS_UNLOCK_ALL (0x0002) +#define ONENAND_HAS_2PLANE (0x0004) #define ONENAND_PAGEBUF_ALLOC (0x1000) #define ONENAND_OOBBUF_ALLOC (0x2000) @@ -133,7 +143,6 @@ struct onenand_chip { * OneNAND Flash Manufacturer ID Codes */ #define ONENAND_MFR_SAMSUNG 0xec -#define ONENAND_MFR_UNKNOWN 0x00 /** * struct nand_manufacturers - NAND Flash Manufacturer ID Structure diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index a245e14bf..fc63380d9 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -119,6 +119,7 @@ #define ONENAND_CMD_UNLOCK (0x23) #define ONENAND_CMD_LOCK (0x2A) #define ONENAND_CMD_LOCK_TIGHT (0x2C) +#define ONENAND_CMD_UNLOCK_ALL (0x27) #define ONENAND_CMD_ERASE (0x94) #define ONENAND_CMD_RESET (0xF0) #define ONENAND_CMD_READID (0x90) diff --git a/include/mb862xx.h b/include/mb862xx.h index 1af567002..164305fbb 100644 --- a/include/mb862xx.h +++ b/include/mb862xx.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License diff --git a/include/mmc.h b/include/mmc.h index 19c76fe4c..b9b27ba18 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -1,6 +1,8 @@ /* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * Copyright 2008, Freescale Semiconductor, Inc + * Andy Fleming + * + * Based (loosely) on the Linux code * * See file CREDITS for list of people who contributed to this * project. @@ -23,35 +25,255 @@ #ifndef _MMC_H_ #define _MMC_H_ -#include <asm/arch/mmc.h> -/* MMC command numbers */ +#include <linux/list.h> + +#define SD_VERSION_SD 0x20000 +#define SD_VERSION_2 (SD_VERSION_SD | 0x20) +#define SD_VERSION_1_0 (SD_VERSION_SD | 0x10) +#define SD_VERSION_1_10 (SD_VERSION_SD | 0x1a) +#define MMC_VERSION_MMC 0x10000 +#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) +#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x12) +#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x14) +#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x22) +#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30) +#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40) + +#define MMC_MODE_HS 0x001 +#define MMC_MODE_HS_52MHz 0x010 +#define MMC_MODE_4BIT 0x100 +#define MMC_MODE_8BIT 0x200 + +#define SD_DATA_4BIT 0x00040000 + +#define IS_SD(x) (mmc->version & SD_VERSION_SD) + +#define MMC_DATA_READ 1 +#define MMC_DATA_WRITE 2 + +#define NO_CARD_ERR -16 /* No SD/MMC card inserted */ +#define UNUSABLE_ERR -17 /* Unusable Card */ +#define COMM_ERR -18 /* Communications Error */ +#define TIMEOUT -19 + #define MMC_CMD_GO_IDLE_STATE 0 #define MMC_CMD_SEND_OP_COND 1 #define MMC_CMD_ALL_SEND_CID 2 #define MMC_CMD_SET_RELATIVE_ADDR 3 #define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SWITCH 6 #define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_EXT_CSD 8 #define MMC_CMD_SEND_CSD 9 #define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 #define MMC_CMD_SEND_STATUS 13 #define MMC_CMD_SET_BLOCKLEN 16 #define MMC_CMD_READ_SINGLE_BLOCK 17 #define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_WRITE_SINGLE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 #define MMC_CMD_APP_CMD 55 -/* SD Card command numbers */ #define SD_CMD_SEND_RELATIVE_ADDR 3 -#define SD_CMD_SWITCH 6 +#define SD_CMD_SWITCH_FUNC 6 #define SD_CMD_SEND_IF_COND 8 #define SD_CMD_APP_SET_BUS_WIDTH 6 #define SD_CMD_APP_SEND_OP_COND 41 +#define SD_CMD_APP_SEND_SCR 51 + +/* SCR definitions in different words */ +#define SD_HIGHSPEED_BUSY 0x00020000 +#define SD_HIGHSPEED_SUPPORTED 0x00020000 + +#define MMC_HS_TIMING 0x00000100 +#define MMC_HS_52MHZ 0x2 + +#define OCR_BUSY 0x80 +#define OCR_HCS 0x40000000 + +#define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */ +#define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */ +#define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */ +#define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */ +#define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */ +#define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */ +#define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */ +#define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */ +#define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */ +#define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */ +#define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */ +#define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */ +#define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */ +#define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */ +#define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */ +#define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */ +#define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */ + +#define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ +#define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte + addressed by index which are + 1 in value field */ +#define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte + addressed by index, which are + 1 in value field */ +#define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */ + +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SWITCH 1 + +/* + * EXT_CSD fields + */ + +#define EXT_CSD_BUS_WIDTH 183 /* R/W */ +#define EXT_CSD_HS_TIMING 185 /* R/W */ +#define EXT_CSD_CARD_TYPE 196 /* RO */ +#define EXT_CSD_REV 192 /* RO */ +#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ + +/* + * EXT_CSD field definitions + */ + +#define EXT_CSD_CMD_SET_NORMAL (1<<0) +#define EXT_CSD_CMD_SET_SECURE (1<<1) +#define EXT_CSD_CMD_SET_CPSECURE (1<<2) + +#define EXT_CSD_CARD_TYPE_26 (1<<0) /* Card can run at 26MHz */ +#define EXT_CSD_CARD_TYPE_52 (1<<1) /* Card can run at 52MHz */ + +#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ +#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ +#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#define MMC_RSP_PRESENT (1 << 0) +#define MMC_RSP_136 (1 << 1) /* 136 bit response */ +#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ +#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ +#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ + +#define MMC_RSP_NONE (0) +#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \ + MMC_RSP_BUSY) +#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) +#define MMC_RSP_R3 (MMC_RSP_PRESENT) +#define MMC_RSP_R4 (MMC_RSP_PRESENT) +#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) +#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) + + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +struct mmc_cmd { + ushort cmdidx; + uint resp_type; + uint cmdarg; + char response[18]; + uint flags; +}; + +struct mmc_data { + union { + char *dest; + const char *src; /* src buffers don't get written to */ + }; + uint flags; + uint blocks; + uint blocksize; +}; + +struct mmc { + struct list_head link; + char name[32]; + void *priv; + uint voltages; + uint version; + uint f_min; + uint f_max; + int high_capacity; + uint bus_width; + uint clock; + uint card_caps; + uint host_caps; + uint ocr; + uint scr[2]; + uint csd[4]; + char cid[16]; + ushort rca; + uint tran_speed; + uint read_bl_len; + uint write_bl_len; + u64 capacity; + block_dev_desc_t block_dev; + int (*send_cmd)(struct mmc *mmc, + struct mmc_cmd *cmd, struct mmc_data *data); + void (*set_ios)(struct mmc *mmc); + int (*init)(struct mmc *mmc); +}; -int mmc_init(int verbose); -int mmc_read(ulong src, uchar *dst, int size); -int mmc_write(uchar *src, ulong dst, int size); -int mmc2info(ulong addr); +int mmc_register(struct mmc *mmc); +int mmc_initialize(bd_t *bis); +int mmc_init(struct mmc *mmc); +int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size); +struct mmc *find_mmc_device(int dev_num); +void print_mmc_devices(char separator); +#ifndef CONFIG_GENERIC_MMC +int mmc_legacy_init(int verbose); +#endif #endif /* _MMC_H_ */ diff --git a/include/mpc512x.h b/include/mpc512x.h index 05a206358..0f022939d 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -573,6 +573,31 @@ void iopin_initialize(iopin_t *,int); /* Register Offset Base */ #define MPC512X_FEC (CONFIG_SYS_IMMR + 0x02800) +#define MPC512X_PATA (CONFIG_SYS_IMMR + 0x10200) + +/* IIM control */ +#define IIM_SET_UA(bk, f) ((bk << 3) | (f >> 5)) +#define IIM_SET_LA(f, bit) (((f & 0x0000001f) << 3) | bit) +#define IIM_STAT_BUSY 0x00000080 +#define IIM_STAT_PRGD 0x00000002 +#define IIM_STAT_SNSD 0x00000001 +#define IIM_ERR_WPE 0x00000040 +#define IIM_ERR_OPE 0x00000020 +#define IIM_ERR_RPE 0x00000010 +#define IIM_ERR_WLRE 0x00000008 +#define IIM_ERR_SNSE 0x00000004 +#define IIM_ERR_PARITYE 0x00000002 +#define IIM_PRG_P_SET 0x000000aa +#define IIM_PRG_P_UNSET 0 +#define IIM_FCTL_PROG_PULSE 0x00000020 +#define IIM_FCTL_PROG 0x00000001 +#define IIM_FCTL_ESNS_N 0x00000008 +#define IIM_FBAC_FBWP 0x00000080 +#define IIM_FBAC_FBOP 0x00000040 +#define IIM_FBAC_FBRP 0x00000020 +#define IIM_FBAC_FBESP 0x00000008 +#define IIM_PROTECTION 0x000000e8 +#define IIM_FMAX 31 /* Number of I2C buses */ #define I2C_BUS_CNT 3 diff --git a/include/mpc824x.h b/include/mpc824x.h index 5aa9370b1..fca9371bd 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -451,45 +451,6 @@ #define MICR_EADDR_MASK 0x30000000 #define MICR_EADDR_SHIFT 28 -#define BATU_BEPI_MSK 0xfffe0000 -#define BATU_BL_MSK 0x00001ffc - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 - -#define BATL_BRPN_MSK 0xfffe0000 -#define BATL_WIMG_MSK 0x00000078 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -/* - * I'd attempt to do defines for the PP bits, but it's use is a bit - * too complex, see the PowerPC Operating Environment Architecture - * section in the PowerPc arch book, chapter 4. - */ - /*eumb and epic config*/ #define EPIC_FPR 0x00041000 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 43553f5ae..3554fdd4e 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -266,6 +266,7 @@ /* SICRL bits - MPC837x specific */ #define SICRL_USB_A 0xC0000000 #define SICRL_USB_B 0x30000000 +#define SICRL_USB_B_SD 0x20000000 #define SICRL_UART 0x0C000000 #define SICRL_GPIO_A 0x02000000 #define SICRL_GPIO_B 0x01000000 @@ -307,10 +308,12 @@ #define SICRH_GPIO2_C 0x00002000 #define SICRH_GPIO2_D 0x00001000 #define SICRH_GPIO2_E 0x00000C00 +#define SICRH_GPIO2_E_SD 0x00000800 #define SICRH_GPIO2_F 0x00000300 #define SICRH_GPIO2_G 0x000000C0 #define SICRH_GPIO2_H 0x00000030 #define SICRH_SPI 0x00000003 +#define SICRH_SPI_SD 0x00000001 #endif /* SWCRR - System Watchdog Control Register @@ -751,9 +754,6 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 -#define SCCR_PCIEXP1CM 0x00300000 -#define SCCR_PCIEXP2CM 0x000c0000 - #define SCCR_SATA1CM 0x00003000 #define SCCR_SATA1CM_SHIFT 12 #define SCCR_SATACM 0x00003c00 @@ -800,6 +800,17 @@ #define SCCR_USBDRCM_2 0x00800000 #define SCCR_USBDRCM_3 0x00c00000 +/* All of the four SATA controllers must have the same clock ratio */ +#define SCCR_SATA1CM 0x000000c0 +#define SCCR_SATA1CM_SHIFT 6 +#define SCCR_SATACM 0x000000ff +#define SCCR_SATACM_SHIFT 0 +#define SCCR_SATACM_0 0x00000000 +#define SCCR_SATACM_1 0x00000055 +#define SCCR_SATACM_2 0x000000aa +#define SCCR_SATACM_3 0x000000ff +#endif + #define SCCR_PCIEXP1CM 0x00300000 #define SCCR_PCIEXP1CM_SHIFT 20 #define SCCR_PCIEXP1CM_0 0x00000000 @@ -814,17 +825,6 @@ #define SCCR_PCIEXP2CM_2 0x00080000 #define SCCR_PCIEXP2CM_3 0x000c0000 -/* All of the four SATA controllers must have the same clock ratio */ -#define SCCR_SATA1CM 0x000000c0 -#define SCCR_SATA1CM_SHIFT 6 -#define SCCR_SATACM 0x000000ff -#define SCCR_SATACM_SHIFT 0 -#define SCCR_SATACM_0 0x00000000 -#define SCCR_SATACM_1 0x00000055 -#define SCCR_SATACM_2 0x000000aa -#define SCCR_SATACM_3 0x000000ff -#endif - /* CSn_BDNS - Chip Select memory Bounds Register */ #define CSBNDS_SA 0x00FF0000 @@ -1170,9 +1170,52 @@ #define DDRCDR_M_ODR 0x00000002 #define DDRCDR_Q_DRN 0x00000001 +/* PCIE Bridge Register +*/ +#define PEX_CSB_CTRL_OBPIOE 0x00000001 +#define PEX_CSB_CTRL_IBPIOE 0x00000002 +#define PEX_CSB_CTRL_WDMAE 0x00000004 +#define PEX_CSB_CTRL_RDMAE 0x00000008 + +#define PEX_CSB_OBCTRL_PIOE 0x00000001 +#define PEX_CSB_OBCTRL_MEMWE 0x00000002 +#define PEX_CSB_OBCTRL_IOWE 0x00000004 +#define PEX_CSB_OBCTRL_CFGWE 0x00000008 + +#define PEX_CSB_IBCTRL_PIOE 0x00000001 + +#define PEX_OWAR_EN 0x00000001 +#define PEX_OWAR_TYPE_CFG 0x00000000 +#define PEX_OWAR_TYPE_IO 0x00000002 +#define PEX_OWAR_TYPE_MEM 0x00000004 +#define PEX_OWAR_RLXO 0x00000008 +#define PEX_OWAR_NANP 0x00000010 +#define PEX_OWAR_SIZE 0xFFFFF000 + +#define PEX_IWAR_EN 0x00000001 +#define PEX_IWAR_TYPE_INT 0x00000000 +#define PEX_IWAR_TYPE_PF 0x00000004 +#define PEX_IWAR_TYPE_NO_PF 0x00000006 +#define PEX_IWAR_NSOV 0x00000008 +#define PEX_IWAR_NSNP 0x00000010 +#define PEX_IWAR_SIZE 0xFFFFF000 +#define PEX_IWAR_SIZE_1M 0x000FF000 +#define PEX_IWAR_SIZE_2M 0x001FF000 +#define PEX_IWAR_SIZE_4M 0x003FF000 +#define PEX_IWAR_SIZE_8M 0x007FF000 +#define PEX_IWAR_SIZE_16M 0x00FFF000 +#define PEX_IWAR_SIZE_32M 0x01FFF000 +#define PEX_IWAR_SIZE_64M 0x03FFF000 +#define PEX_IWAR_SIZE_128M 0x07FFF000 +#define PEX_IWAR_SIZE_256M 0x0FFFF000 + +#define PEX_GCLK_RATIO 0x440 + #ifndef __ASSEMBLY__ struct pci_region; void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); +void mpc83xx_pcislave_unlock(int bus); +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); #endif #endif /* __MPC83XX_H__ */ diff --git a/include/mpc86xx.h b/include/mpc86xx.h index f119d5bb1..c6f30f9fd 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -34,47 +34,6 @@ #define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ #define L2CR_L2IP 0x00000001 /* global invalidate in progress */ -/* - * BAT settings. Look in config_<BOARD>.h for the actual setup - */ - -#define BATU_BL_128K 0x00000000 -#define BATU_BL_256K 0x00000004 -#define BATU_BL_512K 0x0000000c -#define BATU_BL_1M 0x0000001c -#define BATU_BL_2M 0x0000003c -#define BATU_BL_4M 0x0000007c -#define BATU_BL_8M 0x000000fc -#define BATU_BL_16M 0x000001fc -#define BATU_BL_32M 0x000003fc -#define BATU_BL_64M 0x000007fc -#define BATU_BL_128M 0x00000ffc -#define BATU_BL_256M 0x00001ffc -#define BATU_BL_512M 0x00003ffc -#define BATU_BL_1G 0x00007ffc -#define BATU_BL_2G 0x0000fffc -#define BATU_BL_4G 0x0001fffc - -#define BATU_VS 0x00000002 -#define BATU_VP 0x00000001 -#define BATU_INVALID 0x00000000 - -#define BATL_WRITETHROUGH 0x00000040 -#define BATL_CACHEINHIBIT 0x00000020 -#define BATL_MEMCOHERENCE 0x00000010 -#define BATL_GUARDEDSTORAGE 0x00000008 -#define BATL_NO_ACCESS 0x00000000 - -#define BATL_PP_MSK 0x00000003 -#define BATL_PP_00 0x00000000 /* No access */ -#define BATL_PP_01 0x00000001 /* Read-only */ -#define BATL_PP_10 0x00000002 /* Read-write */ -#define BATL_PP_11 0x00000003 - -#define BATL_PP_NO_ACCESS BATL_PP_00 -#define BATL_PP_RO BATL_PP_01 -#define BATL_PP_RW BATL_PP_10 - #define HID0_XBSEN 0x00000100 #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000 @@ -84,6 +43,7 @@ typedef struct { unsigned long freqProcessor; unsigned long freqSystemBus; + unsigned long freqLocalBus; } MPC86xx_SYS_INFO; #define l1icache_enable icache_enable diff --git a/include/nand.h b/include/nand.h index b4f316f71..065a42c3e 100644 --- a/include/nand.h +++ b/include/nand.h @@ -31,6 +31,8 @@ extern void nand_init(void); #include <linux/mtd/mtd.h> #include <linux/mtd/nand.h> +extern int board_nand_init(struct nand_chip *nand); + typedef struct mtd_info nand_info_t; extern int nand_curr_device; diff --git a/include/net.h b/include/net.h index d2d394f0d..b192db193 100644 --- a/include/net.h +++ b/include/net.h @@ -109,25 +109,26 @@ struct eth_device { void *priv; }; -extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ -extern int eth_register(struct eth_device* dev);/* Register network device */ -extern void eth_try_another(int first_restart); /* Change the device */ +extern int eth_initialize(bd_t *bis); /* Initialize network subsystem */ +extern int eth_register(struct eth_device* dev);/* Register network device */ +extern void eth_try_another(int first_restart); /* Change the device */ #ifdef CONFIG_NET_MULTI -extern void eth_set_current(void); /* set nterface to ethcur var. */ +extern void eth_set_current(void); /* set nterface to ethcur var */ #endif -extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ -extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ -extern int eth_get_dev_index (void); /* get the device index */ -extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ - -extern int eth_init(bd_t *bis); /* Initialize the device */ -extern int eth_send(volatile void *packet, int length); /* Send a packet */ +extern struct eth_device *eth_get_dev(void); /* get the current device MAC */ +extern struct eth_device *eth_get_dev_by_name(char *devname); /* get device */ +extern struct eth_device *eth_get_dev_by_index(int index); /* get dev @ index */ +extern int eth_get_dev_index (void); /* get the device index */ +extern void eth_set_enetaddr(int num, char* a); /* Set new MAC address */ + +extern int eth_init(bd_t *bis); /* Initialize the device */ +extern int eth_send(volatile void *packet, int length); /* Send a packet */ #ifdef CONFIG_API -extern int eth_receive(volatile void *packet, int length); /* Receive a packet */ +extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/ #endif -extern int eth_rx(void); /* Check for received packets */ -extern void eth_halt(void); /* stop SCC */ -extern char *eth_get_name(void); /* get name of current device */ +extern int eth_rx(void); /* Check for received packets */ +extern void eth_halt(void); /* stop SCC */ +extern char *eth_get_name(void); /* get name of current device */ #ifdef CONFIG_MCAST_TFTP int eth_mcast_join( IPaddr_t mcast_addr, u8 join); @@ -474,6 +475,22 @@ static inline int is_multicast_ether_addr(const u8 *addr) return (0x01 & addr[0]); } +/** + * is_valid_ether_addr - Determine if the given Ethernet address is valid + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Check that the Ethernet address (MAC) is not 00:00:00:00:00:00, is not + * a multicast address, and is not FF:FF:FF:FF:FF:FF. + * + * Return true if the address is valid. + */ +static inline int is_valid_ether_addr(const u8 * addr) +{ + /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to + * explicitly check for it here. */ + return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); +} + /* Convert an IP address to a string */ extern void ip_to_string (IPaddr_t x, char *s); diff --git a/include/netdev.h b/include/netdev.h index 751f0dab5..2794ddd57 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -12,7 +12,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -44,6 +44,7 @@ int cpu_eth_init(bd_t *bis); int au1x00_enet_initialize(bd_t*); int bfin_EMAC_initialize(bd_t *bis); int dc21x4x_initialize(bd_t *bis); +int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr); int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); int eth_3com_initialize (bd_t * bis); @@ -57,6 +58,7 @@ int mcffec_initialize(bd_t *bis); int mpc512x_fec_initialize(bd_t *bis); int mpc5xxx_fec_initialize(bd_t *bis); int mpc8220_fec_initialize(bd_t *bis); +int mpc82xx_scc_enet_initialize(bd_t *bis); int natsemi_initialize(bd_t *bis); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); @@ -70,6 +72,7 @@ int skge_initialize(bd_t *bis); int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uli526x_initialize(bd_t *bis); +int sh_eth_initialize(bd_t *bis); /* Boards with PCI network controllers can call this from their board_eth_init() * function to initialize whatever's on board. diff --git a/include/nomadik.h b/include/nomadik.h new file mode 100644 index 000000000..d9405fd28 --- /dev/null +++ b/include/nomadik.h @@ -0,0 +1,39 @@ +/* Collection of constants used to access Nomadik registers */ + +#ifndef __NOMADIK_H__ +#define __NOMADIK_H__ + +/* Base addresses of our peripherals */ +#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ +#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ +#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ +#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ +#define NOMADIK_1NAND_BASE 0x30000000 +#define NOMADIK_GPIO0_BASE 0x101E4000 +#define NOMADIK_GPIO1_BASE 0x101E5000 +#define NOMADIK_GPIO2_BASE 0x101E6000 +#define NOMADIK_GPIO3_BASE 0x101E7000 +#define NOMADIK_CPLD_BASE 0x36000000 +#define NOMADIK_UART0_BASE 0x101FD000 +#define NOMADIK_UART1_BASE 0x101FB000 +#define NOMADIK_UART2_BASE 0x101F2000 + +#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ +#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ + +#define NOMADIK_RTC_BASE 0x101E8000 +#define NOMADIK_ETH0_BASE 0x36800300 +#define NOMADIK_CPLD_UART_BASE 0x36480000 + +/* Chip select registers ("Flexible Static Memory Controller") */ + +#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00) +#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04) +#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08) +#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c) +#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40) +#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48) +#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c) +#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54) + +#endif /* __NOMADIK_H__ */ diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index e9602574b..49da9d08b 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -15,25 +15,31 @@ #define __UBOOT_ONENAND_H #include <linux/types.h> -#include <linux/mtd/mtd.h> +/* Forward declarations */ struct mtd_info; +struct mtd_oob_ops; struct erase_info; +struct onenand_chip; extern struct mtd_info onenand_mtd; +/* board */ +extern void onenand_board_init(struct mtd_info *); + /* Functions */ extern void onenand_init(void); extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); -extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, - struct mtd_oob_ops *ops); +extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, const u_char * buf); extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr); -extern int onenand_unlock(struct mtd_info *mtd, loff_t ofs, size_t len); +extern char *onenand_print_device_info(int device, int version); -extern char *onenand_print_device_info(int device); +/* S3C64xx */ +extern void s3c64xx_onenand_init(struct mtd_info *); +extern void s3c64xx_set_width_regs(struct onenand_chip *); #endif /* __UBOOT_ONENAND_H */ diff --git a/include/pca953x.h b/include/pca953x.h new file mode 100644 index 000000000..6c2b58c56 --- /dev/null +++ b/include/pca953x.h @@ -0,0 +1,39 @@ +/* + * Copyright 2008 Extreme Engineering Solutions, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PCA953X_H_ +#define __PCA953X_H_ + +#define PCA953X_IN 0x00 +#define PCA953X_OUT 0x01 +#define PCA953X_POL 0x02 +#define PCA953X_CONF 0x03 + +#define PCA953X_OUT_LOW 0 +#define PCA953X_OUT_HIGH 1 +#define PCA953X_POL_NORMAL 0 +#define PCA953X_POL_INVERT 1 +#define PCA953X_DIR_OUT 0 +#define PCA953X_DIR_IN 1 + +int pca953x_set_val(u8 chip, uint mask, uint data); +int pca953x_set_pol(u8 chip, uint mask, uint data); +int pca953x_set_dir(u8 chip, uint mask, uint data); +int pca953x_get_val(u8 chip); + +#endif /* __PCA953X_H_ */ diff --git a/include/pci.h b/include/pci.h index eebe8a8a5..d0594e316 100644 --- a/include/pci.h +++ b/include/pci.h @@ -334,7 +334,7 @@ struct pci_region { #define PCI_REGION_TYPE 0x00000001 #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */ -#define PCI_REGION_MEMORY 0x00000100 /* System memory */ +#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */ #define PCI_REGION_RO 0x00000200 /* Read-only memory */ extern __inline__ void pci_set_region(struct pci_region *reg, @@ -382,6 +382,8 @@ extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev #define MAX_PCI_REGIONS 7 +#define INDIRECT_TYPE_NO_PCIE_LINK 1 + /* * Structure of a PCI controller (host bridge) */ @@ -394,6 +396,8 @@ struct pci_controller { volatile unsigned int *cfg_addr; volatile unsigned char *cfg_data; + int indirect_type; + struct pci_region regions[MAX_PCI_REGIONS]; int region_count; @@ -450,10 +454,29 @@ extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose, #define pci_bus_to_phys(dev, addr, flags) \ pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags)) -#define pci_phys_to_mem(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) -#define pci_mem_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) -#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) -#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) +#define pci_virt_to_bus(dev, addr, flags) \ + pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \ + (virt_to_phys(addr)), (flags)) +#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \ + map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \ + (addr), (flags)), \ + (len), (map_flags)) + +#define pci_phys_to_mem(dev, addr) \ + pci_phys_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_phys(dev, addr) \ + pci_bus_to_phys((dev), (addr), PCI_REGION_MEM) +#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO) + +#define pci_virt_to_mem(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_MEM) +#define pci_mem_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags)) +#define pci_virt_to_io(dev, addr) \ + pci_virt_to_bus((dev), (addr), PCI_REGION_IO) +#define pci_io_to_virt(dev, addr, len, map_flags) \ + pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags)) extern int pci_hose_read_config_byte(struct pci_controller *hose, pci_dev_t dev, int where, u8 *val); @@ -484,6 +507,7 @@ extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose, extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose, pci_dev_t dev, int where, u16 val); +extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); diff --git a/include/post.h b/include/post.h index 97583b7e9..fe96312cb 100644 --- a/include/post.h +++ b/include/post.h @@ -80,6 +80,19 @@ extern struct post_test post_list[]; extern unsigned int post_list_size; extern int post_hotkeys_pressed(void); +/* + * If GCC is configured to use a version of GAS that supports + * the .gnu_attribute directive, it will use that directive to + * record certain properties of the output code. + * This feature is new to GCC 4.3.0. + * .gnu_attribute is new to GAS 2.18. + */ +#if (__GNUC__ >= 4 && __GNUC_MINOR__ >= 3) +/* Tag_GNU_Power_ABI_FP/soft-float */ +#define GNU_FPOST_ATTR asm(".gnu_attribute 4, 2"); +#else +#define GNU_FPOST_ATTR +#endif /* __GNUC__ */ #endif /* __ASSEMBLY__ */ #define CONFIG_SYS_POST_RTC 0x00000001 diff --git a/include/sata.h b/include/sata.h index 57ee9ac86..37573cfee 100644 --- a/include/sata.h +++ b/include/sata.h @@ -7,5 +7,6 @@ ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer); ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer); int sata_initialize(void); +int __sata_initialize(void); #endif diff --git a/include/status_led.h b/include/status_led.h index 79be69885..175972a05 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -346,6 +346,9 @@ void status_led_set (int led, int state); #elif defined(CONFIG_NIOS2) /* XXX empty just to avoid the error */ /************************************************************************/ +#elif defined(CONFIG_BLACKFIN) +/* XXX empty just to avoid the error */ +/************************************************************************/ #elif defined(CONFIG_V38B) # define STATUS_LED_BIT 0x0010 /* Timer7 GPIO */ diff --git a/include/usb.h b/include/usb.h index 510df95d6..7c47098d8 100644 --- a/include/usb.h +++ b/include/usb.h @@ -138,7 +138,7 @@ enum { struct usb_device { int devnum; /* Device number on USB bus */ - int slow; /* Slow device? */ + int speed; /* full/low/high */ char mf[32]; /* manufacturer */ char prod[32]; /* product */ char serial[32]; /* serial number */ @@ -171,6 +171,7 @@ struct usb_device { unsigned long status; int act_len; /* transfered bytes */ int maxchild; /* Number of ports if hub */ + int portnr; struct usb_device *parent; struct usb_device *children[USB_MAXCHILDREN]; }; @@ -180,8 +181,9 @@ struct usb_device { */ #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ - defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_SL811HS) || \ - defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_R8A66597_HCD) + defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ + defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); @@ -263,13 +265,13 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); ((x_ & 0xFF000000UL) >> 24)); \ }) -#ifdef LITTLEENDIAN +#ifdef __LITTLE_ENDIAN # define swap_16(x) (x) # define swap_32(x) (x) #else # define swap_16(x) __swap_16(x) # define swap_32(x) __swap_32(x) -#endif /* LITTLEENDIAN */ +#endif /* * Calling this entity a "pipe" is glorifying it. A USB pipe @@ -279,7 +281,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - endpoint number (4 bits) * - current Data0/1 state (1 bit) * - direction (1 bit) - * - speed (1 bit) + * - speed (2 bits) * - max packet size (2 bits: 8, 16, 32 or 64) * - pipe type (2 bits: control, interrupt, bulk, isochronous) * @@ -296,7 +298,7 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); * - device: bits 8-14 * - endpoint: bits 15-18 * - Data0/1: bit 19 - * - speed: bit 26 (0 = Full, 1 = Low Speed) + * - speed: bit 26 (0 = Full, 1 = Low Speed, 2 = High) * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, * 10 = control, 11 = bulk) * @@ -308,8 +310,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); /* Create various pipes... */ #define create_pipe(dev,endpoint) \ (((dev)->devnum << 8) | (endpoint << 15) | \ - ((dev)->slow << 26) | (dev)->maxpacketsize) -#define default_pipe(dev) ((dev)->slow << 26) + ((dev)->speed << 26) | (dev)->maxpacketsize) +#define default_pipe(dev) ((dev)->speed << 26) #define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \ create_pipe(dev, endpoint)) @@ -359,7 +361,8 @@ int usb_set_interface(struct usb_device *dev, int interface, int alternate); #define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff) #define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf) #define usb_pipedata(pipe) (((pipe) >> 19) & 1) -#define usb_pipeslow(pipe) (((pipe) >> 26) & 1) +#define usb_pipespeed(pipe) (((pipe) >> 26) & 3) +#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW) #define usb_pipetype(pipe) (((pipe) >> 30) & 3) #define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS) #define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT) diff --git a/include/usb_defs.h b/include/usb_defs.h index 353019fc1..8032e5712 100644 --- a/include/usb_defs.h +++ b/include/usb_defs.h @@ -80,6 +80,12 @@ #define USB_DIR_OUT 0 #define USB_DIR_IN 0x80 +/* USB device speeds */ +#define USB_SPEED_FULL 0x0 /* 12Mbps */ +#define USB_SPEED_LOW 0x1 /* 1.5Mbps */ +#define USB_SPEED_HIGH 0x2 /* 480Mbps */ +#define USB_SPEED_RESERVED 0x3 + /* Descriptor types */ #define USB_DT_DEVICE 0x01 #define USB_DT_CONFIG 0x02 @@ -202,6 +208,7 @@ #define USB_PORT_FEAT_RESET 4 #define USB_PORT_FEAT_POWER 8 #define USB_PORT_FEAT_LOWSPEED 9 +#define USB_PORT_FEAT_HIGHSPEED 10 #define USB_PORT_FEAT_C_CONNECTION 16 #define USB_PORT_FEAT_C_ENABLE 17 #define USB_PORT_FEAT_C_SUSPEND 18 @@ -216,6 +223,9 @@ #define USB_PORT_STAT_RESET 0x0010 #define USB_PORT_STAT_POWER 0x0100 #define USB_PORT_STAT_LOW_SPEED 0x0200 +#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */ +#define USB_PORT_STAT_SPEED \ + (USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED) /* wPortChange bits */ #define USB_PORT_STAT_C_CONNECTION 0x0001 |