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2009-08-2885xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal
P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: P1020RDB Support AddedPoonam Aggrwal
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Added CONFIG_MAX_CPUS for P1020Poonam Aggrwal
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Add L2SRAM Register's macro definitionMingkai Hu
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Fix memory test range on MPC8536DSFelix Radensky
With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END memory test hangs if run without arguments. Set them to sane values, so that all available 512MB of RAM excluding exception vectors at the bottom and u-boot code and stack at the top can be tested. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Removed BEDBUG support on P1_P2_RDBKumar Gala
To match all other 85xx platforms we are removing BEDBUG support. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Init pci ethernet cards if we enable any on MPC8572DSKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28xes: Use proper IO access functionsPeter Tyser
Also fix some minor whitespace oddities while we're cleaning up Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Move to a common linker scriptKumar Gala
There are really no differences between all the 85xx linker scripts so we can just move to a single common one. Board code is still able to override the common one if need be. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Added P1020 Processor Support.Poonam Aggrwal
P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Add support for P2020RDB boardPoonam Aggrwal
The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal
The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-288xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28stx: create common vendor/board hierarchy for STx boardsAlex Dubov
Move files belonging to the STx boards into common vendor directory and update the Makefile to reflect this. Signed-off-by: Alex Dubov <oakad@yahoo.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Remove unused CONFIG_CLEAR_LAW0 definesPeter Tyser
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2886xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 However these are all captured in the config.h and thus redudant. Also moved common 86xx flags into cpu/mpc86xx/config.mk. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 However these are all captured in the config.h and thus redudant. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Add a 36-bit physical configuration for MPC8536DSKumar Gala
We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary to allow for larger memory sizes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-2885xx: Cleanup whitespace in mpc8536ds.cKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28pci/fsl_pci_init: Rework PCI ATMU setup to handle >4G of memoryKumar Gala
The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28pci/fsl_pci_init: Use PCIe capability to determine if controller is PCIeKumar Gala
Change the code to use the PCIe capabilities register to determine if we are a PCIe controller or not. Additionally cleaned up some white space and formatting in the file. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala
Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28Merge branch 'next' of git://git.denx.de/u-boot-nand-flash into nextWolfgang Denk
2009-08-26NAND: DaVinci: V2 Adding 4 BIT ECC supportSandeep Paulraj
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRSTSandeep Paulraj
This patch adds the new mode NAND_ECC_HW_OOB_FIRST in the nand code to support 4-bit ECC on TI DaVinci devices with large page (up to 2K) NAND chips. This ECC mode is similar to NAND_ECC_HW, with the exception of read_page API that first reads the OOB area, reads the data in chunks, feeds the ECC from OOB area to the ECC hw engine and perform any correction on the data as per the ECC status reported by the engine. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-new-ecc-mode-ecc_hw_oob_first.patch Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26mxc_nand: add nand driver for MX2/MX3Ilya Yanok
Driver for NFC NAND controller found on Freescale's MX2 and MX3 processors. Ported from Linux. Tested only with i.MX27 but should works with other MX2 and MX3 processors too. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26NAND: ADD page Parameter to all read_page/read_page_raw API'sSandeep Paulraj
This patch adds a new "page" parameter to all NAND read_page/read_page_raw APIs. The read_page API for the new mode ECC_HW_OOB_FIRST requires the page information to send the READOOB command and read the OOB area before the data area. This patch has been accepted by Andrew Morton and can be found at http://userweb.kernel.org/~akpm/mmotm/broken-out/mtd-nand-add-page-parameter-to-all-read_page-read_page_raw-apis.patch WE would like this to become part of the u-boot GIT as well Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Sneha Narnakaje <nsnehaprabha@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-2683xx, kmeter1: added NAND supportHeiko Schocher
Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26OneNAND: Remove unused read_spareramKyungmin Park
Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26KB9202: Add NAND supportMatthias Kaehlcke
Add KB9202 NAND driver Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-08-26OneNAND: Remove unused read_spareramKyungmin Park
Remove unused read_spareram and add unlock_all as kernel does Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2009-08-26galaxy5200: Cleanup typo and trailing whitespaceEric Millbrandt
Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-08-26Merge branch 'next' of git://www.denx.de/git/u-boot-coldfire into nextWolfgang Denk
2009-08-26ColdFire: Fix compile warning messagesTsiChung Liew
Change %08lX to %08X in board.c. Remove unused variable 'oscillator' in mcf5227x/cpu_init.c and 'scm2' in mcf532x/cpu_init.c. Provide argument type cast in drivers/dma/MCD_dmaApi.c. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-08-26ColdFire: Fix missing _IO_BASE which caused compile errorTsiChung Liew
The compile error was caused by a recent patch. Affected platforms - M5253DEMO.h, M5253EVBE.h, and M54455EVB.h. Adding the _IO_BASE automatically defined to 0 in asm-m68k/io.h if it isn't set in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-08-26Support up to 7 banks for ids as specified in JEDEC JEP106ZNiklaus Giger
see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
2009-08-25Merge branch 'next' of git://git.denx.de/u-boot-net into nextWolfgang Denk
2009-08-25Merge branch 'master' into nextWolfgang Denk
2009-08-25Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk
2009-08-25Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk
2009-08-25net: tsec - handle user interrupt while waiting for PHY auto negotiation to ↵Kim Phillips
complete if you don't have firmware installed for the PHY to come to life, this wait can be painful - let's give the option to avoid it if we want. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25Add Transfer Size Option to tftpRobin Getz
Optionally add RFC 2349 "Transfer Size Option", so we can minimize the time spent sending data over the UART (now print a single line during a tftp transfer). - If turned on (CONFIG_TFTP_TSIZE), U-Boot asks for the size of the file. - if receives the file size, a single line (50 chars) are printed. one hash mark == 2% of the file downloaded. - if it doesn't receive the file size (the server doesn't support RFC 2349, prints standard hash marks (one mark for each UDP frame). Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25Add debug message for Blackfin Ethernet Rx function.Robin Getz
Add a simple print for the Blackfin's Ethernet Rx function, so we can debug incomming Ethernet functions easier. Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25Convert CS8900 Ethernet driver to CONFIG_NET_MULTI APIBen Warren
All in-tree boards that use this controller have CONFIG_NET_MULTI added Also: - changed CONFIG_DRIVER_CS8900 to CONFIG_CS8900 - changed CS8900_BASE to CONFIG_CS8900_BASE - changed CS8900_BUS?? to CONFIG_CS8900_BUS?? - cleaned up line lengths - modified VCMA9 command function that accesses the device - removed MAC address initialization from lib_arm/board.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Tested-by: Wolfgang Denk <wd@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
2009-08-25arm nomadik: activate defrag choose 4k transfer block sizeAlessandro Rubini
This chooses 4kB data size for both TFTP and NFS, as an example about how to use support for IP fragments. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25nfs: accept CONFIG_NFS_READ_SIZE from config fileAlessandro Rubini
To take advantage of defragmented packets, the config file can define CONFIG_NFS_READ_SIZE to override the 1kB default. No support is there for an environment variable by now. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25tftp: get the tftp block size from config file and from the environmentAlessandro Rubini
Increasing the block size is useful if CONFIG_IP_DEFRAG is used. Howerver, the last fragments in a burst may overflow the receiving ethernet, so the default is left at 1468, with thre new CONFIG_TFTP_BLOCKSIZE for config files. Further, "tftpblocksize" can be set in the environment. Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25net: defragment IP packetsAlessandro Rubini
The defragmenting code is enabled by CONFIG_IP_DEFRAG; the code is useful for TFTP and NFS transfers. The user can specify the maximum defragmented payload as CONFIG_NET_MAXDEFRAG (default 16k). Since NFS has a bigger per-packet overhead than TFTP, the static reassembly buffer can hold CONFIG_NET_MAXDEFRAG + the NFS overhead. The packet buffer is used as an array of "hole" structures, acting as a double-linked list. Each new fragment can split a hole in two, reduce a hole or fill a hole. No support is there for a fragment overlapping two diffrent holes (i.e., thre new fragment is across an already-received fragment). Signed-off-by: Alessandro Rubini <rubini@gnudd.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-08-25ppc4xx: Fix ECC Correction bug with SMC ordering for NDFC driverFeng Kan
Fix ECC Correction bug where the byte offset location were double flipped causing correction routine to toggle the wrong byte location in the ECC segment. The ndfc_calculate_ecc routine change the order of getting the ECC code. /* The NDFC uses Smart Media (SMC) bytes order */ ecc_code[0] = p[2]; ecc_code[1] = p[1]; ecc_code[2] = p[3]; But in the Correction algorithm when calculating the byte offset location, the s1 is used as the upper part of the address. Which again reverse the order making the final byte offset address location incorrect. byteoffs = (s1 << 0) & 0x80; . . byteoffs |= (s0 >> 4) & 0x08; The order is change to read it in straight and let the correction function to revert it to SMC order. Signed-off-by: Feng Kan <fkan@amcc.com> Acked-by: Victor Gallardo <vgallardo@amcc.com> Acked-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
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