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path: root/cpu/mpc85xx/cpu.c
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2009-09-08ppc/85xx: Clean up do_resetKumar Gala
There is no reason to do a run time check for e500 v1 based cores to determine if we have the GUTs RSTCR facility. Only the first generation of PQ3 parts (MPC8540/41/55/60) do not have it. So checking to see if we are e500 v2 would miss future parts (like e500mc). Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal
While in probecpu() UART is still not initialized. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal
Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-288xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal
The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-288xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-018xxx: Break out DMA code to a common filePeter Tyser
DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12fsl/85xx, 86xx: Sync up DMA codePeter Tyser
The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser
Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-12qe: Pass in uec_info struct through uec_initializeHaiying Wang
The uec driver contains code to hard code configuration information for the uec ethernet controllers. This patch creates an array of uec_info structures, which are then parsed by the corresponding driver instance to determine configuration. It also creates function uec_standard_init() to initialize all UEC interfaces for 83xx and 85xx. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Add QE clk supportHaiying Wang
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-06-1285xx: Added MPC8535/E identifiersKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-03-30MPC85xx: Add MPC8569 CPU supportHaiying Wang
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-19Coding style cleanup, update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-02-1685xx: Add eSDHC support for 8536 DSAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2009-02-16mpc85xx: Add support for the P2020Srikanth Srinivasan
Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-02-1685xx: Format cpu freq printing to handle 8 coresKumar Gala
Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-01-23Add secondary CPUs processor frequency for e500 coreHaiying Wang
This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2008-12-19mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho
Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19mpc8568: Double local bus clock dividerTrent Piepho
The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
2008-12-19mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho
On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
2008-11-09Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren
Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren
Affected boards: Several MPC8xx boards Several MPC8260/MPC8272 boards Several MPC85xx boards Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-11-09Fix typo in cpu/mpc85xx/cpu.cBen Warren
CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-10-2485xx: Add basic e500mc core supportKumar Gala
Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-21Use strmhz() to format clock frequenciesWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-1885xx if NUM_CPUS>1, print cpu numberEd Swarthout
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
2008-10-18rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-07Fix the incorrect DDR clk freq reporting on 8536DSJason Jin
On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
2008-09-09Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.Sergei Poselenov
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-09-02Pass in tsec_info struct through tsec_initializeAndy Fleming
The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-08-27mpc85xx: Add support for the MPC8536Kumar Gala
The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-08-27mpc85xx: Add support for the MPC8572DS reference boardKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-07-14mpc85xx: use IS_E_PROCESSOR macroKim Phillips
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-07-09Merge branch 'master' of git://www.denx.de/git/u-boot-netWolfgang Denk
2008-07-06Add mechanisms for CPU and board-specific Ethernet initializationBen Warren
This patch is the first step in cleaning up net/eth.c, by moving Ethernet initialization to CPU or board-specific code. Initial implementation is only on the Freescale TSEC controller, but others will be added soon. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2008-06-28Coding Style CleanupWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-06-19Fix 4xx build issueAnatolij Gustschin
Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-11Added the upmconfig() function for 85xx.Sergei Poselenov
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-06-10MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger
The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
2008-06-1085xx: expose cpu identificationKumar Gala
The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-06-0985xx: Only use PORPLLSR[DDR_Ratio] on platforms that define itKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-05-20Fixed reset for socratesSergei Poselenov
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2008-04-2485xx: Round up frequency calculations to get reasonable outputKumar Gala
eg. because of rounding error we can get 799Mhz instead of 800Mhz. Introduced DIV_ROUND_UP and roundup taken from linux kernel. Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
2008-03-2685xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang
Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: get_tbclk() speed up and rounding fixJames Yang
Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26Update SVR numbers to expand supportAndy Fleming
FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
2007-12-11Handle Asynchronous DDR clock on 85xxKumar Gala
The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Stop using immap_t on 85xxKumar Gala
In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-12-11Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdtKumar Gala
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-10-19Setting MSR[DE] in do_reseturwithsughosh@gmail.com
Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
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