snowball/u-boot-ux500.git - u-boot for ux500

Age	Commit message (Expand)	Author
2009-11-12	fsl-ddr: Fix the chip-select interleaving issue	Dave Liu
2009-10-16	mpc8xxx: improve LAW error messages when setting up DDR	Paul Gortmaker
2009-09-24	ppc/p4080: Add various p4080 related defines (and p4040)	Kumar Gala
2009-09-15	ppc/8xxx: Misc DDR related fixes	Kumar Gala
2009-09-08	ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().	Poonam Aggrwal
2009-09-08	ppc/85xx/86xx: Device tree fixup for number of cores	Poonam Aggrwal
2009-09-08	ppc/85xx,86xx: Handling Unknown SOC version	Poonam Aggrwal
2009-09-08	ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host	Kumar Gala
2009-09-08	ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist	Kumar Gala
2009-08-28	85xx: Added single core members of FSL P1xx/P2xx processors series	Poonam Aggrwal
2009-08-28	85xx: Added P1020 Processor Support.	Poonam Aggrwal
2009-08-28	8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx	Poonam Aggrwal
2009-08-28	8xxx: Refactored common cpu specific code for 85xx/86xx into one file.	Poonam Aggrwal
2009-07-22	85xx, 86xx: Add common board_add_ram_info()	Peter Tyser
2009-07-01	fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more	Timur Tabi
2009-06-12	fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT	Kumar Gala
2009-03-30	fsl-ddr: add the DDR3 SPD infrastructure	Dave Liu
2009-03-30	fsl-ddr: Fix two bugs in the ddr infrastructure	Dave Liu
2009-02-16	fsl-ddr: Allow system to boot if we have more than 4G of memory	Kumar Gala
2009-02-16	fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller	Kumar Gala
2009-01-23	fsl-ddr: use the 1T timing as default configuration	Dave Liu
2009-01-23	fsl-ddr: make the self refresh idle threshold configurable	Dave Liu
2009-01-23	fsl-ddr: clean up the ddr code for DDR3 controller	Dave Liu
2009-01-23	fsl-ddr: update the bit mask for DDR3 controller	Dave Liu
2008-12-03	fsl ddr skip interleaving if not supported.	Ed Swarthout
2008-10-18	Add debug information for DDR controller registers	Haiying Wang
2008-10-18	Check DDR interleaving mode	Haiying Wang
2008-10-18	Pass dimm parameters to populate populate controller options	Haiying Wang
2008-10-18	Make DDR interleaving mode work correctly	Haiying Wang
2008-10-18	rename CFG_ macros to CONFIG_SYS	Jean-Christophe PLAGNIOL-VILLARD
2008-09-13	Coding style cleanup, update CHANGELOG	Wolfgang Denk
2008-09-07	Fix compiler warning in mpc8xxx ddr code	Kumar Gala
2008-08-27	FSL DDR: Add DDR2 DIMM paramter support	Kumar Gala
2008-08-27	FSL DDR: Add DDR1 DIMM paramter support	Kumar Gala
2008-08-27	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	Kumar Gala