Age | Commit message (Collapse) | Author |
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cpu/arm_cortex_a9/db8500/sec_bridge.c file)
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Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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db8500 v2.1 has a new ASIC ID. Add it to the function table.
Without this patch and with CONFIG_ITP_LOAD, U-Boot will hang on a
db8500 v2.1
Change-Id: I819663e698aa6667f5831575db87ded2c9f0c5c2
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/14476
Reviewed-by: QATOOLS
Reviewed-by: Jens WIKLANDER <jens.wiklander@stericsson.com>
Reviewed-by: Par-Olof HAKANSSON <par-olof.hakansson@stericsson.com>
Reviewed-by: Martin HOVANG <martin.xm.hovang@stericsson.com>
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With newer PRCMU FW (2.0.6), clearing of the Ack mailbox interrupt is
enforced.
This patch clears the Ack mailbox interrupt.
ST-Ericsson ID: ER 322248
Change-Id: I38c7af5a375230c22b61db6cc46283c01ff39727
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/14201
Reviewed-by: Par-Olof HAKANSSON <par-olof.hakansson@stericsson.com>
Reviewed-by: QATOOLS
Reviewed-by: Ulf MORLAND <ulf.morland@stericsson.com>
Reviewed-by: Mattias NILSSON <mattias.i.nilsson@stericsson.com>
Tested-by: Jonas SKARSTAM <jonas.skarstam@stericsson.com>
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Verification of the kernel and ITP signature before allowing to boot is
added. This feature is configurable and by default not activated. MeeGo-
built RPM will have this enabled.
ST-Ericsson ID: WP275634, ER275440
Change-Id: Ib888f39dd5dca1bc8b7d6e1b002da83a77908b07
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/11415
Tested-by: Robert ROSENGREN <robert.rosengren@stericsson.com>
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Reviewed-by: QATOOLS
Reviewed-by: Jens WIKLANDER <jens.wiklander@stericsson.com>
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General removal of executable permission of built source and header files,
i.e. changing permission from 755 to 644.
ST-Ericsson ID: None
ST-Ericsson FOSS-OUT ID: Trivial
Change-Id: Ic3cfc551d1ef1b1f0b5825f9916d1fc15b15b444
Signed-off-by: Robert Rosengren <robert.rosengren@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/10896
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
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Splitting security related code from itp.c into sec_bridge.c
ST-Ericsson ID: WP275634
ST-Ericsson FOSS-OUT ID: Trivial
Change-Id: I813daf0d0eaea4645e7d990bf467f19b0af968db
Signed-off-by: Robert Rosengren <robert.rosengren@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/10895
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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itp.c and cspsa_fp.c is SoC specific, not board specific.
Other db8500 based boards need it as well, therefore move it into
the SoC directory.
ST-Ericsson ID: WP275634
ST-Ericsson FOSS-OUT ID: Trivial
Change-Id: I386c0d84e9f44f18ded0d9059fc2dae4c27974f2
Signed-off-by: Robert Rosengren <robert.rosengren@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/10894
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Reviewed-by: Ulf HANSSON <ulf.hansson@stericsson.com>
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
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Clean up of PRCMU code in db8500 SoC code. Move things from cpu.c
and clock.h to prcmu.c. Also remove duplicate #defines and have
prcmu.c use the #defines in prcmu.h.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Ieffb0094b3f43f0c88f3ed457c6cb296fa0ce378
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9899
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
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Enable CONFIG_DISPLAY_CPUINFO and implement print_cpuinfo() in
cpu/arm_cortexa9/db8500.c.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Id4f67b223fabc4a8007229f8db12bd2a7362f8c2
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7115
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
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Moved clock code from board/st/u8500/u8500.c to
cpu/arm_cortexa9/db8500/clock.c.
Remove code to simulate Maja clocks.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Ibbb21d53091ceaddcc01e1a195e129039f986696
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7114
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
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Moved u8500_is_earlydrop() and cpu_is_u8500*() to
include/asm-arm/arch-db8500/cpu.h.
They are kept in cpu.h as the functions are very small and
should be inlined with each use of them.
The final binary actually also became around 100 bytes smaller.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Ied553b7c8a004a37c70c3e328a069ae8b2a92b23
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9893
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
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First patch to split cpu_arch SoC-code away from board code.
Added usage of arch_cpu_init() which is the corresponding
to board_init().
Moved db8500 code from board/st/u8500/u8500.c to
cpu/arm_cortexa9/db8500/cpu.c.
Also created include/asm/arch-db8500/cpu.h and
include/asm/arch-db8500/prcmu.h.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: I403d7d4f6c655c0d383afb3cb3be7e7df96683a3
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7150
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Tested-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Reviewed-by: QATOOLS
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
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Add -Wall -Wextra -Werror to CFLAGS for db8500 SoC code.
Also add -Wno-unused-parameter due to some inline functions in generic
include files are having unused parameters.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: Ibc59c6e4ad1188e96d7c65d600881869b7024ce8
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9891
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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Started work with splitting the files in board/st/u8500 into
proper SoC (system on a chip), drivers, commands and board code.
ST-Ericsson ID: None
Signed-off-by: Joakim Axelsson <joakim.axelsson@stericsson.com>
Change-Id: I33300b1990f377bc049785102f1c87fbe579e86d
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/7089
Reviewed-by: Robert ROSENGREN <robert.rosengren@stericsson.com>
Reviewed-by: Markus HELGESSON <markus.helgesson@stericsson.com>
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Michael BRANDT <michael.brandt@stericsson.com>
Reviewed-by: Mikael LARSSON1 <mikael.xt.larsson@stericsson.com>
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clock.c is SoC specific, not board specific.
Other db8500 based boards need it as well, therefore move it into
the SoC directory.
Change-Id: Ib23d44988628e8bb6a8cb89c56941cf2a815892d
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9399
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Reviewed-by: Markus HELGESSON <markus.helgesson@stericsson.com>
Reviewed-by: Robert ROSENGREN <robert.rosengren@stericsson.com>
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prcmu.c is SoC specific, not board specific.
Other db8500 based boards need it as well, therefore move it into
the SoC directory.
Change-Id: Ic40e474700fb737dbbb8ce7ea6c88ea1b89d2f20
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/9371
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Reviewed-by: Markus HELGESSON <markus.helgesson@stericsson.com>
Reviewed-by: Robert ROSENGREN <robert.rosengren@stericsson.com>
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Fixed Android's arm-eabi-gcc GCC 4.4 warning (see below) my removing the
cpu switch.
warning: switch -mcpu=cortex-a9 conflicts with -march= switch
Note:
This warning does not appear with the CodeSourcery GCC 4.4 (2009q3) and
seems wrong since cortex-a9 is an implementation of ARMv7.
Change-Id: I0b26dee03a6ea892f4d62ac0407c0893e372a90b
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Change-Id: I08f0d3813074b6210a9c18d322ce5e147562c239
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/3358
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Reviewed-by: Martin LUNDHOLM <martin.xa.lundholm@stericsson.com>
Tested-by: Martin LUNDHOLM <martin.xa.lundholm@stericsson.com>
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Change-Id: I30b857fc0cf38f7e81647f1d0f9866d7d6a34612
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2500
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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This patch includes a few timer related changes.
- Use MTU timer 2 instead of 0.
- Fixed TIMER_CLOCK (133 MHz instead of 110 MHz).
- Change MTU prescaler to 16.
Change-Id: I589e531bbf2c7f0b317f05604f7550141babc11c
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2499
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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This patch does the following:
* Startup graphics only support for HREF+.
* Displays a logo last in the u-boot sequence before the kernel is booted.
* Informs the kernel not to display penguins.
* Added pmem values to bootargs.
ST Ericsson Change-ID: WP236570
Change-Id: Ib176c17a795ddd002e94344eb9c67739b1e2269e
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/1048
Reviewed-by: Par-Olof HAKANSSON <par-olof.hakansson@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
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This patch is part of WP254081 which depends on WP252006.
* Fixed I2C, use real timeouts instead of counter
* Undefined CONFIG_BOOTTIME, since it as to be changed to new timer.c
* Merged V1 patches from Bangalore
The patches were merged manually, because of the differences
of the U-Boot baseline (Bangalore U-Boot 1.3.1, Lund 2009.11).
The original patches were created by Rabin Vincent
<rabin.vincent@stericsson.com>.
and were applied originally to
Branches: blr_lsp, remotes/origin/blr_lsp
Follows: qpppaaa_20100210_094651
0001-u8500-gpio-add-I2C0-altfun.patch
0002-u8500-use-correct-v1-macros.patch
0003-emmc-clean-up-paritioning.patch
0004-u8500-remove-incorrect-ram-settings.patch
0005-u8500-gpio-remove-unnecessary-ifdefs.patch
0006-u8500-add-ED-v1-detection-and-handle-eMMC-diff.patch
0008-u8500-mmc-don-t-disable-altfuns.patch
0009-u8500-gpio-remove-unused-defined.patch
0010-u8500-mmc-add-barrier-for-while-loop.patch
0011-u8500-mmc-handle-non-block-addressed-cards.patch
0012-u8500-mmc-remove-unused-gpio-settings-on-v1.patch
0013-u8500-emmc-build-fix.patch
0014-u8500-handle-v1-gpios-and-clocks.patch
0015-mmc-build-fix-for-block-addressing.patch
0016-u8500-add-clocks-and-hardware-files.patch
0017-u8500-enable-PRCUM-timers-reg-for-ED.patch
0018-u8500-handle-MTU-for-v1-ED.patch
0019-u8500-emmc-remove-unnecessary-GPIO-settings.patch
0020-u8500-remove-dead-code.patch
0021-u8500-add-working-MTU-timer.patch
0022-pl011-empty-rx-fifo-if-necessary.patch
0023-u8500-gpio-fix-cont-handling-in-altfunc.patch
0024-u8500-reduce-bootdelay-to-1-and-enable-zero-check.patch
0025-u8500-disable-forcing-of-verify-but-set-n-by-default.patch
0029-u8500-fix-some-gpio-settings.patch
0030-emmc-make-v1-paritioning-differences-explicit.patch
Signed-off-by: Michael Brandt <Michael.Brandt@stericsson.com>
Change-Id: I1106702e393c34f630e71f071e06c3952b0d3a1a
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/182
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
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measurement. Note: idle time measurement does not seem to work reliable at the moment. Verification needed.
Signed-off-by: Michael Brandt <Michael.Brandt@stericsson.com>
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Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:
Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.
The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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applied PACK3 changes:
* cpu/arm_cortexa9/start.S: reset register changed, but U-Boot reset
command still does not work.
* config.mk: build address changed to 0x05FC0000
* board/st/u8500/mmc.c: MBR change: descrease 4th partition size (userfs
2) from 0x00c0'0000 to 0x00b9'a000 sectors (6,442,450,944 to
6,228,541,440 bytes).
* board\st\u8500\init_mmc.c: modify bootargs to set board_id to HREF or
MOP. Is is an extremly ugly solution. It modifies the bootargs env
variable directly (bootargs[9] = board_id;), instead of setting a
additional environment variable board_id and use it in the bootargs
envvar.
* board/st/u8500/mmc.c: undocumented clock changes.
* board/st/u8500/mmc_utils.c:
new routine to switch to 4-bit interface.
The switch is done in mmc_read_file(). It would make more sense
to do so in mmc_init.
* board/st/u8500/u8500.c:
clock changes for HSI and I2C. I2C is now clocked by SOC1 PLL and runs
with 24 MHz (depends on boot ROM SOC1 initialisation)
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In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We need to add the readback to bootpage translation LAW
to make it effect.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Now that we track which TLB CAM entries are used we can allocate
entries on the fly. Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code. For example the SPD
DDR code today hard codes which TLB entries it uses. We can now make
that pick entries that are free.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Conflicts:
.gitignore
include/configs/u8500.h
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Conflicts:
include/usb/musb_udc.h
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The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for
usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor
These are out right duplicates in usb.h
usb_device_descriptor
usb_string_descriptor
This one has extra unused elements
usb_endpoint_descriptor
unsigned char bRefresh
unsigned char bSynchAddress;
These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.
usb_config_descriptor
usb_interface_descriptor
The change is to consolidate the definition of the descriptors
to usbdescriptors.h. The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.
So
usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface
For these, the common descriptor elements are accessed now
by an element 'desc'.
As an example
- if (iface->bInterfaceClass != USB_CLASS_HUB)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HUB)
This has been compile tested on MAKEALL arm, ppc and mips.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.
This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.
E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.168 RS: 232
0.172 I2C: ready
0.176 DRAM: 64 MB
1.236 FLASH: 32 MB
Versus:
0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.092 RS: 232
0.092 I2C: ready
0.096 DRAM: 64 MB
0.644 FLASH: 32 MB
So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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u-boot updates, before starting Linux, the memory node in the
DTS. As this is a "standard" feature, move this functionality
to the cpu.c file for mpc5xxx and mpc512x processors.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Conflicts:
lib_generic/zlib.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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