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Fixed Android's arm-eabi-gcc GCC 4.4 warning (see below) my removing the
cpu switch.
warning: switch -mcpu=cortex-a9 conflicts with -march= switch
Note:
This warning does not appear with the CodeSourcery GCC 4.4 (2009q3) and
seems wrong since cortex-a9 is an implementation of ARMv7.
Change-Id: I0b26dee03a6ea892f4d62ac0407c0893e372a90b
Signed-off-by: Michael Brandt <michael.brandt@stericsson.com>
Change-Id: I08f0d3813074b6210a9c18d322ce5e147562c239
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/3358
Reviewed-by: Joakim AXELSSON <joakim.axelsson@stericsson.com>
Reviewed-by: Martin LUNDHOLM <martin.xa.lundholm@stericsson.com>
Tested-by: Martin LUNDHOLM <martin.xa.lundholm@stericsson.com>
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Change-Id: I30b857fc0cf38f7e81647f1d0f9866d7d6a34612
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2500
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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This patch includes a few timer related changes.
- Use MTU timer 2 instead of 0.
- Fixed TIMER_CLOCK (133 MHz instead of 110 MHz).
- Change MTU prescaler to 16.
Change-Id: I589e531bbf2c7f0b317f05604f7550141babc11c
Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com>
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/2499
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
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This patch does the following:
* Startup graphics only support for HREF+.
* Displays a logo last in the u-boot sequence before the kernel is booted.
* Informs the kernel not to display penguins.
* Added pmem values to bootargs.
ST Ericsson Change-ID: WP236570
Change-Id: Ib176c17a795ddd002e94344eb9c67739b1e2269e
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/1048
Reviewed-by: Par-Olof HAKANSSON <par-olof.hakansson@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
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This patch is part of WP254081 which depends on WP252006.
* Fixed I2C, use real timeouts instead of counter
* Undefined CONFIG_BOOTTIME, since it as to be changed to new timer.c
* Merged V1 patches from Bangalore
The patches were merged manually, because of the differences
of the U-Boot baseline (Bangalore U-Boot 1.3.1, Lund 2009.11).
The original patches were created by Rabin Vincent
<rabin.vincent@stericsson.com>.
and were applied originally to
Branches: blr_lsp, remotes/origin/blr_lsp
Follows: qpppaaa_20100210_094651
0001-u8500-gpio-add-I2C0-altfun.patch
0002-u8500-use-correct-v1-macros.patch
0003-emmc-clean-up-paritioning.patch
0004-u8500-remove-incorrect-ram-settings.patch
0005-u8500-gpio-remove-unnecessary-ifdefs.patch
0006-u8500-add-ED-v1-detection-and-handle-eMMC-diff.patch
0008-u8500-mmc-don-t-disable-altfuns.patch
0009-u8500-gpio-remove-unused-defined.patch
0010-u8500-mmc-add-barrier-for-while-loop.patch
0011-u8500-mmc-handle-non-block-addressed-cards.patch
0012-u8500-mmc-remove-unused-gpio-settings-on-v1.patch
0013-u8500-emmc-build-fix.patch
0014-u8500-handle-v1-gpios-and-clocks.patch
0015-mmc-build-fix-for-block-addressing.patch
0016-u8500-add-clocks-and-hardware-files.patch
0017-u8500-enable-PRCUM-timers-reg-for-ED.patch
0018-u8500-handle-MTU-for-v1-ED.patch
0019-u8500-emmc-remove-unnecessary-GPIO-settings.patch
0020-u8500-remove-dead-code.patch
0021-u8500-add-working-MTU-timer.patch
0022-pl011-empty-rx-fifo-if-necessary.patch
0023-u8500-gpio-fix-cont-handling-in-altfunc.patch
0024-u8500-reduce-bootdelay-to-1-and-enable-zero-check.patch
0025-u8500-disable-forcing-of-verify-but-set-n-by-default.patch
0029-u8500-fix-some-gpio-settings.patch
0030-emmc-make-v1-paritioning-differences-explicit.patch
Signed-off-by: Michael Brandt <Michael.Brandt@stericsson.com>
Change-Id: I1106702e393c34f630e71f071e06c3952b0d3a1a
Reviewed-on: http://gerrit.lud.stericsson.com/gerrit/182
Reviewed-by: Michael BRANDT <michael.brandt@stericsson.com>
Tested-by: Jonas ABERG <jonas.aberg@stericsson.com>
Reviewed-by: Jonas ABERG <jonas.aberg@stericsson.com>
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measurement. Note: idle time measurement does not seem to work reliable at the moment. Verification needed.
Signed-off-by: Michael Brandt <Michael.Brandt@stericsson.com>
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Add support to configure bus parking mode and master in bus arbitration
configuration (ACR). Add this for the kmeter1 port:
Configure bus arbiter with recommended values from Freescale
to improve bus latency/throughput for application with
intensive QuiccEngine activity.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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The memory controller could already be enabled, when spd_sdram() is
called. This could be the case for example, when the SDRAM is initialized
by the JTAG debugger.
The "sync" after the register access via the accessor function is
still needed, because the macro uses the sync before the real write
is done. So until not all accesses are converted to using accessor
functions, this sync still needs to be made "manually" here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd.eu>
Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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applied PACK3 changes:
* cpu/arm_cortexa9/start.S: reset register changed, but U-Boot reset
command still does not work.
* config.mk: build address changed to 0x05FC0000
* board/st/u8500/mmc.c: MBR change: descrease 4th partition size (userfs
2) from 0x00c0'0000 to 0x00b9'a000 sectors (6,442,450,944 to
6,228,541,440 bytes).
* board\st\u8500\init_mmc.c: modify bootargs to set board_id to HREF or
MOP. Is is an extremly ugly solution. It modifies the bootargs env
variable directly (bootargs[9] = board_id;), instead of setting a
additional environment variable board_id and use it in the bootargs
envvar.
* board/st/u8500/mmc.c: undocumented clock changes.
* board/st/u8500/mmc_utils.c:
new routine to switch to 4-bit interface.
The switch is done in mmc_read_file(). It would make more sense
to do so in mmc_init.
* board/st/u8500/u8500.c:
clock changes for HSI and I2C. I2C is now clocked by SOC1 PLL and runs
with 24 MHz (depends on boot ROM SOC1 initialisation)
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In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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add the override for write leveling sampling and
start time according to specific board.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but
It should be set to tXP parameter, tXP=max(3CK, 7.5ns)
2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but
It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter
We are setting the mode register MR0[A12]='1'
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL
backwards so we report the wrong frequency.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We already map the page cache-inhibited. There is no reason we
shouldn't also be marking it guarded to prevent speculative accesses.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We need to add the readback to bootpage translation LAW
to make it effect.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Now that we track which TLB CAM entries are used we can allocate
entries on the fly. Change the SPD DDR TLB setup code to assume
we use at most 8 TLBs (or the number free, which ever is fewer).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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We need to track which TLB CAM entries are used to allow us to
"dynamically" allocate entries later in the code. For example the SPD
DDR code today hard codes which TLB entries it uses. We can now make
that pick entries that are free.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The FSL_CORENET platforms use a completely different means to determine
which PCIe port is enabled as well as if its a host or agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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The e500mc core supports the ability to stash into the L1 or L2 cache,
however we need to uniquely identify the caches with an id.
We use the following equation to set the various stash-ids:
32 + coreID*2 + 0(L1) or 1(L2)
The 0 (for L1) or 1 (for L2) matches the CT field used be various cache
control instructions.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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Conflicts:
.gitignore
include/configs/u8500.h
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Conflicts:
include/usb/musb_udc.h
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The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for
usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor
These are out right duplicates in usb.h
usb_device_descriptor
usb_string_descriptor
This one has extra unused elements
usb_endpoint_descriptor
unsigned char bRefresh
unsigned char bSynchAddress;
These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.
usb_config_descriptor
usb_interface_descriptor
The change is to consolidate the definition of the descriptors
to usbdescriptors.h. The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.
So
usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface
For these, the common descriptor elements are accessed now
by an element 'desc'.
As an example
- if (iface->bInterfaceClass != USB_CLASS_HUB)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HUB)
This has been compile tested on MAKEALL arm, ppc and mips.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
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Commit c7190f02 (retain POR values of non-configured ACR, SPCR, SCCR,
and LCRR bitfields) moved the LCRR assignment to after relocation
to RAM because of the potential problem with changing the local bus
clock while executing from flash.
This change unfortunately adversely affects the boot time, as running
all code up to cpu_init_r can cause significant slowdown.
E.G. on a 8347 board a bootup time increase of ~600ms has been observed:
0.020 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.168 RS: 232
0.172 I2C: ready
0.176 DRAM: 64 MB
1.236 FLASH: 32 MB
Versus:
0.016 CPU: e300c1, MPC8347_PBGA_EA, Rev: 3.0 at 400 MHz, CSB: 266.667 MHz
0.092 RS: 232
0.092 I2C: ready
0.096 DRAM: 64 MB
0.644 FLASH: 32 MB
So far no boards have needed the late LCRR setup, so simply revert it
for now - If it is needed at a later time, those boards can either do
their own final LCRR setup in board code (E.G. in board_early_init_r),
or we can introduce a CONFIG_SYS_LCRR_LATE config option to only do
the setup in cpu_init_r.
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
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u-boot updates, before starting Linux, the memory node in the
DTS. As this is a "standard" feature, move this functionality
to the cpu.c file for mpc5xxx and mpc512x processors.
Signed-off-by: Heiko Schocher <hs@denx.de>
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Conflicts:
lib_generic/zlib.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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"nandecc" help output should not reproduce the command name, nor have
a trailing newline.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
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Signed-off-by: Wolfgang Denk <wd@denx.de>
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Conflicts:
board/esd/plu405/plu405.c
drivers/rtc/ftrtc010.c
Signed-off-by: Wolfgang Denk <wd@denx.de>
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According to the PPC reference implementation the udelay() function is
responsible for resetting the watchdog timer as frequently as needed.
Most other architectures do not meet that requirement, so long-running
operations might result in a watchdog reset.
This patch adds a generic udelay() function which takes care of
resetting the watchdog before calling an architecture-specific
__udelay().
Signed-off-by: Ingo van Lil <inguin@gmx.de>
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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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In preperation for full relocation
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
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by the linux kernel and we still want to be able to use that timer for boottime measurement. IE leave the 3rd timer run until we're executing init. Added atags for u-boot timing measurements as communication with the kernel.
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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj <at> jcrosoft.com>
Cc: Haavard Skinnemoen <haavard.skinnemoen <at> atmel.com>
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This patch adds support for A320 evaluation board from Faraday. This board
uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM.
FA526 is an ARMv4 processor and uses the ARM920T source in this patch.
Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
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Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
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Remove SDP referenced unused defines
Signed-off-by: Nishanth Menon <nm@ti.com>
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Provides initial support for TI OMAP-L1x/DA8xx SoC devices.
See http://www.ti.com
Provides:
Low level initialisation.
System clock API.
Timer control.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
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Remove volatiles and memory mapped structure accesses and replace with
readl and writel macro usage.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
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This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Fix stack_setup to place the stack on the correct address in DRAM
accroding to U-Boot standard and remove conditional compilation by
CONFIG_MEMORY_UPPER_CODE macro that is not necessry. This macro
was introduced and used only by this board for some unclear reason.
The definition of this macro is also removed because it's not
referenced elsewhere.
Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Tested-by: Minkyu Kang <mk7.kang@samsung.com>
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