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2008-06-12Change initdram() return type to phys_size_tBecky Bruce
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
2008-06-04ppc4xx: Fix problem with SDRAM init in bamboo NAND booting portStefan Roese
This patch fixes a problem spotted by Eugene O'Brian (thanks Eugene) introduced by the commit: ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S With this patch SDRAM will get initialized again and booting from NAND is working again. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
2008-06-03Remove shell variable UNDEF_SYM.Kenneth Johansson
UNDEF_SYM is a shell variable in the main Makefile used to force the linker to add all u-boot commands to the final image. It has no use here. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
2008-06-03ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese
This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
2008-05-14ppc4xx: Individual handling of ddr2_fixed.c for canyonlands_nand buildStefan Roese
Canyonlands has a file ddr2_fixed.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-30ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM moduleStefan Roese
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-04-18ppc4xx: Adjust Canyonlands fixed DDR2 setup (NAND booting) to 512MB SODIMMStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15ppc4xx: Add Canyonlands NAND booting supportStefan Roese
460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-12Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk
With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-01-09fix comments with new drivers organizationMarcel Ziswiler
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2008-01-04ppc4xx: Fix Sequoia NAND booting targetStefan Roese
The Sequoia NAND booting target now uses the recently extracted cpu/ppc4xx/denali_data_eye.c file too. Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-28ppc4xx: Fix compilation problem of kilauea/haleakala nand booting targetStefan Roese
Use correct link to nand_ecc now located in drivers/mtd/nand/ for the platforms mentioned above. Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-11Merge commit 'u-boot/master' into for-1.3.1Stefan Roese
Conflicts: drivers/rtc/Makefile
2007-11-25drivers/mtd : move mtd drivers to drivers/mtdJean-Christophe PLAGNIOL-VILLARD
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2007-11-03ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese
This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Fix acadia_nand build problemStefan Roese
Since the cache handling functions were moved from start.S into cache.S the acadia NAND booting Makfile needs to be adapted accordingly. Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAMEugene O'Brien
This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
2007-09-11[ppc4xx] Individual handling of sdram.c for bamboo_nand buildGrzegorz Bernacki
Bamboo has a file sdram.c which needs special treatment when building in separate directory. It has to be linked to build directory otherwise it is not seen. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
2007-06-19[ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese
The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese
2007-06-01ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-01ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese
This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-05ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese
Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06[PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese
As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05[PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
2006-10-23Fix sequoia separate object direcory building problems.Marian Balakowicz
2006-09-12Update NAND boot documentationStefan Roese
Patch by Stefan Roese, 12 Sep 2006
2006-09-07Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006