From 66f5fa9263629271edc86178b1f224e3c9aab2b3 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Wed, 7 May 2008 16:54:31 -0500 Subject: 85xx: Limit CPU2 workaround to parts that have the errata Signed-off-by: Ebony Zhu Signed-off-by: Andy Fleming --- board/freescale/mpc8548cds/mpc8548cds.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index dc39fbe8d..efe2a3a3d 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -59,6 +59,7 @@ int checkboard (void) uint pci_slot = get_pci_slot (); uint cpu_board_rev = get_cpu_board_revision (); + uint svr; printf ("Board: CDS Version 0x%02x, PCI Slot %d\n", get_board_version (), pci_slot); @@ -71,12 +72,16 @@ int checkboard (void) */ local_bus_init (); + svr = get_svr(); + /* * Fix CPU2 errata: A core hang possible while executing a * msync instruction and a snoopable transaction from an I/O * master tagged to make quick forward progress is present. + * Fixed in Silicon Rev.2.1 */ - ecm->eebpcr |= (1 << 16); + if (!(SVR_MAJ(svr) >= 2 && SVR_MIN(svr) >= 1)) + ecm->eebpcr |= (1 << 16); /* * Hack TSEC 3 and 4 IO voltages. -- cgit v1.2.3