From b38dbd4622a2abeedf9fcb1806958d9afac0bbd4 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 13 Mar 2006 00:46:05 +0100 Subject: Fix bug in [id]cache_status commands for MPC85xx processors; should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005 --- CHANGELOG | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'CHANGELOG') diff --git a/CHANGELOG b/CHANGELOG index 51efb237f..ac984168d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix bug in [id]cache_status commands for MPC85xx processors; + should look at LSB of L1CSRn registers to determine if L1 cache is + enabled, not the MSB. + Patch by Murray Jensen, 19 Jul 2005 + * Fix array overflow with fw_setenv on uninitialised environment Patch by Murray Jensen, 15 Jul 2005 -- cgit v1.2.3