From f3ed3c9b7441cde936d06a1ff7b1490ff0d600e6 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Jul 2009 10:53:43 +0200 Subject: ppc4xx: Fix Arches DDR2 initialization Testing on AMCC Arches with the latest U-Boot version yielded that DDR2 initialization is currently broken. U-Boot hangs upon relocation to SDRAM or crashes with random traps. This patch fixes this problem. Arches now uses a different WRDTR and CLKTR default setting than Canyonlands/Glacier. Signed-off-by: Stefan Roese --- board/amcc/canyonlands/canyonlands.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index cfc1023f4..c0c135201 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -40,6 +40,24 @@ DECLARE_GLOBAL_DATA_PTR; #define BOARD_GLACIER 3 #define BOARD_ARCHES 4 +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +#if defined(CONFIG_ARCHES) +u32 ddr_wrdtr(u32 default_val) { + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_0_DEG | 0x823); +} +#else +u32 ddr_wrdtr(u32 default_val) { + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); +} + +u32 ddr_clktr(u32 default_val) { + return (SDRAM_CLKTR_CLKP_90_DEG_ADV); +} +#endif + #if defined(CONFIG_ARCHES) /* * FPGA read/write helper macros @@ -286,18 +304,6 @@ int checkboard(void) } #endif /* !defined(CONFIG_ARCHES) */ -/* - * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with - * board specific values. - */ -u32 ddr_wrdtr(u32 default_val) { - return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); -} - -u32 ddr_clktr(u32 default_val) { - return (SDRAM_CLKTR_CLKP_90_DEG_ADV); -} - #if defined(CONFIG_NAND_U_BOOT) /* * NAND booting U-Boot version uses a fixed initialization, since the whole -- cgit v1.2.3 From 11a1604f8d0a8d936b42f6435d004b4aa33a5d87 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Jul 2009 07:42:48 +0200 Subject: ppc4xx: Add some NAND-booting bootstrap entries to Kilauea chip_config cmd This patch adds some I2C bootstrap setting for NAND booting to the Kilauea chip_config command ("533-nand" and "600-nand"). Additionally some incorrectly indented lines are fixed. Signed-off-by: Stefan Roese --- board/amcc/kilauea/chip_config.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/kilauea/chip_config.c b/board/amcc/kilauea/chip_config.c index 9a3fc1512..919ec7f0f 100644 --- a/board/amcc/kilauea/chip_config.c +++ b/board/amcc/kilauea/chip_config.c @@ -25,6 +25,8 @@ #include #include +/* NAND booting versions differ in bytes: 6, 8, 9, 11, 12 */ + struct ppc4xx_config ppc4xx_config_val[] = { { "333-nor","NOR CPU: 333 PLB: 166 OPB: 83 EBC: 83", @@ -49,10 +51,17 @@ struct ppc4xx_config ppc4xx_config_val[] = { }, { "533-nor", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", - { - 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, - 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 - } + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00, + 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 + } + }, + { + "533-nand", "NOR CPU: 533 PLB: 177 OPB: 88 EBC: 88", + { + 0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } }, { "600-nor", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", @@ -61,6 +70,13 @@ struct ppc4xx_config ppc4xx_config_val[] = { 0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00 } }, + { + "600-nand", "NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100", + { + 0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0f, 0x00, + 0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 + } + }, { "666-nor", "NOR CPU: 666 PLB: 222 OPB: 111 EBC: 111", { -- cgit v1.2.3 From 042d01c72e0ea95731708dd24bb8b6cf42e75c80 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 27 Jul 2009 09:13:38 +0200 Subject: ppc4xx: Fix problem with NOR range assignment in Canyonlands ft_board_setup This patch fixes the problem, that the current fdt board fixup code only set's one range, the one for NOR. By this it's overwriting the already correctly configured values done in __ft_board_setup(). Just remove this now unneeded NOR fixup and all the ranges are correctly defined. Signed-off-by: Stefan Roese Cc: Dirk Eibach Cc: Felix Radensky --- board/amcc/canyonlands/canyonlands.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'board/amcc') diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index c0c135201..5071c8d4e 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -585,23 +585,8 @@ extern void __ft_board_setup(void *blob, bd_t *bd); void ft_board_setup(void *blob, bd_t *bd) { - u32 val[4]; - int rc; - __ft_board_setup(blob, bd); - /* Fixup NOR mapping */ - val[0] = CONFIG_SYS_NOR_CS; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L; /* we fixed up this address */ - val[3] = gd->bd->bi_flashsize; - rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", - val, sizeof(val), 1); - if (rc) { - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); - } - if (gd->board_type == BOARD_CANYONLANDS_SATA) { /* * When SATA is selected we need to disable the first PCIe -- cgit v1.2.3