From c553b5f4a0c77fc76e1d25e71c8aaa47657e2d6f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 15 Feb 2009 22:26:54 +0100 Subject: ppc4xx: Cleanup PMC405 board support This patch fixes coding style for PMC405 board support. Also some unneeded features/code is removed. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc405/pmc405.c | 95 +++++++++++++---------------------------------- 1 file changed, 25 insertions(+), 70 deletions(-) (limited to 'board') diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 975b6d6d9..dd58d0124 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -40,7 +40,6 @@ const unsigned char fpgadata[] = }; int filesize = sizeof(fpgadata); - int board_early_init_f (void) { /* @@ -55,23 +54,23 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0, INT0 highest priority */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ /* - * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us + * EBC Configuration Register: + * set ready timeout to 512 ebc-clks -> ca. 15 us */ mtebc (epcr, 0xa8400000); /* * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \ CONFIG_SYS_FPGA_DONE | \ CONFIG_SYS_XEREADY | \ @@ -85,26 +84,26 @@ int board_early_init_f (void) } out32(GPIO0_OR, 0); - out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */ + /* setup for output */ + out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \ + CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); - /* - check if rev1_2 is low, then: - * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST# + /* + * - check if rev1_2 is low, then: + * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST + * in TCR to assert INTA# or SELFRST# */ - return 0; } - -/* ------------------------------------------------------------------------- */ - - int misc_init_r (void) { /* adjust flash start and offset */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */ + /* deassert EREADY# */ + out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); return (0); } @@ -113,16 +112,16 @@ ushort pmc405_pci_subsys_deviceid(void) ulong val; val = in32(GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ - if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ + /* check monarch# signal */ + if (val & CONFIG_SYS_NONMONARCH) return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; - } return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH; } return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH; } /* - * Check Board Identity: + * Check Board Identity */ int checkboard (void) { @@ -133,29 +132,25 @@ int checkboard (void) puts ("Board: "); - if (i == -1) { + if (i == -1) puts ("### No HW ID - assuming PMC405"); - } else { + else puts(str); - } val = in32(GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ puts(" rev1.2 ("); - if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */ + if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */ puts("non-"); - } puts("monarch)"); - } else { + } else puts(" <=rev1.1"); - } putc ('\n'); return 0; } -/* ------------------------------------------------------------------------- */ void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP @@ -166,43 +161,3 @@ void reset_phy(void) lxt971_no_sleep(); #endif } - - -int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - ulong addr; - volatile uchar *ptr; - volatile uchar val; - int i; - - addr = simple_strtol (argv[1], NULL, 16) + 0x16; - - i = 0; - for (;;) { - ptr = (uchar *)addr; - for (i=0; i<8; i++) { - *ptr = i; - val = *ptr; - - if (val != i) { - printf("ERROR: addr=%p write=0x%02X, read=0x%02X\n", ptr, i, val); - return 0; - } - - /* Abort if ctrl-c was pressed */ - if (ctrlc()) { - puts("\nAbort\n"); - return 0; - } - - ptr++; - } - } - - return 0; -} -U_BOOT_CMD( - cantest, 3, 1, do_cantest, - "Test CAN controller", - NULL - ); -- cgit v1.2.3 From 2f6eb9170bf91b72ea51dcea2a8b9c11b0e20bc5 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 15 Feb 2009 22:27:47 +0100 Subject: ppc4xx: Update PMC405 board support This patch prepares the good old PMC405 board support for upcoming PMC405V2 patches. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- board/esd/pmc405/config.mk | 6 +---- board/esd/pmc405/pmc405.c | 18 +++++++------- include/configs/PMC405.h | 58 +++++++++++++++++++++++----------------------- 3 files changed, 40 insertions(+), 42 deletions(-) (limited to 'board') diff --git a/board/esd/pmc405/config.mk b/board/esd/pmc405/config.mk index fc2794dbb..5a3fc4be7 100644 --- a/board/esd/pmc405/config.mk +++ b/board/esd/pmc405/config.mk @@ -21,8 +21,4 @@ # MA 02111-1307 USA # -# -# esd PMC405 boards -# - -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFF80000 diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index dd58d0124..10e7ce420 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -2,7 +2,7 @@ * (C) Copyright 2001-2003 * Stefan Roese, DENX Software Engineering, sr@denx.de. * - * (C) Copyright 2005 + * (C) Copyright 2005-2009 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * * See file CREDITS for list of people who contributed to this @@ -26,6 +26,7 @@ #include #include +#include #include #include @@ -77,16 +78,16 @@ int board_early_init_f (void) CONFIG_SYS_NONMONARCH | \ CONFIG_SYS_REV1_2) << 5)); - if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) { + if (!(in_be32((void*)GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \ CONFIG_SYS_SELF_RST) << 5)); } - out32(GPIO0_OR, 0); + out_be32((void*)GPIO0_OR, CONFIG_SYS_VPEN); /* setup for output */ - out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \ - CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); + out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \ + CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN); /* * - check if rev1_2 is low, then: @@ -103,14 +104,15 @@ int misc_init_r (void) gd->bd->bi_flashoffset = 0; /* deassert EREADY# */ - out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); + out_be32((void*)GPIO0_OR, + in_be32((void*)GPIO0_OR) | CONFIG_SYS_XEREADY); return (0); } ushort pmc405_pci_subsys_deviceid(void) { ulong val; - val = in32(GPIO0_IR); + val = in_be32((void*)GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ /* check monarch# signal */ if (val & CONFIG_SYS_NONMONARCH) @@ -137,7 +139,7 @@ int checkboard (void) else puts(str); - val = in32(GPIO0_IR); + val = in_be32((void*)GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ puts(" rev1.2 ("); if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 7fbdeb08e..c598d00cf 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -40,11 +40,20 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ +/* Only interrupt boot if space is pressed. */ +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot in %d seconds\n", bootdelay +#undef CONFIG_AUTOBOOT_DELAY_STR +#define CONFIG_AUTOBOOT_STOP_STR " " + #undef CONFIG_BOOTARGS #undef CONFIG_BOOTCOMMAND #define CONFIG_PREBOOT /* enable preboot variable */ +#define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ + #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -106,7 +115,7 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ @@ -122,18 +131,18 @@ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_SYS_BASE_BAUD 806400 /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ - { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ - 57600, 115200, 230400, 460800, 921600 } + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ @@ -158,8 +167,6 @@ #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable */ - #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ @@ -180,10 +187,12 @@ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* 256 kB for Monitor */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ +#define CONFIG_PRAM 0 /* use pram variable to overwrite */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -200,6 +209,7 @@ #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ +#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ @@ -207,23 +217,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ -/* - * JFFS2 partitions - second bank contains u-boot - * No command line, one static partition, whole device - */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0x01b00000 -#define CONFIG_JFFS2_PART_OFFSET 0x00400000 - -/* - * mtdparts command line support - * Note: fake mtd_id used, no linux mtd map file - */ -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=pmc405-0" -#define MTDPARTS_DEFAULT "mtdparts=pmc405-0:-(jffs2)" - /* * Environment Variable setup */ @@ -240,14 +233,17 @@ * I2C EEPROM (CAT24WC16) for environment */ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ + /* 16 byte page write mode using*/ + /* last 4 bits of the address */ + #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ /* @@ -287,7 +283,7 @@ * FPGA stuff */ #define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_FPGA_MAX_SIZE (32 * 1024) /* 32kByte for CPLD */ /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ @@ -302,6 +298,7 @@ /* * GPIOs */ +#define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ #define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ #define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ @@ -339,4 +336,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + #endif /* __CONFIG_H */ -- cgit v1.2.3 From f50fe4bd613c6d35a2c34055f02e9501dd6a9ad5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 18 Feb 2009 14:05:37 +0100 Subject: ppc4xx: Some more PMC405 coding-style cleanup Signed-off-by: Stefan Roese --- board/esd/pmc405/pmc405.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) (limited to 'board') diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c index 10e7ce420..94caa6c5e 100644 --- a/board/esd/pmc405/pmc405.c +++ b/board/esd/pmc405/pmc405.c @@ -72,22 +72,22 @@ int board_early_init_f (void) /* * Setup GPIO pins */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \ - CONFIG_SYS_FPGA_DONE | \ - CONFIG_SYS_XEREADY | \ - CONFIG_SYS_NONMONARCH | \ + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | + CONFIG_SYS_FPGA_DONE | + CONFIG_SYS_XEREADY | + CONFIG_SYS_NONMONARCH | CONFIG_SYS_REV1_2) << 5)); - if (!(in_be32((void*)GPIO0_IR) & CONFIG_SYS_REV1_2)) { + if (!(in_be32((void *)GPIO0_IR) & CONFIG_SYS_REV1_2)) { /* rev 1.2 boards */ - mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \ + mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | CONFIG_SYS_SELF_RST) << 5)); } - out_be32((void*)GPIO0_OR, CONFIG_SYS_VPEN); + out_be32((void *)GPIO0_OR, CONFIG_SYS_VPEN); /* setup for output */ - out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | \ - CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN); + out_be32((void *)GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | + CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY | CONFIG_SYS_VPEN); /* * - check if rev1_2 is low, then: @@ -104,15 +104,16 @@ int misc_init_r (void) gd->bd->bi_flashoffset = 0; /* deassert EREADY# */ - out_be32((void*)GPIO0_OR, - in_be32((void*)GPIO0_OR) | CONFIG_SYS_XEREADY); + out_be32((void *)GPIO0_OR, + in_be32((void *)GPIO0_OR) | CONFIG_SYS_XEREADY); return (0); } ushort pmc405_pci_subsys_deviceid(void) { ulong val; - val = in_be32((void*)GPIO0_IR); + + val = in_be32((void *)GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ /* check monarch# signal */ if (val & CONFIG_SYS_NONMONARCH) @@ -128,9 +129,8 @@ ushort pmc405_pci_subsys_deviceid(void) int checkboard (void) { ulong val; - char str[64]; - int i = getenv_r ("serial#", str, sizeof(str)); + int i = getenv_r("serial#", str, sizeof(str)); puts ("Board: "); @@ -139,7 +139,7 @@ int checkboard (void) else puts(str); - val = in_be32((void*)GPIO0_IR); + val = in_be32((void *)GPIO0_IR); if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */ puts(" rev1.2 ("); if (val & CONFIG_SYS_NONMONARCH) /* monarch# signal */ -- cgit v1.2.3