From c360ceac0286159f94d9d1a9496fc9858c8d9bec Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Sat, 14 Mar 2009 12:48:30 +0800 Subject: fsl-ddr: add the DDR3 SPD infrastructure - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu Signed-off-by: Travis Wheatley --- cpu/mpc85xx/ddr-gen3.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'cpu/mpc85xx') diff --git a/cpu/mpc85xx/ddr-gen3.c b/cpu/mpc85xx/ddr-gen3.c index 99c325a4f..8ac3d5fbe 100644 --- a/cpu/mpc85xx/ddr-gen3.c +++ b/cpu/mpc85xx/ddr-gen3.c @@ -98,10 +98,12 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif /* - * 200 painful micro-seconds must elapse between + * 500 painful micro-seconds must elapse between * the DDR clock setup and the DDR config enable. + * DDR2 need 200 us, and DDR3 need 500 us from spec, + * we choose the max, that is 500 us for all of case. */ - udelay(200); + udelay(500); asm volatile("sync;isync"); /* Let the controller go */ -- cgit v1.2.3