From e7ee23ec1788d8cf269a4cf6b9cd3722cbc7d592 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 17 Jul 2009 10:14:45 -0500 Subject: 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- cpu/mpc86xx/ddr-8641.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpu/mpc86xx/ddr-8641.c') diff --git a/cpu/mpc86xx/ddr-8641.c b/cpu/mpc86xx/ddr-8641.c index 51d0102ce..b8f2c9387 100644 --- a/cpu/mpc86xx/ddr-8641.c +++ b/cpu/mpc86xx/ddr-8641.c @@ -56,7 +56,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); - out_be32(&ddr->sdram_mode_1, regs->ddr_sdram_mode); + out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); out_be32(&ddr->sdram_mode_cntl, regs->ddr_sdram_md_cntl); out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); @@ -74,7 +74,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, udelay(200); asm volatile("sync;isync"); - out_be32(&ddr->sdram_cfg_1, regs->ddr_sdram_cfg); + out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); /* * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done -- cgit v1.2.3