From 5b0055547f0246908b79cc300170d87380b69e18 Mon Sep 17 00:00:00 2001 From: Dave Liu Date: Wed, 25 Feb 2009 12:31:32 +0800 Subject: 83xx: Fix some bugs in spd sdram code 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund Reported-by: Joakim Tjernlund Signed-off-by: Dave Liu Signed-off-by: Kim Phillips --- cpu/mpc83xx/spd_sdram.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) (limited to 'cpu') diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index 42a4e675d..ff15cda7a 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -319,7 +319,20 @@ long int spd_sdram() ddrc_clk = gd->mem_clk / 1000000; effective_data_rate = 0; - if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ + if (max_data_rate >= 460) { /* it is DDR2-800, 667, 533 */ + if (spd.cas_lat & 0x08) + caslat = 3; + else + caslat = 4; + if (ddrc_clk <= 460 && ddrc_clk > 350) + effective_data_rate = 400; + else if (ddrc_clk <=350 && ddrc_clk > 280) + effective_data_rate = 333; + else if (ddrc_clk <= 280 && ddrc_clk > 230) + effective_data_rate = 266; + else + effective_data_rate = 200; + } else if (max_data_rate >= 390 && max_data_rate < 460) { /* it is DDR 400 */ if (ddrc_clk <= 460 && ddrc_clk > 350) { /* DDR controller clk at 350~460 */ effective_data_rate = 400; /* 5ns */ @@ -466,6 +479,8 @@ long int spd_sdram() } else { twr_clk = picos_to_clk(spd.twr * 250); twtr_clk = picos_to_clk(spd.twtr * 250); + if (twtr_clk < 2) + twtr_clk = 2; } /* @@ -529,7 +544,7 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2 && (odt_wr_cfg || odt_rd_cfg) && (caslat < 4)) { - add_lat = trcd_clk - 1; + add_lat = 4 - caslat; if ((add_lat + caslat) < 4) { add_lat = 0; } @@ -566,6 +581,9 @@ long int spd_sdram() /* Convert SPD value from quarter nanos to picos. */ trtp_clk = picos_to_clk(spd.trtp * 250); + if (trtp_clk < 2) + trtp_clk = 2; + trtp_clk += add_lat; cke_min_clk = 3; /* By the book. */ four_act = picos_to_clk(37500); /* By the book. 1k pages? */ @@ -579,7 +597,9 @@ long int spd_sdram() if (spd.mem_type == SPD_MEMTYPE_DDR2) { if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ - } else if (effective_data_rate == 333 || effective_data_rate == 400) { + } else if (effective_data_rate == 333) { + cpo = 0x6; /* READ_LAT + 1 */ + } else if (effective_data_rate == 400) { cpo = 0x7; /* READ_LAT + 5/4 */ } else { /* Automatic calibration */ -- cgit v1.2.3 From f70fd13e2fe4cf58e251271c27f9c06e141d7f9a Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 24 Feb 2009 11:30:51 +0100 Subject: 8360, kmeter1: added bootcount feature. add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU. The bootcounter uses 8 bytes from the muram, because no other memory was found on this CPU for the bootcount feature. So we must correct the muram size in DTS before booting Linux. This feature is actual only implemented for MPC8360, because not all 83xx CPU have qe, and therefore no muram, which this feature uses. Signed-off-by: Heiko Schocher Signed-off-by: Kim Phillips --- cpu/mpc83xx/cpu.c | 34 ++++++++++++++++++++++++++++++++++ cpu/mpc83xx/fdt.c | 18 ++++++++++++++++++ 2 files changed, 52 insertions(+) (limited to 'cpu') diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 9e0a05d61..876f5c731 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -35,6 +35,10 @@ #include #include #include +#ifdef CONFIG_BOOTCOUNT_LIMIT +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -399,3 +403,33 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +#if !defined(CONFIG_MPC8360) +#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" +#endif + +#if !defined(CONFIG_BOOTCOUNT_ADDR) +#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) +#endif + +#include + +void bootcount_store (ulong a) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + out_be32 (reg, a); + out_be32 (reg + 4, BOOTCOUNT_MAGIC); +} + +ulong bootcount_load (void) +{ + void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); + + if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32 (reg); +} +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index f89077588..4cc904737 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -32,6 +32,20 @@ extern void ft_qe_setup(void *blob); DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360) +#include + +void fdt_fixup_muram (void *blob) +{ + ulong data[2]; + + data[0] = 0; + data[1] = QE_MURAM_SIZE - 2 * sizeof(unsigned long); + do_fixup_by_path(blob, "/qe/muram/data-only", "reg", + data, sizeof (data), 0); +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; @@ -83,4 +97,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#if defined(CONFIG_BOOTCOUNT_LIMIT) + fdt_fixup_muram (blob); +#endif } -- cgit v1.2.3