From f793a3581901ff39c2abb94012d9bbc8573ccf02 Mon Sep 17 00:00:00 2001
From: David Brownell <david-b@pacbell.net>
Date: Wed, 16 Apr 2008 22:57:58 -0700
Subject: avr32: Disable the AP7000 internal watchdog on startup

This patch forces the watchdog off in all cases.  That will at least
get rid of the constant reboot cycle, though it won't let the watchdog
actually run in the new kernels:  its probe() comes up with a polite
warning.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'cpu')

diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index 311466b78..4542e6797 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -86,6 +86,10 @@ int cpu_init(void)
 	extern void _evba(void);
 	char *p;
 
+	/* in case of soft resets, disable watchdog */
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
+
 	gd->cpu_hz = CFG_OSC0_HZ;
 
 	/* TODO: Move somewhere else, but needs to be run before we
-- 
cgit v1.2.3


From 781eb9a1e4af4bd34c138e6126ec5cc6dd4b5440 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Tue, 29 Apr 2008 12:53:05 +0200
Subject: avr32: Get rid of the .flashprog section

The .flashprog section was only needed back when we were running
directly from flash, and it's even more useless on NGW100 since it
uses the CFI flash driver which never used this workaround in the
first place.

Remove it on STK1000 as well, and get rid of all the associated code and
annotations.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 board/atmel/atngw100/u-boot.lds  | 8 --------
 board/atmel/atstk1000/flash.c    | 6 +++---
 board/atmel/atstk1000/u-boot.lds | 8 --------
 cpu/at32ap/cpu.c                 | 6 ------
 include/asm-avr32/sections.h     | 7 -------
 5 files changed, 3 insertions(+), 32 deletions(-)

(limited to 'cpu')

diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds
index 34e347aec..3c878d865 100644
--- a/board/atmel/atngw100/u-boot.lds
+++ b/board/atmel/atngw100/u-boot.lds
@@ -32,14 +32,6 @@ SECTIONS
 		*(.text)
 		*(.text.*)
 	}
-
-	. = ALIGN(32);
-	__flashprog_start = .;
-	.flashprog : {
-		*(.flashprog)
-	}
-	. = ALIGN(32);
-	__flashprog_end = .;
 	_etext = .;
 
 	.rodata : {
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
index 40478258e..12537f314 100644
--- a/board/atmel/atstk1000/flash.c
+++ b/board/atmel/atstk1000/flash.c
@@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 flash_info_t flash_info[1];
 
-static void __flashprog flash_identify(uint16_t *flash, flash_info_t *info)
+static void flash_identify(uint16_t *flash, flash_info_t *info)
 {
 	unsigned long flags;
 
@@ -76,7 +76,7 @@ void flash_print_info(flash_info_t *info)
 	       info->size >> 10, info->sector_count);
 }
 
-int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
+int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
 	unsigned long flags;
 	unsigned long start_time;
@@ -154,7 +154,7 @@ int __flashprog flash_erase(flash_info_t *info, int s_first, int s_last)
 	return ERR_OK;
 }
 
-int __flashprog write_buff(flash_info_t *info, uchar *src,
+int write_buff(flash_info_t *info, uchar *src,
 			   ulong addr, ulong count)
 {
 	unsigned long flags;
diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds
index 247812e10..f63bc4ff2 100644
--- a/board/atmel/atstk1000/u-boot.lds
+++ b/board/atmel/atstk1000/u-boot.lds
@@ -32,14 +32,6 @@ SECTIONS
 		*(.text)
 		*(.text.*)
 	}
-
-	. = ALIGN(32);
-	__flashprog_start = .;
-	.flashprog : {
-		*(.flashprog)
-	}
-	. = ALIGN(32);
-	__flashprog_end = .;
 	_etext = .;
 
 	.rodata : {
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index 4542e6797..a7a66cc1a 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -84,7 +84,6 @@ static void pm_init(void)
 int cpu_init(void)
 {
 	extern void _evba(void);
-	char *p;
 
 	/* in case of soft resets, disable watchdog */
 	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
@@ -104,11 +103,6 @@ int cpu_init(void)
 	sysreg_write(EVBA, (unsigned long)&_evba);
 	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
 
-	/* Lock everything that mess with the flash in the icache */
-	for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
-	     p += CFG_ICACHE_LINESZ)
-		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
-
 	return 0;
 }
 
diff --git a/include/asm-avr32/sections.h b/include/asm-avr32/sections.h
index 75373abde..fe819b2db 100644
--- a/include/asm-avr32/sections.h
+++ b/include/asm-avr32/sections.h
@@ -25,15 +25,8 @@
 /* References to section boundaries */
 
 extern char _text[], _etext[];
-extern char __flashprog_start[], __flashprog_end[];
 extern char _data[], __data_lma[], _edata[], __edata_lma[];
 extern char __got_start[], __got_lma[], __got_end[];
 extern char _end[];
 
-/*
- * Everything in .flashprog will be locked in the icache so it doesn't
- * get disturbed when executing flash commands.
- */
-#define __flashprog __attribute__((section(".flashprog"), __noinline__))
-
 #endif /* __ASM_AVR32_SECTIONS_H */
-- 
cgit v1.2.3


From a9b2bb78a1bd8ebdb633509bdd1c8134d527b213 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Wed, 30 Apr 2008 14:36:47 +0200
Subject: avr32: Remove unused file cpu/at32ap/pm.c

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/pm.c | 42 ------------------------------------------
 1 file changed, 42 deletions(-)
 delete mode 100644 cpu/at32ap/pm.c

(limited to 'cpu')

diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c
deleted file mode 100644
index c78d547f8..000000000
--- a/cpu/at32ap/pm.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#ifdef CFG_POWER_MANAGER
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#include <asm/arch/memory-map.h>
-
-#include "sm.h"
-
-
-#ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
-#else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-#endif /* CFG_POWER_MANAGER */
-- 
cgit v1.2.3


From 4f5972c3b2454c22957f2842cfe64ec8118e015b Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Wed, 30 Apr 2008 16:15:57 +0200
Subject: avr32: Use new-style Makefile for the at32ap platform

This makes it easier to avoid compiling certain files later.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/Makefile | 21 ++++++++++++++-------
 1 file changed, 14 insertions(+), 7 deletions(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index f69b1f385..8e384c7e0 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -27,13 +27,20 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(CPU).a
 
-START	:= start.o
-SOBJS	:= entry.o
-COBJS	:= cpu.o hsdramc.o exception.o cache.o
-COBJS	+= interrupts.o pio.o atmel_mci.o
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
+START-y			+= start.o
+
+SOBJS-y			+= entry.o
+COBJS-y			+= cpu.o
+COBJS-y			+= hsdramc.o
+COBJS-y			+= exception.o
+COBJS-y			+= cache.o
+COBJS-y			+= interrupts.o
+COBJS-y			+= pio.o
+COBJS-y			+= atmel_mci.o
+
+SRCS	:= $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START	:= $(addprefix $(obj),$(START-y))
 
 all: $(obj).depend $(START) $(LIB)
 
-- 
cgit v1.2.3


From 3ace2527ba80bd2fe1bceaab50d0b3c4fb5dd020 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Fri, 2 May 2008 15:21:40 +0200
Subject: avr32: Rename pm_init() as clk_init() and make SoC-specific

pm_init() was always more about clock initialization than anything
else. Dealing with PLLs, clock gating and such is also inherently
SoC-specific, so move it into a SoC-specific directory.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/at32ap700x/Makefile          |   2 +-
 cpu/at32ap/at32ap700x/clk.c             |  68 +++++++++++
 cpu/at32ap/at32ap700x/sm.h              | 204 ++++++++++++++++++++++++++++++++
 cpu/at32ap/cpu.c                        |  48 +-------
 cpu/at32ap/sm.h                         | 204 --------------------------------
 include/asm-avr32/arch-at32ap700x/clk.h |   2 +
 6 files changed, 280 insertions(+), 248 deletions(-)
 create mode 100644 cpu/at32ap/at32ap700x/clk.c
 create mode 100644 cpu/at32ap/at32ap700x/sm.h
 delete mode 100644 cpu/at32ap/sm.h

(limited to 'cpu')

diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile
index d27671211..740423563 100644
--- a/cpu/at32ap/at32ap700x/Makefile
+++ b/cpu/at32ap/at32ap700x/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(SOC).a
 
-COBJS	:= gpio.o
+COBJS	:= gpio.o clk.o
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c
new file mode 100644
index 000000000..b3aa03495
--- /dev/null
+++ b/cpu/at32ap/at32ap700x/clk.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2005-2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+
+#include "sm.h"
+
+void clk_init(void)
+{
+	uint32_t cksel;
+
+	/* in case of soft resets, disable watchdog */
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
+
+#ifdef CONFIG_PLL
+	/* Initialize the PLL */
+	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
+			    | SM_BF(PLLOSC, 0)
+			    | SM_BIT(PLLEN)));
+
+	/* Wait for lock */
+	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
+#endif
+
+	/* Set up clocks for the CPU and all peripheral buses */
+	cksel = 0;
+	if (CFG_CLKDIV_CPU)
+		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+	if (CFG_CLKDIV_HSB)
+		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+	if (CFG_CLKDIV_PBA)
+		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+	if (CFG_CLKDIV_PBB)
+		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+	sm_writel(PM_CKSEL, cksel);
+
+#ifdef CONFIG_PLL
+	/* Use PLL0 as main clock */
+	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
diff --git a/cpu/at32ap/at32ap700x/sm.h b/cpu/at32ap/at32ap700x/sm.h
new file mode 100644
index 000000000..6492c8e81
--- /dev/null
+++ b/cpu/at32ap/at32ap700x/sm.h
@@ -0,0 +1,204 @@
+/*
+ * Register definitions for System Manager
+ */
+#ifndef __CPU_AT32AP_SM_H__
+#define __CPU_AT32AP_SM_H__
+
+/* SM register offsets */
+#define SM_PM_MCCTRL				0x0000
+#define SM_PM_CKSEL				0x0004
+#define SM_PM_CPU_MASK				0x0008
+#define SM_PM_HSB_MASK				0x000c
+#define SM_PM_PBA_MASK				0x0010
+#define SM_PM_PBB_MASK				0x0014
+#define SM_PM_PLL0				0x0020
+#define SM_PM_PLL1				0x0024
+#define SM_PM_VCTRL				0x0030
+#define SM_PM_VMREF				0x0034
+#define SM_PM_VMV				0x0038
+#define SM_PM_IER				0x0040
+#define SM_PM_IDR				0x0044
+#define SM_PM_IMR				0x0048
+#define SM_PM_ISR				0x004c
+#define SM_PM_ICR				0x0050
+#define SM_PM_GCCTRL				0x0060
+#define SM_RTC_CTRL				0x0080
+#define SM_RTC_VAL				0x0084
+#define SM_RTC_TOP				0x0088
+#define SM_RTC_IER				0x0090
+#define SM_RTC_IDR				0x0094
+#define SM_RTC_IMR				0x0098
+#define SM_RTC_ISR				0x009c
+#define SM_RTC_ICR				0x00a0
+#define SM_WDT_CTRL				0x00b0
+#define SM_WDT_CLR				0x00b4
+#define SM_WDT_EXT				0x00b8
+#define SM_RC_RCAUSE				0x00c0
+#define SM_EIM_IER				0x0100
+#define SM_EIM_IDR				0x0104
+#define SM_EIM_IMR				0x0108
+#define SM_EIM_ISR				0x010c
+#define SM_EIM_ICR				0x0110
+#define SM_EIM_MODE				0x0114
+#define SM_EIM_EDGE				0x0118
+#define SM_EIM_LEVEL				0x011c
+#define SM_EIM_TEST				0x0120
+#define SM_EIM_NMIC				0x0124
+
+/* Bitfields in PM_CKSEL */
+#define SM_CPUSEL_OFFSET			0
+#define SM_CPUSEL_SIZE				3
+#define SM_CPUDIV_OFFSET			7
+#define SM_CPUDIV_SIZE				1
+#define SM_HSBSEL_OFFSET			8
+#define SM_HSBSEL_SIZE				3
+#define SM_HSBDIV_OFFSET			15
+#define SM_HSBDIV_SIZE				1
+#define SM_PBASEL_OFFSET			16
+#define SM_PBASEL_SIZE				3
+#define SM_PBADIV_OFFSET			23
+#define SM_PBADIV_SIZE				1
+#define SM_PBBSEL_OFFSET			24
+#define SM_PBBSEL_SIZE				3
+#define SM_PBBDIV_OFFSET			31
+#define SM_PBBDIV_SIZE				1
+
+/* Bitfields in PM_PLL0 */
+#define SM_PLLEN_OFFSET				0
+#define SM_PLLEN_SIZE				1
+#define SM_PLLOSC_OFFSET			1
+#define SM_PLLOSC_SIZE				1
+#define SM_PLLOPT_OFFSET			2
+#define SM_PLLOPT_SIZE				3
+#define SM_PLLDIV_OFFSET			8
+#define SM_PLLDIV_SIZE				8
+#define SM_PLLMUL_OFFSET			16
+#define SM_PLLMUL_SIZE				8
+#define SM_PLLCOUNT_OFFSET			24
+#define SM_PLLCOUNT_SIZE			6
+#define SM_PLLTEST_OFFSET			31
+#define SM_PLLTEST_SIZE				1
+
+/* Bitfields in PM_VCTRL */
+#define SM_VAUTO_OFFSET				0
+#define SM_VAUTO_SIZE				1
+#define SM_PM_VCTRL_VAL_OFFSET			8
+#define SM_PM_VCTRL_VAL_SIZE			7
+
+/* Bitfields in PM_VMREF */
+#define SM_REFSEL_OFFSET			0
+#define SM_REFSEL_SIZE				4
+
+/* Bitfields in PM_VMV */
+#define SM_PM_VMV_VAL_OFFSET			0
+#define SM_PM_VMV_VAL_SIZE			8
+
+/* Bitfields in PM_ICR */
+#define SM_LOCK0_OFFSET				0
+#define SM_LOCK0_SIZE				1
+#define SM_LOCK1_OFFSET				1
+#define SM_LOCK1_SIZE				1
+#define SM_WAKE_OFFSET				2
+#define SM_WAKE_SIZE				1
+#define SM_VOK_OFFSET				3
+#define SM_VOK_SIZE				1
+#define SM_VMRDY_OFFSET				4
+#define SM_VMRDY_SIZE				1
+#define SM_CKRDY_OFFSET				5
+#define SM_CKRDY_SIZE				1
+
+/* Bitfields in PM_GCCTRL */
+#define SM_OSCSEL_OFFSET			0
+#define SM_OSCSEL_SIZE				1
+#define SM_PLLSEL_OFFSET			1
+#define SM_PLLSEL_SIZE				1
+#define SM_CEN_OFFSET				2
+#define SM_CEN_SIZE				1
+#define SM_CPC_OFFSET				3
+#define SM_CPC_SIZE				1
+#define SM_DIVEN_OFFSET				4
+#define SM_DIVEN_SIZE				1
+#define SM_DIV_OFFSET				8
+#define SM_DIV_SIZE				8
+
+/* Bitfields in RTC_CTRL */
+#define SM_PCLR_OFFSET				1
+#define SM_PCLR_SIZE				1
+#define SM_TOPEN_OFFSET				2
+#define SM_TOPEN_SIZE				1
+#define SM_CLKEN_OFFSET				3
+#define SM_CLKEN_SIZE				1
+#define SM_PSEL_OFFSET				8
+#define SM_PSEL_SIZE				16
+
+/* Bitfields in RTC_VAL */
+#define SM_RTC_VAL_VAL_OFFSET			0
+#define SM_RTC_VAL_VAL_SIZE			31
+
+/* Bitfields in RTC_TOP */
+#define SM_RTC_TOP_VAL_OFFSET			0
+#define SM_RTC_TOP_VAL_SIZE			32
+
+/* Bitfields in RTC_ICR */
+#define SM_TOPI_OFFSET				0
+#define SM_TOPI_SIZE				1
+
+/* Bitfields in WDT_CTRL */
+#define SM_KEY_OFFSET				24
+#define SM_KEY_SIZE				8
+
+/* Bitfields in RC_RCAUSE */
+#define SM_POR_OFFSET				0
+#define SM_POR_SIZE				1
+#define SM_BOD_OFFSET				1
+#define SM_BOD_SIZE				1
+#define SM_EXT_OFFSET				2
+#define SM_EXT_SIZE				1
+#define SM_WDT_OFFSET				3
+#define SM_WDT_SIZE				1
+#define SM_NTAE_OFFSET				4
+#define SM_NTAE_SIZE				1
+#define SM_SERP_OFFSET				5
+#define SM_SERP_SIZE				1
+
+/* Bitfields in EIM_EDGE */
+#define SM_INT0_OFFSET				0
+#define SM_INT0_SIZE				1
+#define SM_INT1_OFFSET				1
+#define SM_INT1_SIZE				1
+#define SM_INT2_OFFSET				2
+#define SM_INT2_SIZE				1
+#define SM_INT3_OFFSET				3
+#define SM_INT3_SIZE				1
+
+/* Bitfields in EIM_LEVEL */
+
+/* Bitfields in EIM_TEST */
+#define SM_TESTEN_OFFSET			31
+#define SM_TESTEN_SIZE				1
+
+/* Bitfields in EIM_NMIC */
+#define SM_EN_OFFSET				0
+#define SM_EN_SIZE				1
+
+/* Bit manipulation macros */
+#define SM_BIT(name)					\
+	(1 << SM_##name##_OFFSET)
+#define SM_BF(name,value)				\
+	(((value) & ((1 << SM_##name##_SIZE) - 1))	\
+	 << SM_##name##_OFFSET)
+#define SM_BFEXT(name,value)				\
+	(((value) >> SM_##name##_OFFSET)		\
+	 & ((1 << SM_##name##_SIZE) - 1))
+#define SM_BFINS(name,value,old)			\
+	(((old) & ~(((1 << SM_##name##_SIZE) - 1)	\
+		    << SM_##name##_OFFSET))		\
+	 | SM_BF(name,value))
+
+/* Register access macros */
+#define sm_readl(reg)					\
+	readl((void *)SM_BASE + SM_##reg)
+#define sm_writel(reg,value)				\
+	writel((value), (void *)SM_BASE + SM_##reg)
+
+#endif /* __CPU_AT32AP_SM_H__ */
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index a7a66cc1a..0ba836180 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -30,7 +30,6 @@
 #include <asm/arch/memory-map.h>
 
 #include "hsmc3.h"
-#include "sm.h"
 
 /* Sanity checks */
 #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)		\
@@ -44,51 +43,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void pm_init(void)
-{
-	uint32_t cksel;
-
-#ifdef CONFIG_PLL
-	/* Initialize the PLL */
-	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
-			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
-			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
-			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
-			    | SM_BF(PLLOSC, 0)
-			    | SM_BIT(PLLEN)));
-
-	/* Wait for lock */
-	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-	/* Set up clocks for the CPU and all peripheral buses */
-	cksel = 0;
-	if (CFG_CLKDIV_CPU)
-		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
-	if (CFG_CLKDIV_HSB)
-		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
-	if (CFG_CLKDIV_PBA)
-		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
-	if (CFG_CLKDIV_PBB)
-		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
-	sm_writel(PM_CKSEL, cksel);
-
-	gd->cpu_hz = get_cpu_clk_rate();
-
-#ifdef CONFIG_PLL
-	/* Use PLL0 as main clock */
-	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-#endif
-}
-
 int cpu_init(void)
 {
 	extern void _evba(void);
 
-	/* in case of soft resets, disable watchdog */
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
-	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
-
 	gd->cpu_hz = CFG_OSC0_HZ;
 
 	/* TODO: Move somewhere else, but needs to be run before we
@@ -98,8 +56,12 @@ int cpu_init(void)
 	hsmc3_writel(PULSE0, 0x0b0a0906);
 	hsmc3_writel(SETUP0, 0x00010002);
 
-	pm_init();
+	clk_init();
+
+	/* Update the CPU speed according to the PLL configuration */
+	gd->cpu_hz = get_cpu_clk_rate();
 
+	/* Set up the exception handler table and enable exceptions */
 	sysreg_write(EVBA, (unsigned long)&_evba);
 	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
 
diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/sm.h
deleted file mode 100644
index 6492c8e81..000000000
--- a/cpu/at32ap/sm.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * Register definitions for System Manager
- */
-#ifndef __CPU_AT32AP_SM_H__
-#define __CPU_AT32AP_SM_H__
-
-/* SM register offsets */
-#define SM_PM_MCCTRL				0x0000
-#define SM_PM_CKSEL				0x0004
-#define SM_PM_CPU_MASK				0x0008
-#define SM_PM_HSB_MASK				0x000c
-#define SM_PM_PBA_MASK				0x0010
-#define SM_PM_PBB_MASK				0x0014
-#define SM_PM_PLL0				0x0020
-#define SM_PM_PLL1				0x0024
-#define SM_PM_VCTRL				0x0030
-#define SM_PM_VMREF				0x0034
-#define SM_PM_VMV				0x0038
-#define SM_PM_IER				0x0040
-#define SM_PM_IDR				0x0044
-#define SM_PM_IMR				0x0048
-#define SM_PM_ISR				0x004c
-#define SM_PM_ICR				0x0050
-#define SM_PM_GCCTRL				0x0060
-#define SM_RTC_CTRL				0x0080
-#define SM_RTC_VAL				0x0084
-#define SM_RTC_TOP				0x0088
-#define SM_RTC_IER				0x0090
-#define SM_RTC_IDR				0x0094
-#define SM_RTC_IMR				0x0098
-#define SM_RTC_ISR				0x009c
-#define SM_RTC_ICR				0x00a0
-#define SM_WDT_CTRL				0x00b0
-#define SM_WDT_CLR				0x00b4
-#define SM_WDT_EXT				0x00b8
-#define SM_RC_RCAUSE				0x00c0
-#define SM_EIM_IER				0x0100
-#define SM_EIM_IDR				0x0104
-#define SM_EIM_IMR				0x0108
-#define SM_EIM_ISR				0x010c
-#define SM_EIM_ICR				0x0110
-#define SM_EIM_MODE				0x0114
-#define SM_EIM_EDGE				0x0118
-#define SM_EIM_LEVEL				0x011c
-#define SM_EIM_TEST				0x0120
-#define SM_EIM_NMIC				0x0124
-
-/* Bitfields in PM_CKSEL */
-#define SM_CPUSEL_OFFSET			0
-#define SM_CPUSEL_SIZE				3
-#define SM_CPUDIV_OFFSET			7
-#define SM_CPUDIV_SIZE				1
-#define SM_HSBSEL_OFFSET			8
-#define SM_HSBSEL_SIZE				3
-#define SM_HSBDIV_OFFSET			15
-#define SM_HSBDIV_SIZE				1
-#define SM_PBASEL_OFFSET			16
-#define SM_PBASEL_SIZE				3
-#define SM_PBADIV_OFFSET			23
-#define SM_PBADIV_SIZE				1
-#define SM_PBBSEL_OFFSET			24
-#define SM_PBBSEL_SIZE				3
-#define SM_PBBDIV_OFFSET			31
-#define SM_PBBDIV_SIZE				1
-
-/* Bitfields in PM_PLL0 */
-#define SM_PLLEN_OFFSET				0
-#define SM_PLLEN_SIZE				1
-#define SM_PLLOSC_OFFSET			1
-#define SM_PLLOSC_SIZE				1
-#define SM_PLLOPT_OFFSET			2
-#define SM_PLLOPT_SIZE				3
-#define SM_PLLDIV_OFFSET			8
-#define SM_PLLDIV_SIZE				8
-#define SM_PLLMUL_OFFSET			16
-#define SM_PLLMUL_SIZE				8
-#define SM_PLLCOUNT_OFFSET			24
-#define SM_PLLCOUNT_SIZE			6
-#define SM_PLLTEST_OFFSET			31
-#define SM_PLLTEST_SIZE				1
-
-/* Bitfields in PM_VCTRL */
-#define SM_VAUTO_OFFSET				0
-#define SM_VAUTO_SIZE				1
-#define SM_PM_VCTRL_VAL_OFFSET			8
-#define SM_PM_VCTRL_VAL_SIZE			7
-
-/* Bitfields in PM_VMREF */
-#define SM_REFSEL_OFFSET			0
-#define SM_REFSEL_SIZE				4
-
-/* Bitfields in PM_VMV */
-#define SM_PM_VMV_VAL_OFFSET			0
-#define SM_PM_VMV_VAL_SIZE			8
-
-/* Bitfields in PM_ICR */
-#define SM_LOCK0_OFFSET				0
-#define SM_LOCK0_SIZE				1
-#define SM_LOCK1_OFFSET				1
-#define SM_LOCK1_SIZE				1
-#define SM_WAKE_OFFSET				2
-#define SM_WAKE_SIZE				1
-#define SM_VOK_OFFSET				3
-#define SM_VOK_SIZE				1
-#define SM_VMRDY_OFFSET				4
-#define SM_VMRDY_SIZE				1
-#define SM_CKRDY_OFFSET				5
-#define SM_CKRDY_SIZE				1
-
-/* Bitfields in PM_GCCTRL */
-#define SM_OSCSEL_OFFSET			0
-#define SM_OSCSEL_SIZE				1
-#define SM_PLLSEL_OFFSET			1
-#define SM_PLLSEL_SIZE				1
-#define SM_CEN_OFFSET				2
-#define SM_CEN_SIZE				1
-#define SM_CPC_OFFSET				3
-#define SM_CPC_SIZE				1
-#define SM_DIVEN_OFFSET				4
-#define SM_DIVEN_SIZE				1
-#define SM_DIV_OFFSET				8
-#define SM_DIV_SIZE				8
-
-/* Bitfields in RTC_CTRL */
-#define SM_PCLR_OFFSET				1
-#define SM_PCLR_SIZE				1
-#define SM_TOPEN_OFFSET				2
-#define SM_TOPEN_SIZE				1
-#define SM_CLKEN_OFFSET				3
-#define SM_CLKEN_SIZE				1
-#define SM_PSEL_OFFSET				8
-#define SM_PSEL_SIZE				16
-
-/* Bitfields in RTC_VAL */
-#define SM_RTC_VAL_VAL_OFFSET			0
-#define SM_RTC_VAL_VAL_SIZE			31
-
-/* Bitfields in RTC_TOP */
-#define SM_RTC_TOP_VAL_OFFSET			0
-#define SM_RTC_TOP_VAL_SIZE			32
-
-/* Bitfields in RTC_ICR */
-#define SM_TOPI_OFFSET				0
-#define SM_TOPI_SIZE				1
-
-/* Bitfields in WDT_CTRL */
-#define SM_KEY_OFFSET				24
-#define SM_KEY_SIZE				8
-
-/* Bitfields in RC_RCAUSE */
-#define SM_POR_OFFSET				0
-#define SM_POR_SIZE				1
-#define SM_BOD_OFFSET				1
-#define SM_BOD_SIZE				1
-#define SM_EXT_OFFSET				2
-#define SM_EXT_SIZE				1
-#define SM_WDT_OFFSET				3
-#define SM_WDT_SIZE				1
-#define SM_NTAE_OFFSET				4
-#define SM_NTAE_SIZE				1
-#define SM_SERP_OFFSET				5
-#define SM_SERP_SIZE				1
-
-/* Bitfields in EIM_EDGE */
-#define SM_INT0_OFFSET				0
-#define SM_INT0_SIZE				1
-#define SM_INT1_OFFSET				1
-#define SM_INT1_SIZE				1
-#define SM_INT2_OFFSET				2
-#define SM_INT2_SIZE				1
-#define SM_INT3_OFFSET				3
-#define SM_INT3_SIZE				1
-
-/* Bitfields in EIM_LEVEL */
-
-/* Bitfields in EIM_TEST */
-#define SM_TESTEN_OFFSET			31
-#define SM_TESTEN_SIZE				1
-
-/* Bitfields in EIM_NMIC */
-#define SM_EN_OFFSET				0
-#define SM_EN_SIZE				1
-
-/* Bit manipulation macros */
-#define SM_BIT(name)					\
-	(1 << SM_##name##_OFFSET)
-#define SM_BF(name,value)				\
-	(((value) & ((1 << SM_##name##_SIZE) - 1))	\
-	 << SM_##name##_OFFSET)
-#define SM_BFEXT(name,value)				\
-	(((value) >> SM_##name##_OFFSET)		\
-	 & ((1 << SM_##name##_SIZE) - 1))
-#define SM_BFINS(name,value,old)			\
-	(((old) & ~(((1 << SM_##name##_SIZE) - 1)	\
-		    << SM_##name##_OFFSET))		\
-	 | SM_BF(name,value))
-
-/* Register access macros */
-#define sm_readl(reg)					\
-	readl((void *)SM_BASE + SM_##reg)
-#define sm_writel(reg,value)				\
-	writel((value), (void *)SM_BASE + SM_##reg)
-
-#endif /* __CPU_AT32AP_SM_H__ */
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h
index 309fda50e..4a1dd33b5 100644
--- a/include/asm-avr32/arch-at32ap700x/clk.h
+++ b/include/asm-avr32/arch-at32ap700x/clk.h
@@ -75,6 +75,8 @@ static inline unsigned long get_mci_clk_rate(void)
 }
 #endif
 
+extern void clk_init(void);
+
 /* Board code may need the SDRAM base clock as a compile-time constant */
 #define SDRAMC_BUS_HZ	(MAIN_CLK_RATE >> CFG_CLKDIV_HSB)
 
-- 
cgit v1.2.3


From caf83ea888a0220f41747d0b7748fa43b4a4bd49 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Fri, 2 May 2008 15:32:57 +0200
Subject: avr32: Use the same entry point for reset and exception handling

Since the reset vector is always aligned to a very large boundary, we
can save a couple of KB worth of alignment padding by placing the
exception vectors at the same address.

Deciding which one it is is easy: If we're handling an exception, the
CPU is in Exception mode. If we're starting up after reset, the CPU is
in Supervisor mode. So this adds a very minimal overhead to the reset
path (only executed once) and the exception handling path (normally
never executed at all.)

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 board/atmel/atngw100/u-boot.lds  |   1 +
 board/atmel/atstk1000/u-boot.lds |   1 +
 cpu/at32ap/Makefile              |   1 -
 cpu/at32ap/entry.S               |  64 -------------------
 cpu/at32ap/start.S               | 129 ++++++++++++++++++++++++++++++++++++---
 5 files changed, 122 insertions(+), 74 deletions(-)
 delete mode 100644 cpu/at32ap/entry.S

(limited to 'cpu')

diff --git a/board/atmel/atngw100/u-boot.lds b/board/atmel/atngw100/u-boot.lds
index 3c878d865..e736adf0f 100644
--- a/board/atmel/atngw100/u-boot.lds
+++ b/board/atmel/atngw100/u-boot.lds
@@ -29,6 +29,7 @@ SECTIONS
 	. = 0;
 	_text = .;
 	.text : {
+		*(.exception.text)
 		*(.text)
 		*(.text.*)
 	}
diff --git a/board/atmel/atstk1000/u-boot.lds b/board/atmel/atstk1000/u-boot.lds
index f63bc4ff2..0d3b19c64 100644
--- a/board/atmel/atstk1000/u-boot.lds
+++ b/board/atmel/atstk1000/u-boot.lds
@@ -29,6 +29,7 @@ SECTIONS
 	. = 0;
 	_text = .;
 	.text : {
+		*(.exception.text)
 		*(.text)
 		*(.text.*)
 	}
diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index 8e384c7e0..29f9c0d04 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -29,7 +29,6 @@ LIB	:= $(obj)lib$(CPU).a
 
 START-y			+= start.o
 
-SOBJS-y			+= entry.o
 COBJS-y			+= cpu.o
 COBJS-y			+= hsdramc.o
 COBJS-y			+= exception.o
diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S
deleted file mode 100644
index a6fc68867..000000000
--- a/cpu/at32ap/entry.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/sysreg.h>
-#include <asm/ptrace.h>
-
-	.section .text.exception,"ax"
-	.global	_evba
-	.type	_evba,@function
-	.align	10
-_evba:
-	.irp	x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
-	.align	2
-	rjmp	unknown_exception
-	.endr
-
-	.global	timer_interrupt_handler
-	.type	timer_interrupt_handler,@function
-	.align	2
-timer_interrupt_handler:
-	/*
-	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
-	 *
-	 * We're running at interrupt level 3, so we don't need to save
-	 * r8-r12 or lr to the stack.
-	 */
-	lda.w	r8, timer_overflow
-	ld.w	r9, r8[0]
-	mov	r10, -1
-	mtsr	SYSREG_COMPARE, r10
-	sub	r9, -1
-	st.w	r8[0], r9
-	rete
-
-	.type	unknown_exception, @function
-unknown_exception:
-	pushm	r0-r12
-	sub	r8, sp, REG_R12 - REG_R0 - 4
-	mov	r9, lr
-	mfsr	r10, SYSREG_RAR_EX
-	mfsr	r11, SYSREG_RSR_EX
-	pushm	r8-r11
-	mfsr	r12, SYSREG_ECR
-	mov	r11, sp
-	rcall	do_unknown_exception
-1:	rjmp	1b
diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S
index ab8c2b73d..907e9b153 100644
--- a/cpu/at32ap/start.S
+++ b/cpu/at32ap/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2006 Atmel Corporation
+ * Copyright (C) 2005-2008 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,12 +20,9 @@
  * MA 02111-1307 USA
  */
 #include <config.h>
+#include <asm/ptrace.h>
 #include <asm/sysreg.h>
 
-#ifndef PART_SPECIFIC_BOOTSTRAP
-# define PART_SPECIFIC_BOOTSTRAP
-#endif
-
 #define SYSREG_MMUCR_I_OFFSET	2
 #define SYSREG_MMUCR_S_OFFSET	4
 
@@ -34,11 +31,115 @@
 		    | SYSREG_BIT(FE) | SYSREG_BIT(RE)		\
 		    | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
 
-	.text
+	/*
+	 * To save some space, we use the same entry point for
+	 * exceptions and reset. This avoids lots of alignment padding
+	 * since the reset vector is always suitably aligned.
+	 */
+	.section .exception.text, "ax", @progbits
 	.global	_start
+	.global	_evba
+	.type	_start, @function
+	.type	_evba, @function
 _start:
-	PART_SPECIFIC_BOOTSTRAP
+	.size	_start, 0
+_evba:
+	.org	0x00
+	rjmp	unknown_exception	/* Unrecoverable exception */
+	.org	0x04
+	rjmp	unknown_exception	/* TLB multiple hit */
+	.org	0x08
+	rjmp	unknown_exception	/* Bus error data fetch */
+	.org	0x0c
+	rjmp	unknown_exception	/* Bus error instruction fetch */
+	.org	0x10
+	rjmp	unknown_exception	/* NMI */
+	.org	0x14
+	rjmp	unknown_exception	/* Instruction address */
+	.org	0x18
+	rjmp	unknown_exception	/* ITLB protection */
+	.org	0x1c
+	rjmp	unknown_exception	/* Breakpoint */
+	.org	0x20
+	rjmp	unknown_exception	/* Illegal opcode */
+	.org	0x24
+	rjmp	unknown_exception	/* Unimplemented instruction */
+	.org	0x28
+	rjmp	unknown_exception	/* Privilege violation */
+	.org	0x2c
+	rjmp	unknown_exception	/* Floating-point */
+	.org	0x30
+	rjmp	unknown_exception	/* Coprocessor absent */
+	.org	0x34
+	rjmp	unknown_exception	/* Data Address (read) */
+	.org	0x38
+	rjmp	unknown_exception	/* Data Address (write) */
+	.org	0x3c
+	rjmp	unknown_exception	/* DTLB Protection (read) */
+	.org	0x40
+	rjmp	unknown_exception	/* DTLB Protection (write) */
+	.org	0x44
+	rjmp	unknown_exception	/* DTLB Modified */
+
+	.org	0x50
+	rjmp	unknown_exception	/* ITLB Miss */
+	.org	0x60
+	rjmp	unknown_exception	/* DTLB Miss (read) */
+	.org	0x70
+	rjmp	unknown_exception	/* DTLB Miss (write) */
+
+	.size	_evba, . - _evba
+
+	.align	2
+	.type	unknown_exception, @function
+unknown_exception:
+	/* Figure out whether we're handling an exception (Exception
+	 * mode) or just booting (Supervisor mode). */
+	csrfcz	SYSREG_M1_OFFSET
+	brcc	at32ap_cpu_bootstrap
+
+	/* This is an exception. Complain. */
+	pushm	r0-r12
+	sub	r8, sp, REG_R12 - REG_R0 - 4
+	mov	r9, lr
+	mfsr	r10, SYSREG_RAR_EX
+	mfsr	r11, SYSREG_RSR_EX
+	pushm	r8-r11
+	mfsr	r12, SYSREG_ECR
+	mov	r11, sp
+	rcall	do_unknown_exception
+1:	rjmp	1b
+
+	/* The COUNT/COMPARE timer interrupt handler */
+	.global	timer_interrupt_handler
+	.type	timer_interrupt_handler,@function
+	.align	2
+timer_interrupt_handler:
+	/*
+	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+	 *
+	 * We're running at interrupt level 3, so we don't need to save
+	 * r8-r12 or lr to the stack.
+	 */
+	lda.w	r8, timer_overflow
+	ld.w	r9, r8[0]
+	mov	r10, -1
+	mtsr	SYSREG_COMPARE, r10
+	sub	r9, -1
+	st.w	r8[0], r9
+	rete
 
+	/*
+	 * CPU bootstrap after reset is handled here. SoC code may
+	 * override this in case they need to initialize oscillators,
+	 * etc.
+	 */
+	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
+	.global	at32ap_cpu_bootstrap
+	.weak	at32ap_cpu_bootstrap
+	.type	at32ap_cpu_bootstrap, @function
+	.align	2
+at32ap_cpu_bootstrap:
 	/* Reset the Status Register */
 	mov	r0, lo(SR_INIT)
 	orh	r0, hi(SR_INIT)
@@ -66,9 +167,16 @@ _start:
 	lddpc	pc, 1f
 
 	.align	2
-1:	.long	2f
+1:	.long	at32ap_low_level_init
+	.size	_start, . - _start
 
-2:	lddpc	sp, sp_init
+	/* Common CPU bootstrap code after oscillator/cache/etc. init */
+	.section .text.avr32ap_low_level_init, "ax", @progbits
+	.global	at32ap_low_level_init
+	.type	at32ap_low_level_init, @function
+	.align	2
+at32ap_low_level_init:
+	lddpc	sp, sp_init
 
 	/* Initialize the GOT pointer */
 	lddpc	r6, got_init
@@ -90,6 +198,7 @@ got_init:
 	 * Relocate the u-boot image into RAM and continue from there.
 	 * Does not return.
 	 */
+	.section .text.relocate_code,"ax",@progbits
 	.global	relocate_code
 	.type	relocate_code,@function
 relocate_code:
@@ -162,3 +271,5 @@ in_ram:
 	.align	2
 got_init_reloc:
 	.long	3b - _GLOBAL_OFFSET_TABLE_
+
+	.size	relocate_code, . - relocate_code
-- 
cgit v1.2.3


From 95107b7c028806919630bf02c653aa8f4f867c94 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Mon, 19 May 2008 11:27:37 +0200
Subject: avr32: Do stricter stack checking in the exception handler

Don't do a stack dump if the stack pointer is outside the memory area
reserved for stack.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/exception.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c
index 0672685cd..dc9c3002a 100644
--- a/cpu/at32ap/exception.c
+++ b/cpu/at32ap/exception.c
@@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
 	printf("CPU Mode: %s\n", cpu_modes[mode]);
 
 	/* Avoid exception loops */
-	if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
+	if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
+			|| regs->sp >= gd->stack_end)
 		printf("\nStack pointer seems bogus, won't do stack dump\n");
 	else
 		dump_mem("\nStack: ", regs->sp, gd->stack_end);
-- 
cgit v1.2.3


From a23e277c4a3a2bbc42d237aae29da3a8971e757f Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Mon, 19 May 2008 11:36:28 +0200
Subject: avr32: Rework SDRAM initialization code

This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.

  * Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
  * Remove memory test from sdram_init() and make caller responsible
    for verifying the SDRAM and determining its size.
  * Remove base_address member from struct sdram_config (was sdram_info)
  * Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
  * Add support for a common STK1000 hack: 16MB SDRAM instead of 8.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 board/atmel/atngw100/atngw100.c                |  21 ++++-
 board/atmel/atstk1000/atstk1000.c              |  42 +++++++---
 cpu/at32ap/hsdramc.c                           | 102 ++++++++++---------------
 include/asm-avr32/arch-at32ap700x/memory-map.h |  20 +++++
 include/asm-avr32/sdram.h                      |  27 +++++--
 include/configs/atngw100.h                     |  21 ++---
 include/configs/atstk1002.h                    |  13 ++--
 include/configs/atstk1003.h                    |  13 ++--
 include/configs/atstk1004.h                    |  14 ++--
 include/configs/atstk1006.h                    |  13 ++--
 10 files changed, 166 insertions(+), 120 deletions(-)

(limited to 'cpu')

diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c
index 3ff6f0feb..c649855d6 100644
--- a/board/atmel/atngw100/atngw100.c
+++ b/board/atmel/atngw100/atngw100.c
@@ -29,8 +29,8 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_16BIT,
 	.row_bits	= 13,
 	.col_bits	= 9,
 	.bank_bits	= 2,
@@ -66,7 +66,22 @@ int board_early_init_f(void)
 
 long int initdram(int board_type)
 {
-	return sdram_init(&sdram);
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %u of %u MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
 }
 
 void board_init_info(void)
diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c
index 52fec65c1..33bdba6f5 100644
--- a/board/atmel/atstk1000/atstk1000.c
+++ b/board/atmel/atstk1000/atstk1000.c
@@ -29,10 +29,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_ATSTK1006
-/* Dual MT48LC16M16A2-7E on daughterboard */
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+static const struct sdram_config sdram_config = {
+#if defined(CONFIG_ATSTK1006)
+	/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
+	.data_bits	= SDRAM_DATA_32BIT,
 	.row_bits	= 13,
 	.col_bits	= 9,
 	.bank_bits	= 2,
@@ -45,12 +45,19 @@ static const struct sdram_info sdram = {
 	.txsr		= 7,
 	/* 7.81 us */
 	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
 #else
-/* MT48LC2M32B2-5 on motherboard */
-static const struct sdram_info sdram = {
-	.phys_addr	= CFG_SDRAM_BASE,
+	/* MT48LC2M32B2P-5 (8 MB) on motherboard */
+#ifdef CONFIG_ATSTK1004
+	.data_bits	= SDRAM_DATA_16BIT,
+#else
+	.data_bits	= SDRAM_DATA_32BIT,
+#endif
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+	/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+	.row_bits	= 12,
+#else
 	.row_bits	= 11,
+#endif
 	.col_bits	= 8,
 	.bank_bits	= 2,
 	.cas		= 3,
@@ -62,8 +69,8 @@ static const struct sdram_info sdram = {
 	.txsr		= 5,
 	/* 15.6 us */
 	.refresh_period	= (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
 #endif
+};
 
 int board_early_init_f(void)
 {
@@ -85,7 +92,22 @@ int board_early_init_f(void)
 
 long int initdram(int board_type)
 {
-	return sdram_init(&sdram);
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %u of %u MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
 }
 
 void board_init_info(void)
diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c
index 1fcfe75d7..992612b46 100644
--- a/cpu/at32ap/hsdramc.c
+++ b/cpu/at32ap/hsdramc.c
@@ -30,39 +30,32 @@
 
 #include "hsdramc1.h"
 
-unsigned long sdram_init(const struct sdram_info *info)
+unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
 {
-	unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
 	unsigned long sdram_size;
-	unsigned long tmp;
-	unsigned long bus_hz;
+	uint32_t cfgreg;
 	unsigned int i;
 
-	if (!info->refresh_period)
-		panic("ERROR: SDRAM refresh period == 0. "
-				"Please update the board code\n");
-
-	tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
-	       | HSDRAMC1_BF(NR, info->row_bits - 11)
-	       | HSDRAMC1_BF(NB, info->bank_bits - 1)
-	       | HSDRAMC1_BF(CAS, info->cas)
-	       | HSDRAMC1_BF(TWR, info->twr)
-	       | HSDRAMC1_BF(TRC, info->trc)
-	       | HSDRAMC1_BF(TRP, info->trp)
-	       | HSDRAMC1_BF(TRCD, info->trcd)
-	       | HSDRAMC1_BF(TRAS, info->tras)
-	       | HSDRAMC1_BF(TXSR, info->txsr));
-
-#ifdef CFG_SDRAM_16BIT
-	tmp |= HSDRAMC1_BIT(DBW);
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 1);
-#else
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 2);
-#endif
-
-	hsdramc1_writel(CR, tmp);
+	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
+		       | HSDRAMC1_BF(NR, config->row_bits - 11)
+		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
+		       | HSDRAMC1_BF(CAS, config->cas)
+		       | HSDRAMC1_BF(TWR, config->twr)
+		       | HSDRAMC1_BF(TRC, config->trc)
+		       | HSDRAMC1_BF(TRP, config->trp)
+		       | HSDRAMC1_BF(TRCD, config->trcd)
+		       | HSDRAMC1_BF(TRAS, config->tras)
+		       | HSDRAMC1_BF(TXSR, config->txsr));
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		cfgreg |= HSDRAMC1_BIT(DBW);
+
+	hsdramc1_writel(CR, cfgreg);
+
+	/* Send a NOP to turn on the clock (necessary on some chips) */
+	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
+	hsdramc1_readl(MR);
+	writel(0, sdram_base);
 
 	/*
 	 * Initialization sequence for SDRAM, from the data sheet:
@@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info)
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 3. Eight auto-refresh (CBR) cycles are provided
@@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info)
 	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
 	hsdramc1_readl(MR);
 	for (i = 0; i < 8; i++)
-		writel(0, sdram);
+		writel(0, sdram_base);
 
 	/*
 	 * 4. A mode register set (MRS) cycle is issued to program
 	 *    SDRAM parameters, in particular CAS latency and burst
 	 *    length.
 	 *
-	 * CAS from info struct, burst length 1, serial burst type
+	 * The address will be chosen by the SDRAMC automatically; we
+	 * just have to make sure BA[1:0] are set to 0.
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
 	hsdramc1_readl(MR);
-	writel(0, sdram + (info->cas << 4));
+	writel(0, sdram_base);
 
 	/*
-	 * 5. A Normal Mode command is provided, 3 clocks after tMRD
-	 *    is met.
-	 *
-	 * From the timing diagram, it looks like tMRD is 3
-	 * cycles...try a dummy read from the peripheral bus.
+	 * 5. The application must go into Normal Mode, setting Mode
+	 *    to 0 in the Mode Register and performing a write access
+	 *    at any location in the SDRAM.
 	 */
-	hsdramc1_readl(MR);
 	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 6. Write refresh rate into SDRAMC refresh timer count
 	 *    register (refresh rate = timing between refresh cycles).
-	 *
-	 * 15.6 us is a typical value for a burst of length one
 	 */
-	bus_hz = get_sdram_clk_rate();
-	hsdramc1_writel(TR, info->refresh_period);
-
-	printf("SDRAM: %u MB at address 0x%08lx\n",
-	       sdram_size >> 20, info->phys_addr);
-
-	printf("Testing SDRAM...");
-	for (i = 0; i < sdram_size / 4; i++)
-		sdram[i] = i;
-
-	for (i = 0; i < sdram_size / 4; i++) {
-		tmp = sdram[i];
-		if (tmp != i) {
-			printf("FAILED at address 0x%08lx\n",
-			       info->phys_addr + i * 4);
-			printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
-			return 0;
-		}
-	}
-
-	puts("OK\n");
+	hsdramc1_writel(TR, config->refresh_period);
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 1);
+	else
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 2);
 
 	return sdram_size;
 }
diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h
index 5513e88e7..6592c039f 100644
--- a/include/asm-avr32/arch-at32ap700x/memory-map.h
+++ b/include/asm-avr32/arch-at32ap700x/memory-map.h
@@ -22,6 +22,26 @@
 #ifndef __AT32AP7000_MEMORY_MAP_H__
 #define __AT32AP7000_MEMORY_MAP_H__
 
+/* Internal and external memories */
+#define EBI_SRAM_CS0_BASE			0x00000000
+#define EBI_SRAM_CS0_SIZE			0x04000000
+#define EBI_SRAM_CS4_BASE			0x04000000
+#define EBI_SRAM_CS4_SIZE			0x04000000
+#define EBI_SRAM_CS2_BASE			0x08000000
+#define EBI_SRAM_CS2_SIZE			0x04000000
+#define EBI_SRAM_CS3_BASE			0x0c000000
+#define EBI_SRAM_CS3_SIZE			0x04000000
+#define EBI_SRAM_CS1_BASE			0x10000000
+#define EBI_SRAM_CS1_SIZE			0x10000000
+#define EBI_SRAM_CS5_BASE			0x20000000
+#define EBI_SRAM_CS5_SIZE			0x04000000
+
+#define EBI_SDRAM_BASE				EBI_SRAM_CS1_BASE
+#define EBI_SDRAM_SIZE				EBI_SRAM_CS1_SIZE
+
+#define INTERNAL_SRAM_BASE			0x24000000
+#define INTERNAL_SRAM_SIZE			0x00008000
+
 /* Devices on the High Speed Bus (HSB) */
 #define LCDC_BASE				0xFF000000
 #define DMAC_BASE				0xFF200000
diff --git a/include/asm-avr32/sdram.h b/include/asm-avr32/sdram.h
index 833af6e6a..7bdefc1fd 100644
--- a/include/asm-avr32/sdram.h
+++ b/include/asm-avr32/sdram.h
@@ -22,15 +22,32 @@
 #ifndef __ASM_AVR32_SDRAM_H
 #define __ASM_AVR32_SDRAM_H
 
-struct sdram_info {
-	unsigned long phys_addr;
-	unsigned int row_bits, col_bits, bank_bits;
-	unsigned int cas, twr, trc, trp, trcd, tras, txsr;
+struct sdram_config {
+	/* Number of data bits. */
+	enum {
+		SDRAM_DATA_16BIT,
+		SDRAM_DATA_32BIT,
+	} data_bits;
+
+	/* Number of address bits */
+	uint8_t row_bits, col_bits, bank_bits;
+
+	/* SDRAM timings in cycles */
+	uint8_t cas, twr, trc, trp, trcd, tras, txsr;
 
 	/* SDRAM refresh period in cycles */
 	unsigned long refresh_period;
 };
 
-extern unsigned long sdram_init(const struct sdram_info *info);
+/*
+ * Attempt to initialize the SDRAM controller using the specified
+ * parameters. Return the expected size of the memory area based on
+ * the number of address and data bits.
+ *
+ * The caller should verify that the configuration is correct by
+ * running a memory test, e.g. get_ram_size().
+ */
+extern unsigned long sdram_init(void *sdram_base,
+			const struct sdram_config *config);
 
 #endif /* __ASM_AVR32_SDRAM_H */
diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h
index 313298a5c..3fc997563 100644
--- a/include/configs/atngw100.h
+++ b/include/configs/atngw100.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -140,11 +142,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -153,17 +153,10 @@
 #define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
 
 #define CFG_MALLOC_LEN			(256*1024)
-#define CFG_MALLOC_END							\
-	({								\
-		DECLARE_GLOBAL_DATA_PTR;				\
-		CFG_SDRAM_BASE + gd->sdram_size;			\
-	})
-#define CFG_MALLOC_START		(CFG_MALLOC_END - CFG_MALLOC_LEN)
-
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
@@ -173,7 +166,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)
 
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h
index f652b2871..ba18eb63c 100644
--- a/include/configs/atstk1002.h
+++ b/include/configs/atstk1002.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -170,10 +172,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -185,7 +186,7 @@
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
@@ -195,7 +196,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1003.h b/include/configs/atstk1003.h
index 2d981ccba..a528ddfb0 100644
--- a/include/configs/atstk1003.h
+++ b/include/configs/atstk1003.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7001		1
@@ -153,10 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -167,7 +168,7 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
@@ -177,7 +178,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1004.h b/include/configs/atstk1004.h
index 235c1cc9d..fc9585e84 100644
--- a/include/configs/atstk1004.h
+++ b/include/configs/atstk1004.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7002		1
@@ -153,11 +155,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
-#define CFG_SDRAM_16BIT			1
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -168,7 +168,7 @@
 #define CFG_MALLOC_LEN			(256*1024)
 
 /* Allow 2MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00200000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00200000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
@@ -178,7 +178,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x700000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h
index c606d5dcc..9fd49a53a 100644
--- a/include/configs/atstk1006.h
+++ b/include/configs/atstk1006.h
@@ -24,6 +24,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/memory-map.h>
+
 #define CONFIG_AVR32			1
 #define CONFIG_AT32AP			1
 #define CONFIG_AT32AP7000		1
@@ -170,10 +172,9 @@
 
 #define CFG_MONITOR_BASE		CFG_FLASH_BASE
 
-#define CFG_INTRAM_BASE			0x24000000
-#define CFG_INTRAM_SIZE			0x8000
-
-#define CFG_SDRAM_BASE			0x10000000
+#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
+#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
+#define CFG_SDRAM_BASE			EBI_SDRAM_BASE
 
 #define CFG_ENV_IS_IN_FLASH		1
 #define CFG_ENV_SIZE			65536
@@ -185,7 +186,7 @@
 #define CFG_DMA_ALLOC_LEN		(16384)
 
 /* Allow 4MB for the kernel run-time image */
-#define CFG_LOAD_ADDR			(CFG_SDRAM_BASE + 0x00400000)
+#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
 #define CFG_BOOTPARAMS_LEN		(16 * 1024)
 
 /* Other configuration settings that shouldn't have to change all that often */
@@ -195,7 +196,7 @@
 #define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_LONGHELP			1
 
-#define CFG_MEMTEST_START		CFG_SDRAM_BASE
+#define CFG_MEMTEST_START		EBI_SDRAM_BASE
 #define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x3f00000)
 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 
-- 
cgit v1.2.3


From 7a96ddadd13e6ac9a829affce9b6f8823f580e49 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Wed, 21 May 2008 11:10:59 +0200
Subject: avr32: Fix two warnings in atmel_mci.c

The warnings are harmless but annoying. Let's fix them.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/atmel_mci.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
index f59dfb599..3ce9ea532 100644
--- a/cpu/at32ap/atmel_mci.c
+++ b/cpu/at32ap/atmel_mci.c
@@ -182,12 +182,13 @@ static int mmc_acmd(unsigned long cmd, unsigned long arg,
 
 static unsigned long
 mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
-	  unsigned long *buffer)
+	  void *buffer)
 {
 	int ret, i = 0;
 	unsigned long resp[4];
 	unsigned long card_status, data;
 	unsigned long wordcount;
+	u32 *p = buffer;
 	u32 status;
 
 	if (blkcnt == 0)
@@ -225,7 +226,7 @@ mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
 			if (status & MMCI_BIT(RXRDY)) {
 				data = mmci_readl(RDR);
 				/* pr_debug("%x\n", data); */
-				*buffer++ = data;
+				*p++ = data;
 				wordcount++;
 			}
 		} while(wordcount < (mmc_blkdev.blksz / 4));
@@ -443,6 +444,7 @@ static void mci_set_data_timeout(struct mmc_csd *csd)
 
 	dtocyc = timeout_clks;
 	dtomul = 0;
+	shift = 0;
 	while (dtocyc > 15 && dtomul < 8) {
 		dtomul++;
 		shift = dtomul_to_shift[dtomul];
-- 
cgit v1.2.3


From e92a5bf8330654e33ac13f6b3058634e58f5d1c0 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Thu, 22 May 2008 12:28:25 +0200
Subject: avr32: Fix wrong error flags in atmel_mci driver

Make sure we check for CRC errors when sending commands that use CRC
checking.

Reported-by: Gururaja Hebbar K R <gururajakr@sanyo.co.in>
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/atmel_mci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
index 3ce9ea532..226b5c045 100644
--- a/cpu/at32ap/atmel_mci.c
+++ b/cpu/at32ap/atmel_mci.c
@@ -139,7 +139,7 @@ mmc_cmd(unsigned long cmd, unsigned long arg,
 
 	pr_debug("mmc: status 0x%08lx\n", status);
 
-	if (status & ERROR_FLAGS) {
+	if (status & error_flags) {
 		printf("mmc: command %lu failed (status: 0x%08lx)\n",
 		       cmd, status);
 		return -EIO;
-- 
cgit v1.2.3


From 48ea623eae8674793372e3e7c95e72e5a44d7a95 Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Wed, 21 May 2008 13:01:09 +0200
Subject: avr32: Compile atmel_mci.o conditionally

Remove #ifdef CONFIG_MMC from the source file and use conditional
compilation in the Makefile instead.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/Makefile    | 2 +-
 cpu/at32ap/atmel_mci.c | 4 ----
 2 files changed, 1 insertion(+), 5 deletions(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index 29f9c0d04..d16c58b77 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -35,7 +35,7 @@ COBJS-y			+= exception.o
 COBJS-y			+= cache.o
 COBJS-y			+= interrupts.o
 COBJS-y			+= pio.o
-COBJS-y			+= atmel_mci.o
+COBJS-$(CONFIG_MMC)	+= atmel_mci.o
 
 SRCS	:= $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
index 226b5c045..3795addf0 100644
--- a/cpu/at32ap/atmel_mci.c
+++ b/cpu/at32ap/atmel_mci.c
@@ -21,8 +21,6 @@
  */
 #include <common.h>
 
-#ifdef CONFIG_MMC
-
 #include <part.h>
 #include <mmc.h>
 
@@ -548,5 +546,3 @@ int mmc2info(ulong addr)
 {
 	return 0;
 }
-
-#endif /* CONFIG_MMC */
-- 
cgit v1.2.3


From a8092c021d27f27f4b323b7d49979ca01b3fc19d Mon Sep 17 00:00:00 2001
From: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Date: Mon, 26 May 2008 12:19:10 +0200
Subject: avr32: Fix theoretical race in udelay()

If the specified delay is very short, the cycle counter may go past the
"end" time we are waiting for before we get around to reading it.

Fix it by checking the different between the cycle count "now" and the
cycle count at the beginning. This will work as long as the delay
measured in number of cycles is below 2^31.

Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
---
 cpu/at32ap/interrupts.c | 16 +++++++---------
 1 file changed, 7 insertions(+), 9 deletions(-)

(limited to 'cpu')

diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c
index bef1f30d7..160838eee 100644
--- a/cpu/at32ap/interrupts.c
+++ b/cpu/at32ap/interrupts.c
@@ -98,18 +98,16 @@ void set_timer(unsigned long t)
  */
 void udelay(unsigned long usec)
 {
-	unsigned long now, end;
+	unsigned long cycles;
+	unsigned long base;
+	unsigned long now;
 
-	now = sysreg_read(COUNT);
+	base = sysreg_read(COUNT);
+	cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
 
-	end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
-	end += now;
-
-	while (now > end)
-		now = sysreg_read(COUNT);
-
-	while (now < end)
+	do {
 		now = sysreg_read(COUNT);
+	} while ((now - base) < cycles);
 }
 
 static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
-- 
cgit v1.2.3