From 2e72ad0644b940817a89a3590ce0d7b99c05c396 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Mon, 14 Jan 2008 17:11:47 -0600 Subject: ColdFire: PCI and misc updates for MCF5445x Signed-off-by: TsiChungLiew Signed-off by: John Rigby --- cpu/mcf5445x/cpu_init.c | 1 - cpu/mcf5445x/pci.c | 61 +++++++++++++++---------------------------------- cpu/mcf5445x/start.S | 25 ++++++++------------ 3 files changed, 27 insertions(+), 60 deletions(-) (limited to 'cpu') diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 6622eeea9..585216d6e 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -113,7 +113,6 @@ int cpu_init_r(void) #ifdef CONFIG_MCFTMR volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - u32 oscillator = CFG_RTC_OSCILLATOR; rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c index 8ace53630..039846928 100644 --- a/cpu/mcf5445x/pci.c +++ b/cpu/mcf5445x/pci.c @@ -46,48 +46,18 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose, \ u16 cfg_type = 0; \ addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ out_be32(hose->cfg_addr, addr); \ - __asm__ __volatile__("nop"); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ out_be32(hose->cfg_addr, addr & 0x7fffffff); \ - __asm__ __volatile__("nop"); \ return 0; \ } PCI_OP(read, byte, u8 *, in_8, 3) PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(read, dword, u32 *, in_le32, 0) PCI_OP(write, byte, u8, out_8, 3) PCI_OP(write, word, u16, out_le16, 2) PCI_OP(write, dword, u32, out_le32, 0) -int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, - int offset, u32 * val) -{ - u32 addr; - u32 tmpv; - u32 mask = 2; /* word access */ - /* Read lower 16 bits */ - addr = ((offset & 0xfc) | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("nop"); - *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("nop"); - - /* Read upper 16 bits */ - offset += 2; - addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("nop"); - tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("nop"); - - /* combine results into dword value */ - *val = (tmpv << 16) | *val; - - return 0; -} - void pci_mcf5445x_init(struct pci_controller *hose) { volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; @@ -95,7 +65,7 @@ void pci_mcf5445x_init(struct pci_controller *hose) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; u32 barEn = 0; - pciarb->acr = 0x001f001f; + pciarb->acr = 0x001F001F; /* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, PCIREQ2, PCIGNT2 */ @@ -104,53 +74,58 @@ void pci_mcf5445x_init(struct pci_controller *hose) GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0; + /* Assert reset bit */ + pci->gscr |= PCI_GSCR_PR; + pci->tcr1 |= PCI_TCR1_P; /* Initiator windows */ - pci->iw0btar = CFG_PCI_MEM_PHYS; - pci->iw1btar = CFG_PCI_IO_PHYS; - pci->iw2btar = CFG_PCI_CFG_PHYS; + pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); + pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); + pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16); pci->iwcr = PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + pci->icr = 0; + /* Enable bus master and mem access */ - pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M; + pci->scr = PCI_SCR_B | PCI_SCR_M; /* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF); + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); pci->cr2 = 0; #ifdef CFG_PCI_BAR0 pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B0E; + barEn |= PCI_TCR2_B0E; #endif #ifdef CFG_PCI_BAR1 pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B1E; + barEn |= PCI_TCR2_B1E; #endif #ifdef CFG_PCI_BAR2 pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B2E; + barEn |= PCI_TCR2_B2E; #endif #ifdef CFG_PCI_BAR3 pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B3E; + barEn |= PCI_TCR2_B3E; #endif #ifdef CFG_PCI_BAR4 pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B4E; + barEn |= PCI_TCR2_B4E; #endif #ifdef CFG_PCI_BAR5 pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B5E; + barEn |= PCI_TCR2_B5E; #endif pci->tcr2 = barEn; diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 423583d04..d64c5af0d 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -279,14 +279,13 @@ icache_enable: move.l (%a1), %d1 move.l #0x00040100, %d0 /* Invalidate icache */ - or.l %d1, %d0 movec %d0, %CACR - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */ + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ movec %d0, %ACR2 - or.l #0x00088400, %d1 /* Enable bcache and icache */ - movec %d1, %CACR + move.l #0x04088020, %d0 /* Enable bcache and icache */ + movec %d0, %CACR move.l #(ICACHE_STATUS), %a1 moveq #1, %d0 @@ -298,7 +297,7 @@ icache_disable: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0 - and.l #0xFFF77BFF, %d0 + move.l #0xFFF77BFF, %d0 or.l #0x00040100, %d0 /* Setup cache mask */ movec %d0, %CACR /* Invalidate icache */ clr.l %d0 @@ -321,7 +320,7 @@ icache_invalid: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0 - or.l #0x00040100, %d0 /* Invalidate icache */ + move.l #0x00040100, %d0 /* Invalidate icache */ movec %d0, %CACR /* Enable and invalidate cache */ rts @@ -330,17 +329,11 @@ dcache_enable: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d1 - move.l #0x01000000, %d0 - or.l %d1, %d0 + move.l #0x01040100, %d0 movec %d0, %CACR /* Invalidate dcache */ - move.l #(CFG_SDRAM_BASE + 0xc000), %d0 - movec %d0, %ACR0 - move.l #0, %d0 - movec %d0, %ACR1 - - or.l #0x80000000, %d1 /* Enable bcache and icache */ - movec %d1, %CACR + move.l #0x80088020, %d0 /* Enable bcache and icache */ + movec %d0, %CACR move.l #(DCACHE_STATUS), %a1 moveq #1, %d0 @@ -369,7 +362,7 @@ dcache_invalid: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0 - or.l #0x01000000, %d0 /* Setup cache mask */ + move.l #0x81088020, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable and invalidate cache */ rts -- cgit v1.2.3 From aa5f1f9dc815a76f6dffb580798599c028fe7feb Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Mon, 14 Jan 2008 17:23:08 -0600 Subject: ColdFire: Add M5373EVB platform support - 2 Signed-off-by: TsiChungLiew Signed-off by: John Rigby --- MAINTAINERS | 1 + MAKEALL | 3 +- Makefile | 10 ++ cpu/mcf532x/cpu.c | 20 ++- doc/README.m5373evb | 333 ++++++++++++++++++++++++++++++++++++++++++ include/asm-m68k/immap.h | 4 +- include/asm-m68k/immap_5329.h | 89 ++++++++--- include/asm-m68k/m5329.h | 5 + include/configs/M5373EVB.h | 267 +++++++++++++++++++++++++++++++++ 9 files changed, 708 insertions(+), 24 deletions(-) create mode 100644 doc/README.m5373evb create mode 100644 include/configs/M5373EVB.h (limited to 'cpu') diff --git a/MAINTAINERS b/MAINTAINERS index de0fbdf74..6b4bfe70d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -649,6 +649,7 @@ TsiChung Liew M5235EVB mcf52x2 M5329EVB mcf532x + M5373EVB mcf532x M54455EVB mcf5445x Hayden Fraser diff --git a/MAKEALL b/MAKEALL index c9bd5e1b7..4048f8b11 100755 --- a/MAKEALL +++ b/MAKEALL @@ -649,7 +649,8 @@ LIST_coldfire=" \ M5271EVB \ M5272C3 \ M5282EVB \ - M5329EVB \ + M5329AFEE \ + M5373EVB \ M54455EVB \ r5200 \ TASREG \ diff --git a/Makefile b/Makefile index 78546cf61..d6e4d74cd 100644 --- a/Makefile +++ b/Makefile @@ -1811,6 +1811,16 @@ M5329BFEE_config : unconfig fi @$(MKCONFIG) -a M5329EVB m68k mcf532x m5329evb freescale +M5373EVB_config : unconfig + @case "$@" in \ + M5373EVB_config) NAND=16;; \ + esac; \ + >include/config.h ; \ + if [ "$${NAND}" != "0" ] ; then \ + echo "#define NANDFLASH_SIZE $${NAND}" > $(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a M5373EVB m68k mcf532x m5373evb freescale + M54455EVB_config \ M54455EVB_atmel_config \ M54455EVB_intel_config \ diff --git a/cpu/mcf532x/cpu.c b/cpu/mcf532x/cpu.c index 89cc8ad93..61541ab0f 100644 --- a/cpu/mcf532x/cpu.c +++ b/cpu/mcf532x/cpu.c @@ -64,6 +64,18 @@ int checkcpu(void) case 0x61: id = 5327; break; + case 0x65: + id = 5373; + break; + case 0x68: + id = 53721; + break; + case 0x69: + id = 5372; + break; + case 0x6B: + id = 5372; + break; } if (id) { @@ -84,6 +96,7 @@ void watchdog_reset(void) volatile wdog_t *wdp = (wdog_t *) (MMAP_WDOG); wdp->sr = 0x5555; /* Count register */ + wdp->sr = 0xAAAA; /* Count register */ } int watchdog_disable(void) @@ -104,8 +117,11 @@ int watchdog_init(void) /* set timeout and enable watchdog */ wdog_module = ((CFG_CLK / 1000) * CONFIG_WATCHDOG_TIMEOUT); - wdog_module |= (wdog_module / 8192); - wdp->mr = wdog_module; +#ifdef CONFIG_M5329 + wdp->mr = (wdog_module / 8192); +#else + wdp->mr = (wdog_module / 4096); +#endif wdp->cr = WTM_WCR_EN; puts("WATCHDOG:enabled\n"); diff --git a/doc/README.m5373evb b/doc/README.m5373evb new file mode 100644 index 000000000..4f33b7dcf --- /dev/null +++ b/doc/README.m5373evb @@ -0,0 +1,333 @@ +Freescale MCF5373EVB ColdFire Development Board +================================================ + +TsiChung Liew(Tsi-Chung.Liew@freescale.com) +Created 11/08/07 +=========================================== + + +Changed files: +============== + +- board/freescale/m5373evb/m5373evb.c Dram setup +- board/freescale/m5373evb/mii.c Mii access +- board/freescale/m5373evb/Makefile Makefile +- board/freescale/m5373evb/config.mk config make +- board/freescale/m5373evb/u-boot.lds Linker description + +- cpu/mcf532x/cpu.c cpu specific code +- cpu/mcf532x/cpu_init.c FBCS, Mux pins, icache and RTC extra regs +- cpu/mcf532x/interrupts.c cpu specific interrupt support +- cpu/mcf532x/speed.c system, pci, flexbus, and cpu clock +- cpu/mcf532x/Makefile Makefile +- cpu/mcf532x/config.mk config make +- cpu/mcf532x/start.S start up assembly code + +- doc/README.m5373evb This readme file + +- drivers/net/mcffec.c ColdFire common FEC driver +- drivers/serial/mcfuart.c ColdFire common UART driver +- drivers/rtc/mcfrtc.c Realtime clock Driver + +- include/asm-m68k/bitops.h Bit operation function export +- include/asm-m68k/byteorder.h Byte order functions +- include/asm-m68k/fec.h FEC structure and definition +- include/asm-m68k/fsl_i2c.h I2C structure and definition +- include/asm-m68k/global_data.h Global data structure +- include/asm-m68k/immap.h ColdFire specific header file and driver macros +- include/asm-m68k/immap_532x.h mcf532x specific header file +- include/asm-m68k/io.h io functions +- include/asm-m68k/m532x.h mcf532x specific header file +- include/asm-m68k/posix_types.h Posix +- include/asm-m68k/processor.h header file +- include/asm-m68k/ptrace.h Exception structure +- include/asm-m68k/rtc.h Realtime clock header file +- include/asm-m68k/string.h String function export +- include/asm-m68k/timer.h Timer structure and definition +- include/asm-m68k/types.h Data types definition +- include/asm-m68k/uart.h Uart structure and definition +- include/asm-m68k/u-boot.h u-boot structure + +- include/configs/M5373EVB.h Board specific configuration file + +- lib_m68k/board.c board init function +- lib_m68k/cache.c +- lib_m68k/interrupts Coldfire common interrupt functions +- lib_m68k/m68k_linux.c +- lib_m68k/time.c Timer functions (Dma timer and PIT) +- lib_m68k/traps.c Exception init code + +1 MCF5373 specific Options/Settings +==================================== +1.1 pre-loader is no longer suppoer in thie coldfire family + +1.2 Configuration settings for M5373EVB Development Board +CONFIG_MCF532x -- define for all MCF532x CPUs +CONFIG_M5373 -- define for all Freescale MCF5373 CPUs +CONFIG_M5373EVB -- define for M5373EVB board + +CONFIG_MCFUART -- define to use common CF Uart driver +CFG_UART_PORT -- define UART port number, start with 0, 1 and 2 +CONFIG_BAUDRATE -- define UART baudrate + +CONFIG_MCFRTC -- define to use common CF RTC driver +CFG_MCFRTC_BASE -- provide base address for RTC in immap.h +CFG_RTC_OSCILLATOR -- define RTC clock frequency +RTC_DEBUG -- define to show RTC debug message +CONFIG_CMD_DATE -- enable to use date feature in u-boot + +CONFIG_MCFFEC -- define to use common CF FEC driver +CONFIG_NET_MULTI -- define to use multi FEC in u-boot +CONFIG_MII -- enable to use MII driver +CONFIG_CF_DOMII -- enable to use MII feature in cmd_mii.c +CFG_DISCOVER_PHY -- enable PHY discovery +CFG_RX_ETH_BUFFER -- Set FEC Receive buffer +CFG_FAULT_ECHO_LINK_DOWN-- +CFG_FEC0_PINMUX -- Set FEC0 Pin configuration +CFG_FEC0_MIIBASE -- Set FEC0 MII base register +MCFFEC_TOUT_LOOP -- set FEC timeout loop + +CONFIG_MCFTMR -- define to use DMA timer +CONFIG_MCFPIT -- define to use PIT timer + +CONFIG_FSL_I2C -- define to use FSL common I2C driver +CONFIG_HARD_I2C -- define for I2C hardware support +CONFIG_SOFT_I2C -- define for I2C bit-banged +CFG_I2C_SPEED -- define for I2C speed +CFG_I2C_SLAVE -- define for I2C slave address +CFG_I2C_OFFSET -- define for I2C base address offset +CFG_IMMR -- define for MBAR offset + +CFG_MBAR -- define MBAR offset + +CONFIG_MONITOR_IS_IN_RAM -- Not support + +CFG_INIT_RAM_ADDR -- defines the base address of the MCF5373 internal SRAM + +CFG_CSn_BASE -- defines the Chip Select Base register +CFG_CSn_MASK -- defines the Chip Select Mask register +CFG_CSn_CTRL -- defines the Chip Select Control register + +CFG_SDRAM_BASE -- defines the DRAM Base + +2. MEMORY MAP UNDER U-BOOT AND LINUX KERNEL +=========================================== +2.1. System memory map: + Flash: 0x00000000-0x3FFFFFFF (1024MB) + DDR: 0x40000000-0x7FFFFFFF (1024MB) + SRAM: 0x80000000-0x8FFFFFFF (256MB) + IP: 0xF0000000-0xFFFFFFFF (256MB) + +2.2. For the initial bringup, we adopted a consistent memory scheme between u-boot and + linux kernel, you can customize it based on your system requirements: + Flash0: 0x00000000-0x00FFFFFF (16MB) + + DDR: 0x40000000-0x4FFFFFFF (256MB) + SRAM: 0x80000000-0x80007FFF (32KB) + IP: 0xFC000000-0xFC0FFFFF (64KB) + +3. COMPILATION +============== +3.1 To create U-Boot the gcc-4.1-xx compiler set (ColdFire ELF or +uClinux version) from codesourcery.com was used. Download it from: +http://www.codesourcery.com/gnu_toolchains/coldfire/download.html + +3.2 Compilation + export CROSS_COMPILE=cross-compile-prefix + cd u-boot-1.x.x + make distclean + make M5373EVB_config + make + +4. SCREEN DUMP +============== +4.1 M5373EVB Development board + (NOTE: May not show exactly the same) + +U-Boot 1.3.0 (Nov 8 2007 - 12:44:08) + +CPU: Freescale MCF5373 (Mask:65 Version:1) + CPU CLK 240 Mhz BUS CLK 80 Mhz +Board: Freescale FireEngine 5373 EVB +I2C: ready +DRAM: 32 MB +FLASH: 2 MB +In: serial +Out: serial +Err: serial +NAND: 16 MiB +Net: FEC0 +-> print +bootdelay=1 +baudrate=115200 +ethaddr=00:e0:0c:bc:e5:60 +hostname=M5373EVB +netdev=eth0 +loadaddr=40010000 +load=tftp ${loadaddr) ${u-boot} +upd=run load; run prog +prog=prot off 0 2ffff;era 0 2ffff;cp.b ${loadaddr} 0 ${filesize};save +ethact=FEC0 +u-boot=u-boot.bin +gatewayip=192.168.1.1 +netmask=255.255.255.0 +ipaddr=192.168.1.3 +serverip=192.168.1.2 +stdin=serial +stdout=serial +stderr=serial +mem=261632k + +Environment size: 401/8188 bytes +-> bdinfo +memstart = 0x40000000 +memsize = 0x02000000 +flashstart = 0x00000000 +flashsize = 0x00200000 +flashoffset = 0x00000000 +sramstart = 0x80000000 +sramsize = 0x00008000 +mbar = 0xFC000000 +busfreq = 80 MHz +ethaddr = 00:E0:0C:BC:E5:60 +ip_addr = 192.168.1.3 +baudrate = 115200 bps +-> +-> help +? - alias for 'help' +autoscr - run script from memory +base - print or set address offset +bdinfo - print Board Info structure +boot - boot default, i.e., run 'bootcmd' +bootd - boot default, i.e., run 'bootcmd' +bootelf - Boot from an ELF image in memory +bootm - boot application image from memory +bootp - boot image via network using BootP/TFTP protocol +bootvx - Boot vxWorks from an ELF image +cmp - memory compare +coninfo - print console devices and information +cp - memory copy +crc32 - checksum calculation +date - get/set/reset date & time +dcache - enable or disable data cache +echo - echo args to console +erase - erase FLASH memory +flinfo - print FLASH memory information +go - start application at address 'addr' +help - print online help +icache - enable or disable instruction cache +icrc32 - checksum calculation +iloop - infinite loop on address range +imd - i2c memory display +iminfo - print header information for application image +imls - list all images found in flash +imm - i2c memory modify (auto-incrementing) +imw - memory write (fill) +inm - memory modify (constant address) +iprobe - probe to discover valid I2C chip addresses +itest - return true/false on integer compare +loadb - load binary file over serial line (kermit mode) +loads - load S-Record file over serial line +loady - load binary file over serial line (ymodem mode) +loop - infinite loop on address range +ls - list files in a directory (default /) +md - memory display +mii - MII utility commands +mm - memory modify (auto-incrementing) +mtest - simple RAM test +mw - memory write (fill) +nand - NAND sub-system +nboot - boot from NAND device +nfs - boot image via network using NFS protocol +nm - memory modify (constant address) +ping - send ICMP ECHO_REQUEST to network host +printenv- print environment variables +protect - enable or disable FLASH write protection +rarpboot- boot image via network using RARP/TFTP protocol +reset - Perform RESET of the CPU +run - run commands in an environment variable +saveenv - save environment variables to persistent storage +setenv - set environment variables +sleep - delay execution for some time +tftpboot- boot image via network using TFTP protocol +version - print monitor version +-> tftp 0x40800000 uImage +Using FEC0 device +TFTP from server 192.168.1.3; our IP address is 192.168.1.3 Filename 'uImage'. +Load address: 0x40800000 +Loading: ################################################################# + ################################################################# + ########## +done +Bytes transferred = 2053270 (1f5496 hex) +-> bootm 0x40800000 +## Booting image at 40800000 ... + Image Name: Linux Kernel Image + Created: 2007-11-07 20:33:08 UTC + Image Type: M68K Linux Kernel Image (gzip compressed) + Data Size: 2053206 Bytes = 2 MB + Load Address: 40020000 + Entry Point: 40020000 + Verifying Checksum ... OK + Uncompressing Kernel Image ... OK +Linux version 2.6.22-uc1 (mattw@loa) (gcc version 4.2.1 (Sourcery G++ Lite 4.2-7 + + +uClinux/COLDFIRE(m537x) +COLDFIRE port done by Greg Ungerer, gerg@snapgear.com Flat model support (C) 1998,1999 Kenneth Albanowski, D. Jeff Dionne Built 1 zonelists. Total pages: 8128 Kernel command line: rootfstype=romfs PID hash table entries: 128 (order: 7, 512 bytes) Dentry cache hash table entries: 4096 (order: 2, 16384 bytes) Inode-cache hash table entries: 2048 (order: 1, 8192 bytes) Memory available: 28092k/32768k RAM, (1788k kernel code, 244k data) Mount-cache hash table entries: 512 +NET: Registered protocol family 16 +USB-MCF537x: (HOST module) EHCI device is registered +USB-MCF537x: (OTG module) EHCI device is registered +USB-MCF537x: (OTG module) UDC device is registered +usbcore: registered new interface driver usbfs +usbcore: registered new interface driver hub +usbcore: registered new device driver usb +NET: Registered protocol family 2 +IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 1024 (order: 1, 8192 bytes) TCP bind hash table entries: 1024 (order: 0, 4096 bytes) +TCP: Hash tables configured (established 1024 bind 1024) TCP reno registered +JFFS2 version 2.2. (NAND) © 2001-2006 Red Hat, Inc. +io scheduler noop registered +io scheduler cfq registered (default) +ColdFire internal UART serial driver version 1.00 ttyS0 at 0xfc060000 (irq = 90) is a builtin ColdFire UART +ttyS1 at 0xfc064000 (irq = 91) is a builtin ColdFire UART +ttyS2 at 0xfc068000 (irq = 92) is a builtin ColdFire UART RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize +loop: module loaded +nbd: registered device at major 43 +usbcore: registered new interface driver ub FEC ENET Version 0.2 +fec: PHY @ 0x1, ID 0x20005c90 -- DP83848 +eth0: ethernet 00:e0:0c:bc:e5:60 +uclinux[mtd]: RAM probe address=0x4021c22c size=0x22b000 Creating 1 MTD partitions on "RAM": +0x00000000-0x0022b000 : "ROMfs" +uclinux[mtd]: set ROMfs to be root filesystem NAND device: Manufacturer ID: 0x20, Chip ID: 0x73 (ST Micro NAND 16MiB 3,3V 8-b) Scanning device for bad blocks Creating 1 MTD partitions on "NAND 16MiB 3,3V 8-bit": +0x00000000-0x01000000 : "M53xx flash partition 1" +QSPI: spi->max_speed_hz 300000 +QSPI: Baud set to 255 +SPI: Coldfire master initialized +M537x - Disable UART1 when using Audio +udc: Freescale MCF53xx UDC driver version 27 October 2006 init +udc: MCF53xx USB Device is found. ID=0x5 Rev=0x41 i2c /dev entries driver +usbcore: registered new interface driver usbhid +drivers/hid/usbhid/hid-core.c: v2.6:USB HID core driver TCP cubic registered +NET: Registered protocol family 1 +NET: Registered protocol family 17 +VFS: Mounted root (romfs filesystem) readonly. +Freeing unused kernel memory: 64k freed (0x401f5000 - 0x40204000) init started: BusyBox v1.00 (2007.11.07-19:57+0000) multi-call binary?Setting e Mounting filesystems +mount: Mounting devpts on /dev/pts failed: No such device +mount: Mounting usbfs on /proc/bus/usb failed: No such file or directory Starting syslogd and klogd Setting up networking on loopback device: +Setting up networking on eth0: +info, udhcpc (v0.9.9-pre) started +eth0: config: auto-negotiation on, 100FDX, 100HDX, 10FDX, 10HDX. +debug, Sending discover... +debug, Sending discover... +debug, Sending select for 172.27.0.130... +info, Lease of 172.27.0.130 obtained, lease time 43200 deleting routers +route: SIOC[ADD|DEL]RT: No such process +adding dns 172.27.0.1 +Starting the boa webserver: +Setting time from ntp server: ntp.cs.strath.ac.uk +ntp.cs.strath.ac.uk: Unknown host + + +BusyBox v1.00 (2007.11.07-19:57+0000) Built-in shell (msh) Enter 'help' for a list of built-in commands. + +# diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index 912753d22..852d94158 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -169,7 +169,7 @@ #endif #endif /* CONFIG_M5282 */ -#ifdef CONFIG_M5329 +#if defined(CONFIG_M5329) || defined(CONFIG_M5373) #include #include @@ -197,7 +197,7 @@ #define CFG_INTR_BASE (MMAP_INTC0) #define CFG_NUM_IRQS (128) -#endif /* CONFIG_M5329 */ +#endif /* CONFIG_M5329 && CONFIG_M5373 */ #ifdef CONFIG_M54455 #include diff --git a/include/asm-m68k/immap_5329.h b/include/asm-m68k/immap_5329.h index 7ff0b9317..7678406e5 100644 --- a/include/asm-m68k/immap_5329.h +++ b/include/asm-m68k/immap_5329.h @@ -378,91 +378,133 @@ typedef struct rcm { /* GPIO port registers */ typedef struct gpio_ctrl { /* Port Output Data Registers */ +#ifdef CONFIG_M5329 u8 podr_fech; /* 0x00 */ u8 podr_fecl; /* 0x01 */ +#else + u16 res00; /* 0x00 - 0x01 */ +#endif u8 podr_ssi; /* 0x02 */ u8 podr_busctl; /* 0x03 */ u8 podr_be; /* 0x04 */ u8 podr_cs; /* 0x05 */ u8 podr_pwm; /* 0x06 */ u8 podr_feci2c; /* 0x07 */ - u8 res1; /* 0x08 */ + u8 res08; /* 0x08 */ u8 podr_uart; /* 0x09 */ u8 podr_qspi; /* 0x0A */ u8 podr_timer; /* 0x0B */ - u8 res2; /* 0x0C */ +#ifdef CONFIG_M5329 + u8 res0C; /* 0x0C */ u8 podr_lcddatah; /* 0x0D */ u8 podr_lcddatam; /* 0x0E */ u8 podr_lcddatal; /* 0x0F */ u8 podr_lcdctlh; /* 0x10 */ u8 podr_lcdctll; /* 0x11 */ +#else + u16 res0C; /* 0x0C - 0x0D */ + u8 podr_fech; /* 0x0E */ + u8 podr_fecl; /* 0x0F */ + u16 res10[3]; /* 0x10 - 0x15 */ +#endif /* Port Data Direction Registers */ - u16 res3; /* 0x12 - 0x13 */ +#ifdef CONFIG_M5329 + u16 res12; /* 0x12 - 0x13 */ u8 pddr_fech; /* 0x14 */ u8 pddr_fecl; /* 0x15 */ +#endif u8 pddr_ssi; /* 0x16 */ u8 pddr_busctl; /* 0x17 */ u8 pddr_be; /* 0x18 */ u8 pddr_cs; /* 0x19 */ u8 pddr_pwm; /* 0x1A */ u8 pddr_feci2c; /* 0x1B */ - u8 res4; /* 0x1C */ + u8 res1C; /* 0x1C */ u8 pddr_uart; /* 0x1D */ u8 pddr_qspi; /* 0x1E */ u8 pddr_timer; /* 0x1F */ - u8 res5; /* 0x20 */ +#ifdef CONFIG_M5329 + u8 res20; /* 0x20 */ u8 pddr_lcddatah; /* 0x21 */ u8 pddr_lcddatam; /* 0x22 */ u8 pddr_lcddatal; /* 0x23 */ u8 pddr_lcdctlh; /* 0x24 */ u8 pddr_lcdctll; /* 0x25 */ - u16 res6; /* 0x26 - 0x27 */ + u16 res26; /* 0x26 - 0x27 */ +#else + u16 res20; /* 0x20 - 0x21 */ + u8 pddr_fech; /* 0x22 */ + u8 pddr_fecl; /* 0x23 */ + u16 res24[3]; /* 0x24 - 0x29 */ +#endif /* Port Data Direction Registers */ +#ifdef CONFIG_M5329 u8 ppd_fech; /* 0x28 */ u8 ppd_fecl; /* 0x29 */ +#endif u8 ppd_ssi; /* 0x2A */ u8 ppd_busctl; /* 0x2B */ u8 ppd_be; /* 0x2C */ u8 ppd_cs; /* 0x2D */ u8 ppd_pwm; /* 0x2E */ u8 ppd_feci2c; /* 0x2F */ - u8 res7; /* 0x30 */ + u8 res30; /* 0x30 */ u8 ppd_uart; /* 0x31 */ u8 ppd_qspi; /* 0x32 */ u8 ppd_timer; /* 0x33 */ - u8 res8; /* 0x34 */ +#ifdef CONFIG_M5329 + u8 res34; /* 0x34 */ u8 ppd_lcddatah; /* 0x35 */ u8 ppd_lcddatam; /* 0x36 */ u8 ppd_lcddatal; /* 0x37 */ u8 ppd_lcdctlh; /* 0x38 */ u8 ppd_lcdctll; /* 0x39 */ - u16 res9; /* 0x3A - 0x3B */ + u16 res3A; /* 0x3A - 0x3B */ +#else + u16 res34; /* 0x34 - 0x35 */ + u8 ppd_fech; /* 0x36 */ + u8 ppd_fecl; /* 0x37 */ + u16 res38[3]; /* 0x38 - 0x3D */ +#endif /* Port Clear Output Data Registers */ - u8 pclrr_fech; /* 0x3C */ - u8 pclrr_fecl; /* 0x3D */ +#ifdef CONFIG_M5329 + u8 res3C; /* 0x3C */ + u8 pclrr_fech; /* 0x3D */ + u8 pclrr_fecl; /* 0x3E */ +#else u8 pclrr_ssi; /* 0x3E */ +#endif u8 pclrr_busctl; /* 0x3F */ u8 pclrr_be; /* 0x40 */ u8 pclrr_cs; /* 0x41 */ u8 pclrr_pwm; /* 0x42 */ u8 pclrr_feci2c; /* 0x43 */ - u8 res10; /* 0x44 */ + u8 res44; /* 0x44 */ u8 pclrr_uart; /* 0x45 */ u8 pclrr_qspi; /* 0x46 */ u8 pclrr_timer; /* 0x47 */ - u8 res11; /* 0x48 */ - u8 pclrr_lcddatah; /* 0x49 */ - u8 pclrr_lcddatam; /* 0x4A */ - u8 pclrr_lcddatal; /* 0x4B */ +#ifdef CONFIG_M5329 + u8 pclrr_lcddatah; /* 0x48 */ + u8 pclrr_lcddatam; /* 0x49 */ + u8 pclrr_lcddatal; /* 0x4A */ + u8 pclrr_ssi; /* 0x4B */ u8 pclrr_lcdctlh; /* 0x4C */ u8 pclrr_lcdctll; /* 0x4D */ - u16 res12; /* 0x4E - 0x4F */ + u16 res4E; /* 0x4E - 0x4F */ +#else + u16 res48; /* 0x48 - 0x49 */ + u8 pclrr_fech; /* 0x4A */ + u8 pclrr_fecl; /* 0x4B */ + u8 res4C[5]; /* 0x4C - 0x50 */ +#endif /* Pin Assignment Registers */ +#ifdef CONFIG_M5329 u8 par_fec; /* 0x50 */ +#endif u8 par_pwm; /* 0x51 */ u8 par_busctl; /* 0x52 */ u8 par_feci2c; /* 0x53 */ @@ -472,15 +514,20 @@ typedef struct gpio_ctrl { u16 par_uart; /* 0x58 */ u16 par_qspi; /* 0x5A */ u8 par_timer; /* 0x5C */ +#ifdef CONFIG_M5329 u8 par_lcddata; /* 0x5D */ u16 par_lcdctl; /* 0x5E */ +#else + u8 par_fec; /* 0x5D */ + u16 res5E; /* 0x5E - 0x5F */ +#endif u16 par_irq; /* 0x60 */ - u16 res16; /* 0x62 - 0x63 */ + u16 res62; /* 0x62 - 0x63 */ /* Mode Select Control Registers */ u8 mscr_flexbus; /* 0x64 */ u8 mscr_sdram; /* 0x65 */ - u16 res17; /* 0x66 - 0x67 */ + u16 res66; /* 0x66 - 0x67 */ /* Drive Strength Control Registers */ u8 dscr_i2c; /* 0x68 */ @@ -490,7 +537,11 @@ typedef struct gpio_ctrl { u8 dscr_qspi; /* 0x6C */ u8 dscr_timer; /* 0x6D */ u8 dscr_ssi; /* 0x6E */ +#ifdef CONFIG_M5329 u8 dscr_lcd; /* 0x6F */ +#else + u8 res6F; /* 0x6F */ +#endif u8 dscr_debug; /* 0x70 */ u8 dscr_clkrst; /* 0x71 */ u8 dscr_irq; /* 0x72 */ diff --git a/include/asm-m68k/m5329.h b/include/asm-m68k/m5329.h index 8316fcf20..c1669dcb1 100644 --- a/include/asm-m68k/m5329.h +++ b/include/asm-m68k/m5329.h @@ -1118,6 +1118,7 @@ #define GPIO_PCLRR_LCDCTLL7 (0x80) /* Bit definitions and macros for GPIO_PAR_FEC */ +#ifdef CONFIG_M5329 #define GPIO_PAR_FEC_MII(x) (((x)&0x03)<<0) #define GPIO_PAR_FEC_7W(x) (((x)&0x03)<<2) #define GPIO_PAR_FEC_7W_GPIO (0x00) @@ -1126,6 +1127,10 @@ #define GPIO_PAR_FEC_MII_GPIO (0x00) #define GPIO_PAR_FEC_MII_UART (0x01) #define GPIO_PAR_FEC_MII_FEC (0x03) +#else +#define GPIO_PAR_FEC_7W_FEC (0x08) +#define GPIO_PAR_FEC_MII_FEC (0x02) +#endif /* Bit definitions and macros for GPIO_PAR_PWM */ #define GPIO_PAR_PWM1(x) (((x)&0x03)<<0) diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h new file mode 100644 index 000000000..6bfffa108 --- /dev/null +++ b/include/configs/M5373EVB.h @@ -0,0 +1,267 @@ +/* + * Configuation settings for the Freescale MCF5373 FireEngine board. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef _M5373EVB_H +#define _M5373EVB_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MCF532x /* define processor family */ +#define CONFIG_M5373 /* define processor type */ + +#undef DEBUG + +#define CONFIG_MCFUART +#define CFG_UART_PORT (0) +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_WATCHDOG +#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ + +/* Command line configuration */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + +#ifdef NANDFLASH_SIZE +# define CONFIG_CMD_NAND +#endif + +#define CFG_UNIFY_CACHE + +#define CONFIG_MCFFEC +#ifdef CONFIG_MCFFEC +# define CONFIG_NET_MULTI 1 +# define CONFIG_MII 1 +# define CFG_DISCOVER_PHY +# define CFG_RX_ETH_BUFFER 8 +# define CFG_FAULT_ECHO_LINK_DOWN + +# define CFG_FEC0_PINMUX 0 +# define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE +# define MCFFEC_TOUT_LOOP 50000 +/* If CFG_DISCOVER_PHY is not defined - hardcoded */ +# ifndef CFG_DISCOVER_PHY +# define FECDUPLEX FULL +# define FECSPEED _100BASET +# else +# ifndef CFG_FAULT_ECHO_LINK_DOWN +# define CFG_FAULT_ECHO_LINK_DOWN +# endif +# endif /* CFG_DISCOVER_PHY */ +#endif + +#define CONFIG_MCFRTC +#undef RTC_DEBUG + +/* Timer */ +#define CONFIG_MCFTMR +#undef CONFIG_MCFPIT + +/* I2C */ +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C /* I2C with hw support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 80000 +#define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_OFFSET 0x58000 +#define CFG_IMMR CFG_MBAR + +#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ +#define CONFIG_UDP_CHECKSUM + +#ifdef CONFIG_MCFFEC +# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 +# define CONFIG_IPADDR 192.162.1.2 +# define CONFIG_NETMASK 255.255.255.0 +# define CONFIG_SERVERIP 192.162.1.1 +# define CONFIG_GATEWAYIP 192.162.1.1 +# define CONFIG_OVERWRITE_ETHADDR_ONCE +#endif /* FEC_ENET */ + +#define CONFIG_HOSTNAME M5373EVB +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "loadaddr=" MK_STR(CFG_LOAD_ADDR) "\0" \ + "u-boot=u-boot.bin\0" \ + "load=tftp ${loadaddr) ${u-boot}\0" \ + "upd=run load; run prog\0" \ + "prog=prot off 0 2ffff;" \ + "era 0 2ffff;" \ + "cp.b ${loadaddr} 0 ${filesize};" \ + "save\0" \ + "" + +#define CONFIG_PRAM 512 /* 512 KB */ +#define CFG_PROMPT "-> " +#define CFG_LONGHELP /* undef to save memory */ + +#ifdef CONFIG_CMD_KGDB +# define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +# define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x40010000 + +#define CFG_HZ 1000 +#define CFG_CLK 80000000 +#define CFG_CPU_CLK CFG_CLK * 3 + +#define CFG_MBAR 0xFC000000 + +#define CFG_LATCH_ADDR (CFG_CS1_BASE + 0x80000) + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x80000000 +#define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ +#define CFG_INIT_RAM_CTRL 0x221 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 0x10) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x40000000 +#define CFG_SDRAM_SIZE 32 /* SDRAM size in MB */ +#define CFG_SDRAM_CFG1 0x53722730 +#define CFG_SDRAM_CFG2 0x56670000 +#define CFG_SDRAM_CTRL 0xE1092000 +#define CFG_SDRAM_EMOD 0x40010000 +#define CFG_SDRAM_MODE 0x018D0000 + +#define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 +#define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) + +#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_BOOTPARAMS_LEN 64*1024 +#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_FLASH_CFI +#ifdef CFG_FLASH_CFI +# define CFG_FLASH_CFI_DRIVER 1 +# define CFG_FLASH_SIZE 0x800000 /* Max size that the board might have */ +# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ +# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ +#endif + +#ifdef NANDFLASH_SIZE +# define CFG_MAX_NAND_DEVICE 1 +# define CFG_NAND_BASE CFG_CS2_BASE +# define CFG_NAND_SIZE 1 +# define CFG_NAND_BASE_LIST { CFG_NAND_BASE } +# define NAND_MAX_CHIPS 1 +# define NAND_ALLOW_ERASE_ALL 1 +# define CONFIG_JFFS2_NAND 1 +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_PART_SIZE (CFG_CS2_MASK & ~1) +# define CONFIG_JFFS2_PART_OFFSET 0x00000000 +#endif + +#define CFG_FLASH_BASE CFG_CS0_BASE + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#define CFG_ENV_OFFSET 0x4000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_IS_EMBEDDED 1 + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Chipselect bank definitions + */ +/* + * CS0 - NOR Flash 1, 2, 4, or 8MB + * CS1 - CompactFlash and registers + * CS2 - NAND Flash 16, 32, or 64MB + * CS3 - Available + * CS4 - Available + * CS5 - Available + */ +#define CFG_CS0_BASE 0 +#define CFG_CS0_MASK 0x007f0001 +#define CFG_CS0_CTRL 0x00001fa0 + +#define CFG_CS1_BASE 0x10000000 +#define CFG_CS1_MASK 0x001f0001 +#define CFG_CS1_CTRL 0x002A3780 + +#ifdef NANDFLASH_SIZE +#define CFG_CS2_BASE 0x20000000 +#define CFG_CS2_MASK ((NANDFLASH_SIZE << 20) | 1) +#define CFG_CS2_CTRL 0x00001f60 +#endif + +#endif /* _M5373EVB_H */ -- cgit v1.2.3 From c87581027994c148131b2f11aa75501f782ec19a Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Mon, 14 Jan 2008 17:46:19 -0600 Subject: ColdFire: Add MCF5227x cpu and MCF52277EVB support-2 Signed-off-by: TsiChungLiew Signed-off by: John Rigby --- cpu/mcf5227x/Makefile | 48 ++++++ cpu/mcf5227x/config.mk | 31 ++++ cpu/mcf5227x/cpu.c | 75 +++++++++ cpu/mcf5227x/cpu_init.c | 146 +++++++++++++++++ cpu/mcf5227x/interrupts.c | 52 ++++++ cpu/mcf5227x/speed.c | 120 ++++++++++++++ cpu/mcf5227x/start.S | 356 +++++++++++++++++++++++++++++++++++++++++ include/asm-m68k/immap_5227x.h | 343 +++++++++++++++++++++++++++++++++++++++ 8 files changed, 1171 insertions(+) create mode 100644 cpu/mcf5227x/Makefile create mode 100644 cpu/mcf5227x/config.mk create mode 100644 cpu/mcf5227x/cpu.c create mode 100644 cpu/mcf5227x/cpu_init.c create mode 100644 cpu/mcf5227x/interrupts.c create mode 100644 cpu/mcf5227x/speed.c create mode 100644 cpu/mcf5227x/start.S create mode 100644 include/asm-m68k/immap_5227x.h (limited to 'cpu') diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile new file mode 100644 index 000000000..d0e9b4550 --- /dev/null +++ b/cpu/mcf5227x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = start.o +COBJS = cpu.o speed.o cpu_init.o interrupts.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf5227x/config.mk b/cpu/mcf5227x/config.mk new file mode 100644 index 000000000..8d60fd66b --- /dev/null +++ b/cpu/mcf5227x/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +PLATFORM_CPPFLAGS += -mcpu=5208 -fPIC +else +PLATFORM_CPPFLAGS += -m5307 -fPIC +endif diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c new file mode 100644 index 000000000..5792a1c08 --- /dev/null +++ b/cpu/mcf5227x/cpu.c @@ -0,0 +1,75 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM); + udelay(1000); + rcm->rcr |= RCM_RCR_SOFTRST; + + /* we don't return! */ + return 0; +}; + +int checkcpu(void) +{ + volatile ccm_t *ccm = (ccm_t *) MMAP_CCM; + u16 msk; + u16 id = 0; + u8 ver; + + puts("CPU: "); + msk = (ccm->cir >> 6); + ver = (ccm->cir & 0x003f); + switch (msk) { + case 0x6c: + id = 52277; + break; + } + + if (id) { + printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk, + ver); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000), + (int)(gd->flb_clk / 1000000)); + printf(" INP CLK %d Mhz VCO CLK %d Mhz\n", + (int)(gd->inp_clk / 1000000), + (int)(gd->vco_clk / 1000000)); + } + + return 0; +} diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c new file mode 100644 index 000000000..71b053d4d --- /dev/null +++ b/cpu/mcf5227x/cpu_init.c @@ -0,0 +1,146 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Workaround, must place before fbcs */ + pll->psr = 0x12; + + scm1->mpr = 0x77777777; + scm1->pacra = 0; + scm1->pacrb = 0; + scm1->pacrc = 0; + scm1->pacrd = 0; + scm1->pacre = 0; + scm1->pacrf = 0; + scm1->pacrg = 0; + scm1->pacri = 0; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#ifdef CONFIG_MCFTMR + volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); + volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; + u32 oscillator = CFG_RTC_OSCILLATOR; + + rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; + rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; +#endif + + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_uart &= + (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); + break; + case 1: + gpio->par_uart &= + (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); + gpio->par_uart |= + (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); + break; + case 2: + gpio->par_dspi &= + (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); + gpio->par_dspi = + (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); + break; + } +} diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c new file mode 100644 index 000000000..9572a7bc3 --- /dev/null +++ b/cpu/mcf5227x/interrupts.c @@ -0,0 +1,52 @@ +/* + * + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + return 0; +} + +#if defined(CONFIG_MCFTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c new file mode 100644 index 000000000..78c946f25 --- /dev/null +++ b/cpu/mcf5227x/speed.c @@ -0,0 +1,120 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Low Power Divider specifications + */ +#define CLOCK_LPD_MIN (1 << 0) /* Divider (decoded) */ +#define CLOCK_LPD_MAX (1 << 15) /* Divider (decoded) */ + +#define CLOCK_PLL_FVCO_MAX 540000000 +#define CLOCK_PLL_FVCO_MIN 300000000 + +#define CLOCK_PLL_FSYS_MAX 266666666 +#define CLOCK_PLL_FSYS_MIN 100000000 +#define MHZ 1000000 + +void clock_enter_limp(int lpdiv) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + int i, j; + + /* Check bounds of divider */ + if (lpdiv < CLOCK_LPD_MIN) + lpdiv = CLOCK_LPD_MIN; + if (lpdiv > CLOCK_LPD_MAX) + lpdiv = CLOCK_LPD_MAX; + + /* Round divider down to nearest power of two */ + for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ; + + /* Apply the divider to the system clock */ + ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i); + + /* Enable Limp Mode */ + ccm->misccr |= CCM_MISCCR_LIMP; +} + +/* + * brief Exit Limp mode + * warning The PLL should be set and locked prior to exiting Limp mode + */ +void clock_exit_limp(void) +{ + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + + /* Exit Limp mode */ + ccm->misccr &= ~CCM_MISCCR_LIMP; + + /* Wait for the PLL to lock */ + while (!(pll->psr & PLL_PSR_LOCK)) ; +} + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + + volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM; + volatile pll_t *pll = (volatile pll_t *)MMAP_PLL; + int vco, temp, pcrvalue, pfdr; + u8 bootmode; + + bootmode = (ccm->ccr & 0x000C) >> 2; + + pcrvalue = pll->pcr & 0xFF0F0FFF; + pfdr = pcrvalue >> 24; + + if (pfdr != 0x1E) { + /* serial mode */ + } else { + /* Normal Mode */ + vco = pfdr * CFG_INPUT_CLKSRC; + gd->vco_clk = vco; + } + + if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) { + /* Limp mode */ + } else { + gd->inp_clk = CFG_INPUT_CLKSRC; /* Input clock */ + + temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1; + gd->cpu_clk = vco / temp; /* cpu clock */ + + temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1; + gd->flb_clk = vco / temp; /* flexbus clock */ + gd->bus_clk = gd->flb_clk; + } + + return (0); +} diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S new file mode 100644 index 000000000..0e2db1261 --- /dev/null +++ b/cpu/mcf5227x/start.S @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l #(CACR_STATUS), %a3 /* CACR */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* invalidate and disable cache */ + move.l #0x01000000, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + /* set stackpointer to end of internal ram to get some stackspace for + the first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #0x01200000, %d0 /* Invalid cache */ + movec %d0, %CACR + + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + movec %d0, %ACR0 + + move.l #0x81600610, %d0 /* Enable cache */ + movec %d0, %CACR + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x01F00000, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + clr.l %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl icache_invalid +icache_invalid: + move.l #0x80600610, %d0 /* Invalidate icache */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_enable +dcache_enable: + move.l #0x01200000, %d0 /* Invalid cache */ + movec %d0, %CACR + + move.l #0x81300610, %d0 + movec %d0, %CACR + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #0x81600610, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Invalidate icache */ + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_invalid +dcache_invalid: + move.l #0x81100610, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable and invalidate cache */ + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h new file mode 100644 index 000000000..1d1e6f1b0 --- /dev/null +++ b/include/asm-m68k/immap_5227x.h @@ -0,0 +1,343 @@ +/* + * MCF5227x Internal Memory Map + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5227X__ +#define __IMMAP_5227X__ + +/* Module Base Addresses */ +#define MMAP_SCM1 (CFG_MBAR + 0x00000000) +#define MMAP_XBS (CFG_MBAR + 0x00004000) +#define MMAP_FBCS (CFG_MBAR + 0x00008000) +#define MMAP_CAN (CFG_MBAR + 0x00020000) +#define MMAP_RTC (CFG_MBAR + 0x0003C000) +#define MMAP_SCM2 (CFG_MBAR + 0x00040010) +#define MMAP_SCM3 (CFG_MBAR + 0x00040070) +#define MMAP_EDMA (CFG_MBAR + 0x00044000) +#define MMAP_INTC0 (CFG_MBAR + 0x00048000) +#define MMAP_INTC1 (CFG_MBAR + 0x0004C000) +#define MMAP_IACK (CFG_MBAR + 0x00054000) +#define MMAP_I2C (CFG_MBAR + 0x00058000) +#define MMAP_DSPI (CFG_MBAR + 0x0005C000) +#define MMAP_UART0 (CFG_MBAR + 0x00060000) +#define MMAP_UART1 (CFG_MBAR + 0x00064000) +#define MMAP_UART2 (CFG_MBAR + 0x00068000) +#define MMAP_DTMR0 (CFG_MBAR + 0x00070000) +#define MMAP_DTMR1 (CFG_MBAR + 0x00074000) +#define MMAP_DTMR2 (CFG_MBAR + 0x00078000) +#define MMAP_DTMR3 (CFG_MBAR + 0x0007C000) +#define MMAP_PIT0 (CFG_MBAR + 0x00080000) +#define MMAP_PIT1 (CFG_MBAR + 0x00084000) +#define MMAP_PWM (CFG_MBAR + 0x00090000) +#define MMAP_EPORT (CFG_MBAR + 0x00094000) +#define MMAP_RCM (CFG_MBAR + 0x000A0000) +#define MMAP_CCM (CFG_MBAR + 0x000A0004) +#define MMAP_GPIO (CFG_MBAR + 0x000A4000) +#define MMAP_ADC (CFG_MBAR + 0x000A8000) +#define MMAP_LCD (CFG_MBAR + 0x000AC000) +#define MMAP_LCD_BGLUT (CFG_MBAR + 0x000AC800) +#define MMAP_LCD_GWLUT (CFG_MBAR + 0x000ACC00) +#define MMAP_USBHW (CFG_MBAR + 0x000B0000) +#define MMAP_USBCAPS (CFG_MBAR + 0x000B0100) +#define MMAP_USBEHCI (CFG_MBAR + 0x000B0140) +#define MMAP_USBOTG (CFG_MBAR + 0x000B01A0) +#define MMAP_SDRAM (CFG_MBAR + 0x000B8000) +#define MMAP_SSI (CFG_MBAR + 0x000BC000) +#define MMAP_PLL (CFG_MBAR + 0x000C0000) + +#include +#include +#include +#include +#include +#include + +/* Interrupt Controller (INTC) */ +typedef struct int0_ctrl { + u32 iprh0; /* 0x00 Pending Register High */ + u32 iprl0; /* 0x04 Pending Register Low */ + u32 imrh0; /* 0x08 Mask Register High */ + u32 imrl0; /* 0x0C Mask Register Low */ + u32 frch0; /* 0x10 Force Register High */ + u32 frcl0; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 - 0x19 */ + u16 icfg0; /* 0x1A Configuration Register */ + u8 simr0; /* 0x1C Set Interrupt Mask */ + u8 cimr0; /* 0x1D Clear Interrupt Mask */ + u8 clmask0; /* 0x1E Current Level Mask */ + u8 slmask; /* 0x1F Saved Level Mask */ + u32 res2[8]; /* 0x20 - 0x3F */ + u8 icr0[64]; /* 0x40 - 0x7F Control registers */ + u32 res3[24]; /* 0x80 - 0xDF */ + u8 swiack0; /* 0xE0 Software Interrupt ack */ + u8 res4[3]; /* 0xE1 - 0xE3 */ + u8 Lniack0_1; /* 0xE4 Level n interrupt ack */ + u8 res5[3]; /* 0xE5 - 0xE7 */ + u8 Lniack0_2; /* 0xE8 Level n interrupt ack */ + u8 res6[3]; /* 0xE9 - 0xEB */ + u8 Lniack0_3; /* 0xEC Level n interrupt ack */ + u8 res7[3]; /* 0xED - 0xEF */ + u8 Lniack0_4; /* 0xF0 Level n interrupt ack */ + u8 res8[3]; /* 0xF1 - 0xF3 */ + u8 Lniack0_5; /* 0xF4 Level n interrupt ack */ + u8 res9[3]; /* 0xF5 - 0xF7 */ + u8 Lniack0_6; /* 0xF8 Level n interrupt ack */ + u8 resa[3]; /* 0xF9 - 0xFB */ + u8 Lniack0_7; /* 0xFC Level n interrupt ack */ + u8 resb[3]; /* 0xFD - 0xFF */ +} int0_t; + +typedef struct int1_ctrl { + /* Interrupt Controller 1 */ + u32 iprh1; /* 0x00 Pending Register High */ + u32 iprl1; /* 0x04 Pending Register Low */ + u32 imrh1; /* 0x08 Mask Register High */ + u32 imrl1; /* 0x0C Mask Register Low */ + u32 frch1; /* 0x10 Force Register High */ + u32 frcl1; /* 0x14 Force Register Low */ + u16 res1; /* 0x18 */ + u16 icfg1; /* 0x1A Configuration Register */ + u8 simr1; /* 0x1C Set Interrupt Mask */ + u8 cimr1; /* 0x1D Clear Interrupt Mask */ + u16 res2; /* 0x1E - 0x1F */ + u32 res3[8]; /* 0x20 - 0x3F */ + u8 icr1[64]; /* 0x40 - 0x7F */ + u32 res4[24]; /* 0x80 - 0xDF */ + u8 swiack1; /* 0xE0 Software Interrupt ack */ + u8 res5[3]; /* 0xE1 - 0xE3 */ + u8 Lniack1_1; /* 0xE4 Level n interrupt ack */ + u8 res6[3]; /* 0xE5 - 0xE7 */ + u8 Lniack1_2; /* 0xE8 Level n interrupt ack */ + u8 res7[3]; /* 0xE9 - 0xEB */ + u8 Lniack1_3; /* 0xEC Level n interrupt ack */ + u8 res8[3]; /* 0xED - 0xEF */ + u8 Lniack1_4; /* 0xF0 Level n interrupt ack */ + u8 res9[3]; /* 0xF1 - 0xF3 */ + u8 Lniack1_5; /* 0xF4 Level n interrupt ack */ + u8 resa[3]; /* 0xF5 - 0xF7 */ + u8 Lniack1_6; /* 0xF8 Level n interrupt ack */ + u8 resb[3]; /* 0xF9 - 0xFB */ + u8 Lniack1_7; /* 0xFC Level n interrupt ack */ + u8 resc[3]; /* 0xFD - 0xFF */ +} int1_t; + +/* Global Interrupt Acknowledge (IACK) */ +typedef struct iack { + u8 resv0[0xE0]; + u8 gswiack; + u8 resv1[0x3]; + u8 gl1iack; + u8 resv2[0x3]; + u8 gl2iack; + u8 resv3[0x3]; + u8 gl3iack; + u8 resv4[0x3]; + u8 gl4iack; + u8 resv5[0x3]; + u8 gl5iack; + u8 resv6[0x3]; + u8 gl6iack; + u8 resv7[0x3]; + u8 gl7iack; +} iack_t; + +/* Edge Port Module (EPORT) */ +typedef struct eport { + u16 eppar; + u8 epddr; + u8 epier; + u8 epdr; + u8 eppdr; + u8 epfr; +} eport_t; + +/* Reset Controller Module (RCM) */ +typedef struct rcm { + u8 rcr; + u8 rsr; +} rcm_t; + +/* Chip Configuration Module (CCM) */ +typedef struct ccm { + u16 ccr; /* Chip Configuration (Rd-only) */ + u16 resv1; + u16 rcon; /* Reset Configuration (Rd-only) */ + u16 cir; /* Chip Identification (Rd-only) */ + u32 resv2; + u16 misccr; /* Miscellaneous Control */ + u16 cdr; /* Clock Divider */ + u16 uocsr; /* USB On-the-Go Controller Status */ + u16 resv4; + u16 sbfsr; /* Serial Boot Status */ + u16 sbfcr; /* Serial Boot Control */ +} ccm_t; + +/* General Purpose I/O Module (GPIO) */ +typedef struct gpio { + /* Port Output Data Registers */ + u8 podr_be; /* 0x00 */ + u8 podr_cs; /* 0x01 */ + u8 podr_fbctl; /* 0x02 */ + u8 podr_i2c; /* 0x03 */ + u8 rsvd1; /* 0x04 */ + u8 podr_uart; /* 0x05 */ + u8 podr_dspi; /* 0x06 */ + u8 podr_timer; /* 0x07 */ + u8 podr_lcdctl; /* 0x08 */ + u8 podr_lcddatah; /* 0x09 */ + u8 podr_lcddatam; /* 0x0A */ + u8 podr_lcddatal; /* 0x0B */ + + /* Port Data Direction Registers */ + u8 pddr_be; /* 0x0C */ + u8 pddr_cs; /* 0x0D */ + u8 pddr_fbctl; /* 0x0E */ + u8 pddr_i2c; /* 0x0F */ + u8 rsvd2; /* 0x10 */ + u8 pddr_uart; /* 0x11 */ + u8 pddr_dspi; /* 0x12 */ + u8 pddr_timer; /* 0x13 */ + u8 pddr_lcdctl; /* 0x14 */ + u8 pddr_lcddatah; /* 0x15 */ + u8 pddr_lcddatam; /* 0x16 */ + u8 pddr_lcddatal; /* 0x17 */ + + /* Port Pin Data/Set Data Registers */ + u8 ppdsdr_be; /* 0x18 */ + u8 ppdsdr_cs; /* 0x19 */ + u8 ppdsdr_fbctl; /* 0x1A */ + u8 ppdsdr_i2c; /* 0x1B */ + u8 rsvd3; /* 0x1C */ + u8 ppdsdr_uart; /* 0x1D */ + u8 ppdsdr_dspi; /* 0x1E */ + u8 ppdsdr_timer; /* 0x1F */ + u8 ppdsdr_lcdctl; /* 0x20 */ + u8 ppdsdr_lcddatah; /* 0x21 */ + u8 ppdsdr_lcddatam; /* 0x22 */ + u8 ppdsdr_lcddatal; /* 0x23 */ + + /* Port Clear Output Data Registers */ + u8 pclrr_be; /* 0x24 */ + u8 pclrr_cs; /* 0x25 */ + u8 pclrr_fbctl; /* 0x26 */ + u8 pclrr_i2c; /* 0x27 */ + u8 rsvd4; /* 0x28 */ + u8 pclrr_uart; /* 0x29 */ + u8 pclrr_dspi; /* 0x2A */ + u8 pclrr_timer; /* 0x2B */ + u8 pclrr_lcdctl; /* 0x2C */ + u8 pclrr_lcddatah; /* 0x2D */ + u8 pclrr_lcddatam; /* 0x2E */ + u8 pclrr_lcddatal; /* 0x2F */ + + /* Pin Assignment Registers */ + u8 par_be; /* 0x30 */ + u8 par_cs; /* 0x31 */ + u8 par_fbctl; /* 0x32 */ + u8 par_i2c; /* 0x33 */ + u16 par_uart; /* 0x34 */ + u8 par_dspi; /* 0x36 */ + u8 par_timer; /* 0x37 */ + u8 par_lcdctl; /* 0x38 */ + u8 par_irq; /* 0x39 */ + u16 rsvd6; /* 0x3A - 0x3B */ + u32 par_lcdh; /* 0x3C */ + u32 par_lcdl; /* 0x40 */ + + /* Mode select control registers */ + u8 mscr_fb; /* 0x44 */ + u8 mscr_sdram; /* 0x45 */ + + u16 rsvd7; /* 0x46 - 0x47 */ + u8 dscr_dspi; /* 0x48 */ + u8 dscr_timer; /* 0x49 */ + u8 dscr_i2c; /* 0x4A */ + u8 dscr_lcd; /* 0x4B */ + u8 dscr_debug; /* 0x4C */ + u8 dscr_clkrst; /* 0x4D */ + u8 dscr_irq; /* 0x4E */ + u8 dscr_uart; /* 0x4F */ +} gpio_t; + +/* SDRAM Controller (SDRAMC) */ +typedef struct sdramc { + u32 sdmr; /* Mode/Extended Mode */ + u32 sdcr; /* Control */ + u32 sdcfg1; /* Configuration 1 */ + u32 sdcfg2; /* Chip Select */ + u8 resv0[0x100]; + u32 sdcs0; /* Mode/Extended Mode */ + u32 sdcs1; /* Mode/Extended Mode */ +} sdramc_t; + +/* Phase Locked Loop (PLL) */ +typedef struct pll { + u32 pcr; /* PLL Control */ + u32 psr; /* PLL Status */ +} pll_t; + +/* System Control Module register */ +typedef struct scm1 { + u32 mpr; /* 0x00 Master Privilege */ + u32 rsvd1[7]; + u32 pacra; /* 0x20 */ + u32 pacrb; /* 0x24 */ + u32 pacrc; /* 0x28 */ + u32 pacrd; /* 0x2C */ + u32 rsvd2[4]; + u32 pacre; /* 0x40 */ + u32 pacrf; /* 0x44 */ + u32 pacrg; /* 0x48 */ + u32 rsvd3; + u32 pacri; /* 0x50 */ +} scm1_t; + +typedef struct scm2_ctrl { + u8 res1[3]; /* 0x00 - 0x02 */ + u8 wcr; /* 0x03 wakeup control */ + u16 res2; /* 0x04 - 0x05 */ + u16 cwcr; /* 0x06 Core Watchdog Control */ + u8 res3[3]; /* 0x08 - 0x0A */ + u8 cwsr; /* 0x0B Core Watchdog Service */ + u8 res4[2]; /* 0x0C - 0x0D */ + u8 scmisr; /* 0x0F Interrupt Status */ + u32 res5; /* 0x20 */ + u32 bcr; /* 0x24 Burst Configuration */ +} scm2_t; + +typedef struct scm3_ctrl { + u32 cfadr; /* 0x00 Core Fault Address */ + u8 res7; /* 0x04 */ + u8 cfier; /* 0x05 Core Fault Interrupt Enable */ + u8 cfloc; /* 0x06 Core Fault Location */ + u8 cfatr; /* 0x07 Core Fault Attributes */ + u32 cfdtr; /* 0x08 Core Fault Data */ +} scm3_t; + +typedef struct rtcex { + u32 rsvd1[3]; + u32 gocu; + u32 gocl; +} rtcex_t; +#endif /* __IMMAP_5227X__ */ -- cgit v1.2.3 From 570c0186aecab1b747b2d44d0e1d3c1ac4cb27f5 Mon Sep 17 00:00:00 2001 From: TsiChungLiew Date: Tue, 15 Jan 2008 13:37:34 -0600 Subject: ColdFire: Add MCF547x_8x cpu arch Signed-off-by: TsiChungLiew Signed-off by: John Rigby --- cpu/mcf547x_8x/Makefile | 48 ++++++ cpu/mcf547x_8x/config.mk | 31 ++++ cpu/mcf547x_8x/cpu.c | 143 ++++++++++++++++++ cpu/mcf547x_8x/cpu_init.c | 132 ++++++++++++++++ cpu/mcf547x_8x/interrupts.c | 50 ++++++ cpu/mcf547x_8x/pci.c | 167 ++++++++++++++++++++ cpu/mcf547x_8x/slicetimer.c | 112 ++++++++++++++ cpu/mcf547x_8x/speed.c | 43 ++++++ cpu/mcf547x_8x/start.S | 361 ++++++++++++++++++++++++++++++++++++++++++++ 9 files changed, 1087 insertions(+) create mode 100644 cpu/mcf547x_8x/Makefile create mode 100644 cpu/mcf547x_8x/config.mk create mode 100644 cpu/mcf547x_8x/cpu.c create mode 100644 cpu/mcf547x_8x/cpu_init.c create mode 100644 cpu/mcf547x_8x/interrupts.c create mode 100644 cpu/mcf547x_8x/pci.c create mode 100644 cpu/mcf547x_8x/slicetimer.c create mode 100644 cpu/mcf547x_8x/speed.c create mode 100644 cpu/mcf547x_8x/start.S (limited to 'cpu') diff --git a/cpu/mcf547x_8x/Makefile b/cpu/mcf547x_8x/Makefile new file mode 100644 index 000000000..e12bef12c --- /dev/null +++ b/cpu/mcf547x_8x/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = lib$(CPU).a + +START = +COBJS = cpu.o speed.o cpu_init.o pci.o interrupts.o slicetimer.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mcf547x_8x/config.mk b/cpu/mcf547x_8x/config.mk new file mode 100644 index 000000000..e5f4385dd --- /dev/null +++ b/cpu/mcf547x_8x/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003 Josef Baumgartner +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data +ifeq ($(findstring 4.2,$(shell $(CC) --version)),4.2) +PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC +else +PLATFORM_CPPFLAGS += -m5407 -fPIC +endif diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c new file mode 100644 index 000000000..528bca6bf --- /dev/null +++ b/cpu/mcf547x_8x/cpu.c @@ -0,0 +1,143 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#include + +DECLARE_GLOBAL_DATA_PTR; + +int do_reset(cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[]) +{ + volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + + gptmr->pre = 10; + gptmr->cnt = 1; + + /* enable watchdog, set timeout to 0 and wait */ + gptmr->mode = GPT_TMS_SGPIO; + gptmr->ctrl = GPT_CTRL_WDEN | GPT_CTRL_CE; + + /* we don't return! */ + return 1; +}; + +int checkcpu(void) +{ + volatile siu_t *siu = (siu_t *) MMAP_SIU; + u16 id = 0; + + puts("CPU: "); + + switch ((siu->jtagid & 0x000FF000) >> 12) { + case 0x0C: + id = 5485; + break; + case 0x0D: + id = 5484; + break; + case 0x0E: + id = 5483; + break; + case 0x0F: + id = 5482; + break; + case 0x10: + id = 5481; + break; + case 0x11: + id = 5480; + break; + case 0x12: + id = 5475; + break; + case 0x13: + id = 5474; + break; + case 0x14: + id = 5473; + break; + case 0x15: + id = 5472; + break; + case 0x16: + id = 5471; + break; + case 0x17: + id = 5470; + break; + } + + if (id) { + printf("Freescale MCF%d\n", id); + printf(" CPU CLK %d Mhz BUS CLK %d Mhz\n", + (int)(gd->cpu_clk / 1000000), + (int)(gd->bus_clk / 1000000)); + } + + return 0; +}; + +#if defined(CONFIG_HW_WATCHDOG) +/* Called by macro WATCHDOG_RESET */ +void hw_watchdog_reset(void) +{ + volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + + gptmr->ocpw = 0xa5; +} + +int watchdog_disable(void) +{ + volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + + /* UserManual, once the wdog is disabled, wdog cannot be re-enabled */ + gptmr->mode = 0; + gptmr->ctrl = 0; + + puts("WATCHDOG:disabled\n"); + + return (0); +} + +int watchdog_init(void) +{ + + volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR); + + gptmr->pre = CONFIG_WATCHDOG_TIMEOUT; + gptmr->cnt = CFG_TIMER_PRESCALER * 1000; + + gptmr->mode = GPT_TMS_SGPIO; + gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN; + puts("WATCHDOG:enabled\n"); + + return (0); +} +#endif /* CONFIG_HW_WATCHDOG */ diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c new file mode 100644 index 000000000..11154c63a --- /dev/null +++ b/cpu/mcf547x_8x/cpu_init.c @@ -0,0 +1,132 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + * initialize the UPM's + */ +void cpu_init_f(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS; + volatile xlbarb_t *xlbarb = (volatile xlbarb_t *) MMAP_XARB; + + xlbarb->adrto = 0x2000; + xlbarb->datto = 0x2000; + xlbarb->busto = 0x3000; + + xlbarb->cfg = XARB_SR_AT | XARB_SR_DT; + + /* Master Priority Enable */ + xlbarb->pri = 0; + xlbarb->prien = 0xff; + +#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL)) + fbcs->csar0 = CFG_CS0_BASE; + fbcs->cscr0 = CFG_CS0_CTRL; + fbcs->csmr0 = CFG_CS0_MASK; +#endif + +#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL)) + fbcs->csar1 = CFG_CS1_BASE; + fbcs->cscr1 = CFG_CS1_CTRL; + fbcs->csmr1 = CFG_CS1_MASK; +#endif + +#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL)) + fbcs->csar2 = CFG_CS2_BASE; + fbcs->cscr2 = CFG_CS2_CTRL; + fbcs->csmr2 = CFG_CS2_MASK; +#endif + +#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL)) + fbcs->csar3 = CFG_CS3_BASE; + fbcs->cscr3 = CFG_CS3_CTRL; + fbcs->csmr3 = CFG_CS3_MASK; +#endif + +#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL)) + fbcs->csar4 = CFG_CS4_BASE; + fbcs->cscr4 = CFG_CS4_CTRL; + fbcs->csmr4 = CFG_CS4_MASK; +#endif + +#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL)) + fbcs->csar5 = CFG_CS5_BASE; + fbcs->cscr5 = CFG_CS5_CTRL; + fbcs->csmr5 = CFG_CS5_MASK; +#endif + +#ifdef CONFIG_FSL_I2C + gpio->par_feci2cirq = GPIO_PAR_FECI2CIRQ_SCL | GPIO_PAR_FECI2CIRQ_SDA; +#endif + + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ +#if defined(CONFIG_CMD_NET) && defined(CONFIG_FSLDMAFEC) + MCD_initDma((dmaRegs *) (MMAP_MCDMA), (void *)(MMAP_SRAM + 512), + MCD_RELOC_TASKS); +#endif + return (0); +} + +void uart_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + volatile u8 *pscsicr = (u8 *) (CFG_UART_BASE + 0x40); + + /* Setup Ports: */ + switch (CFG_UART_PORT) { + case 0: + gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0); + break; + case 1: + gpio->par_psc1 = (GPIO_PAR_PSC1_TXD1 | GPIO_PAR_PSC1_RXD1); + break; + case 2: + gpio->par_psc2 = (GPIO_PAR_PSC2_TXD2 | GPIO_PAR_PSC2_RXD2); + break; + case 3: + gpio->par_psc3 = (GPIO_PAR_PSC3_TXD3 | GPIO_PAR_PSC3_RXD3); + break; + } + + *pscsicr &= 0xF8; +} diff --git a/cpu/mcf547x_8x/interrupts.c b/cpu/mcf547x_8x/interrupts.c new file mode 100644 index 000000000..d684ffe9d --- /dev/null +++ b/cpu/mcf547x_8x/interrupts.c @@ -0,0 +1,50 @@ +/* + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* CPU specific interrupt routine */ +#include +#include + +int interrupt_init(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + /* Make sure all interrupts are disabled */ + intp->imrh0 |= 0xFFFFFFFF; + intp->imrl0 |= 0xFFFFFFFF; + + enable_interrupts(); + + return 0; +} + +#if defined(CONFIG_SLTTMR) +void dtimer_intr_setup(void) +{ + volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE); + + intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI; + intp->imrh0 &= ~CFG_TMRINTR_MASK; +} +#endif diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c new file mode 100644 index 000000000..70378b09e --- /dev/null +++ b/cpu/mcf547x_8x/pci.c @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * PCI Configuration space access support + */ +#include +#include +#include +#include + +#if defined(CONFIG_PCI) +/* System RAM mapped over PCI */ +#define CFG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CFG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define cfg_read(val, addr, type, op) *val = op((type)(addr)); +#define cfg_write(val, addr, type, op) op((type *)(addr), (val)); + +#define PCI_OP(rw, size, type, op, mask) \ +int pci_##rw##_cfg_##size(struct pci_controller *hose, \ + pci_dev_t dev, int offset, type val) \ +{ \ + u32 addr = 0; \ + u16 cfg_type = 0; \ + addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ + out_be32(hose->cfg_addr, addr); \ + cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ + __asm__ __volatile__("nop"); \ + __asm__ __volatile__("nop"); \ + out_be32(hose->cfg_addr, addr & 0x7fffffff); \ + return 0; \ +} + +PCI_OP(read, byte, u8 *, in_8, 3) +PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(write, byte, u8, out_8, 3) +PCI_OP(write, word, u16, out_le16, 2) +PCI_OP(write, dword, u32, out_le32, 0) + +int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, + int offset, u32 * val) +{ + u32 addr; + u32 tmpv; + u32 mask = 2; /* word access */ + /* Read lower 16 bits */ + addr = ((offset & 0xfc) | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + __asm__ __volatile__("nop"); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + + /* Read upper 16 bits */ + offset += 2; + addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); + out_be32(hose->cfg_addr, addr); + tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); + __asm__ __volatile__("nop"); + out_be32(hose->cfg_addr, addr & 0x7fffffff); + + /* combine results into dword value */ + *val = (tmpv << 16) | *val; + + return 0; +} + +void pci_mcf547x_8x_init(struct pci_controller *hose) +{ + volatile pci_t *pci = (volatile pci_t *) MMAP_PCI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + /* Port configuration */ + gpio->par_pcibg = + GPIO_PAR_PCIBG_PCIBG0(3) | GPIO_PAR_PCIBG_PCIBG1(3) | + GPIO_PAR_PCIBG_PCIBG2(3) | GPIO_PAR_PCIBG_PCIBG3(3) | + GPIO_PAR_PCIBG_PCIBG4(3); + gpio->par_pcibr = + GPIO_PAR_PCIBR_PCIBR0(3) | GPIO_PAR_PCIBR_PCIBR1(3) | + GPIO_PAR_PCIBR_PCIBR2(3) | GPIO_PAR_PCIBR_PCIBR3(3) | + GPIO_PAR_PCIBR_PCIBR4(3); + + /* Assert reset bit */ + pci->gscr |= PCI_GSCR_PR; + + pci->tcr1 = PCI_TCR1_P; + + /* Initiator windows */ + pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); + pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); + pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16); + + pci->iwcr = + PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | + PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO; + + pci->icr = 0; + + /* Enable bus master and mem access */ + pci->scr = PCI_SCR_B | PCI_SCR_M; + + /* Cache line size and master latency */ + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); + pci->cr2 = 0; + +#ifdef CFG_PCI_BAR0 + pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); + pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN; +#endif +#ifdef CFG_PCI_BAR1 + pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); + pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN; +#endif + + /* Deassert reset bit */ + pci->gscr &= ~PCI_GSCR_PR; + udelay(1000); + + /* Enable PCI bus master support */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS, + CFG_PCI_MEM_SIZE, PCI_REGION_MEM); + + pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS, + CFG_PCI_IO_SIZE, PCI_REGION_IO); + + pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS, + CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + hose->region_count = 3; + + hose->cfg_addr = &(pci->car); + hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS; + + pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word, + pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word, + pci_write_cfg_dword); + + /* Hose scan */ + pci_register_hose(hose); + hose->last_busno = pci_hose_scan(hose); +} +#endif /* CONFIG_PCI */ diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c new file mode 100644 index 000000000..494f98f66 --- /dev/null +++ b/cpu/mcf547x_8x/slicetimer.c @@ -0,0 +1,112 @@ +/* + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static ulong timestamp; + +#if defined(CONFIG_SLTTMR) +#ifndef CFG_UDELAY_BASE +# error "uDelay base not defined!" +#endif + +#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK) +# error "TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!" +#endif +extern void dtimer_intr_setup(void); + +void udelay(unsigned long usec) +{ + volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE); + u32 now, freq; + + /* 1 us period */ + freq = CFG_TIMER_PRESCALER; + + timerp->cr = 0; /* Disable */ + timerp->tcnt = usec * freq; + timerp->cr = SLT_CR_TEN; + + now = timerp->cnt; + while (now != 0) + now = timerp->cnt; + + timerp->sr |= SLT_SR_ST; + timerp->cr = 0; +} + +void dtimer_interrupt(void *not_used) +{ + volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + + /* check for timer interrupt asserted */ + if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) { + timerp->sr |= SLT_SR_ST; + timestamp++; + return; + } +} + +void timer_init(void) +{ + volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE); + + timestamp = 0; + + timerp->cr = 0; /* disable timer */ + timerp->tcnt = 0; + timerp->sr = SLT_SR_BE | SLT_SR_ST; /* clear status */ + + /* initialize and enable timer interrupt */ + irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0); + + /* Interrupt every ms */ + timerp->tcnt = 1000 * CFG_TIMER_PRESCALER; + + dtimer_intr_setup(); + + /* set a period of 1us, set timer mode to restart and + enable timer and interrupt */ + timerp->cr = SLT_CR_RUN | SLT_CR_IEN | SLT_CR_TEN; +} + +void reset_timer(void) +{ + timestamp = 0; +} + +ulong get_timer(ulong base) +{ + return (timestamp - base); +} + +void set_timer(ulong t) +{ + timestamp = t; +} +#endif /* CONFIG_SLTTMR */ diff --git a/cpu/mcf547x_8x/speed.c b/cpu/mcf547x_8x/speed.c new file mode 100644 index 000000000..389e7c99f --- /dev/null +++ b/cpu/mcf547x_8x/speed.c @@ -0,0 +1,43 @@ +/* + * + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include + +/* + * get_clocks() fills in gd->cpu_clock and gd->bus_clk + */ +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bus_clk = CFG_CLK; + gd->cpu_clk = (gd->bus_clk * 2); + return (0); +} diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S new file mode 100644 index 000000000..442665f25 --- /dev/null +++ b/cpu/mcf547x_8x/start.S @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2003 Josef Baumgartner + * Based on code from Bernhard Kuhn + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include "version.h" + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +/* last three long word reserved for cache status */ +#define ICACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4) +#define DCACHE_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8) +#define CACR_STATUS (CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12) + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte; + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ +vector02: .long _FAULT /* Access Error */ +vector03: .long _FAULT /* Address Error */ +vector04: .long _FAULT /* Illegal Instruction */ +vector05: .long _FAULT /* Reserved */ +vector06: .long _FAULT /* Reserved */ +vector07: .long _FAULT /* Reserved */ +vector08: .long _FAULT /* Privilege Violation */ +vector09: .long _FAULT /* Trace */ +vector0A: .long _FAULT /* Unimplemented A-Line */ +vector0B: .long _FAULT /* Unimplemented F-Line */ +vector0C: .long _FAULT /* Debug Interrupt */ +vector0D: .long _FAULT /* Reserved */ +vector0E: .long _FAULT /* Format Error */ +vector0F: .long _FAULT /* Unitialized Int. */ + +/* Reserved */ +vector10_17: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector18: .long _FAULT /* Spurious Interrupt */ +vector19: .long _FAULT /* Autovector Level 1 */ +vector1A: .long _FAULT /* Autovector Level 2 */ +vector1B: .long _FAULT /* Autovector Level 3 */ +vector1C: .long _FAULT /* Autovector Level 4 */ +vector1D: .long _FAULT /* Autovector Level 5 */ +vector1E: .long _FAULT /* Autovector Level 6 */ +vector1F: .long _FAULT /* Autovector Level 7 */ + +/* TRAP #0 - #15 */ +vector20_2F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +/* Reserved */ +vector30_3F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector64_127: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector128_191: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +vector192_255: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + + .text + + .globl _start +_start: + nop + nop + move.w #0x2700,%sr /* Mask off Interrupt */ + + /* Set vector base register at the beginning of the Flash */ + move.l #CFG_FLASH_BASE, %d0 + movec %d0, %VBR + + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR0 + + move.l #(CFG_INIT_RAM1_ADDR + CFG_INIT_RAM1_CTRL), %d0 + movec %d0, %RAMBAR1 + + move.l #CFG_MBAR, %d0 /* set MBAR address */ + move.c %d0, %MBAR + + /* invalidate and disable cache */ + move.l #0x01040100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + movec %d0, %ACR2 + movec %d0, %ACR3 + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l #(CACR_STATUS), %a3 /* CACR */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) + + /* set stackpointer to end of internal ram to get some stackspace for the + first c-code */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CFG_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CFG_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CFG_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CFG_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CFG_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CFG_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CFG_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + .globl _exc_handler + +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ +/* cache functions */ + .globl icache_enable +icache_enable: + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 + movec %d0, %ACR2 /* Enable cache */ + + move.l #0x020C8100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop + + move.l #(ICACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl icache_disable +icache_disable: + move.l #0x000C8100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR2 + movec %d0, %ACR3 + + move.l #(ICACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl icache_invalid +icache_invalid: + move.l #0x000C8100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + rts + + .globl icache_status +icache_status: + move.l #(ICACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + + .globl dcache_enable +dcache_enable: + bsr icache_disable + + move.l #(CFG_SDRAM_BASE + 0xc000), %d0 + movec %d0, %ACR0 /* Enable cache */ + + move.l #0xA30C8100, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + + move.l #(DCACHE_STATUS), %a1 + moveq #1, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_disable +dcache_disable: + move.l #0xA30C8100, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Disable cache */ + clr.l %d0 /* Setup cache mask */ + movec %d0, %ACR0 + movec %d0, %ACR1 + + move.l #(DCACHE_STATUS), %a1 + moveq #0, %d0 + move.l %d0, (%a1) + rts + + .globl dcache_status +dcache_status: + move.l #(DCACHE_STATUS), %a1 + move.l (%a1), %d0 + rts + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii CONFIG_IDENT_STRING, "\0" -- cgit v1.2.3